diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
82 files changed, 1435 insertions, 280 deletions
diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll index 6c23a61..8d5ea8a 100644 --- a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll +++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll @@ -5,7 +5,7 @@ target triple = "powerpc-apple-darwin9.6" define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind { entry: -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: subfc ; CHECK: subfe ; CHECK: subfc diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll index d1a3c9f..a25ce07 100644 --- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll +++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll @@ -6,7 +6,7 @@ target triple = "powerpc-apple-darwin9.8" define i32 @main() nounwind { entry: ; Make sure we're generating references using the red zone -; CHECK: main: +; CHECK-LABEL: main: ; CHECK: stw r2, -12(r1) %retval = alloca i32 %0 = alloca i32 diff --git a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll index a18829e..b1cbb36 100644 --- a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll +++ b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll @@ -9,7 +9,7 @@ entry: store i64 %z2, i64* %xx, align 4 ret void -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: sldi {{.*}}, {{.*}}, 32 ; Note: it's okay if someday CodeGen gets smart enough to optimize out ; the shift. diff --git a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll new file mode 100644 index 0000000..635062b --- /dev/null +++ b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -verify-machineinstrs | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@g_51 = external global [8 x i32], align 4 + +; CHECK: func_7 + +; Function Attrs: nounwind +define fastcc void @func_7() #0 { +entry: + %arrayidx638 = getelementptr inbounds [3 x [1 x i32]]* undef, i64 0, i64 1, i64 0 + br i1 undef, label %for.cond940, label %if.end1018 + +for.cond940: ; preds = %for.cond940, %if.else876 + %l_655.1 = phi i32* [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ], [ %l_654.0, %for.cond940 ] + %l_654.0 = phi i32* [ null, %entry ], [ %arrayidx638, %for.cond940 ] + %exitcond = icmp eq i32 undef, 20 + br i1 %exitcond, label %if.end1018, label %for.cond940 + +if.end1018: ; preds = %for.end957, %for.end834 + %l_655.3.ph33 = phi i32* [ %l_655.1, %for.cond940 ], [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ] + store i32 0, i32* %l_655.3.ph33, align 4 + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll index 8c928ce..500d126 100644 --- a/test/CodeGen/PowerPC/addc.ll +++ b/test/CodeGen/PowerPC/addc.ll @@ -5,7 +5,7 @@ define i64 @add_ll(i64 %a, i64 %b) nounwind { entry: %tmp.2 = add i64 %b, %a ; <i64> [#uses=1] ret i64 %tmp.2 -; CHECK: add_ll: +; CHECK-LABEL: add_ll: ; CHECK: addc r4, r6, r4 ; CHECK: adde r3, r5, r3 ; CHECK: blr @@ -15,7 +15,7 @@ define i64 @add_l_5(i64 %a) nounwind { entry: %tmp.1 = add i64 %a, 5 ; <i64> [#uses=1] ret i64 %tmp.1 -; CHECK: add_l_5: +; CHECK-LABEL: add_l_5: ; CHECK: addic r4, r4, 5 ; CHECK: addze r3, r3 ; CHECK: blr @@ -25,7 +25,7 @@ define i64 @add_l_m5(i64 %a) nounwind { entry: %tmp.1 = add i64 %a, -5 ; <i64> [#uses=1] ret i64 %tmp.1 -; CHECK: add_l_m5: +; CHECK-LABEL: add_l_m5: ; CHECK: addic r4, r4, -5 ; CHECK: addme r3, r3 ; CHECK: blr diff --git a/test/CodeGen/PowerPC/altivec-ord.ll b/test/CodeGen/PowerPC/altivec-ord.ll new file mode 100644 index 0000000..6aea843 --- /dev/null +++ b/test/CodeGen/PowerPC/altivec-ord.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define <4 x i16> @test(<4 x float> %f, <4 x float> %g) { +entry: + %r = fcmp ord <4 x float> %f, %g + %s = sext <4 x i1> %r to <4 x i16> + ret <4 x i16> %s +} + +define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) { +entry: + %r = fcmp one <4 x float> %f, %g + %s = sext <4 x i1> %r to <4 x i16> + ret <4 x i16> %s +} + diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index 78c0911..1525e05 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s ; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s @@ -20,10 +20,10 @@ unequal: ret i8* %ptr } -; CHECK: func1: +; CHECK-LABEL: func1: ; CHECK: cmpld {{[0-9]+}}, 4, 5 -; CHECK: std 4, -[[OFFSET1:[0-9]+]] -; CHECK: std 5, -[[OFFSET2:[0-9]+]] +; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]] +; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) @@ -61,12 +61,12 @@ unequal: ret i8* %array2_ptr } -; CHECK: func2: +; CHECK-LABEL: func2: ; CHECK: addi [[REG1:[0-9]+]], 1, 64 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]]) ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]] -; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]] -; CHECK: std 4, -[[OFFSET2:[0-9]+]] +; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]] +; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) @@ -107,7 +107,7 @@ unequal: ret i8* %array2_ptr } -; CHECK: func3: +; CHECK-LABEL: func3: ; CHECK: addi [[REG1:[0-9]+]], 1, 64 ; CHECK: addi [[REG2:[0-9]+]], 1, 48 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) @@ -156,7 +156,7 @@ unequal: ret i8* %array2_ptr } -; CHECK: func4: +; CHECK-LABEL: func4: ; CHECK: addi [[REG1:[0-9]+]], 1, 128 ; CHECK: ld [[REG2:[0-9]+]], 120(1) ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) diff --git a/test/CodeGen/PowerPC/ashr-neg1.ll b/test/CodeGen/PowerPC/ashr-neg1.ll new file mode 100644 index 0000000..28e74f4 --- /dev/null +++ b/test/CodeGen/PowerPC/ashr-neg1.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD30723(i32) { +BB: + br label %CF80 + +CF80: ; preds = %CF80, %BB + %B = ashr i32 %0, -1 + br i1 undef, label %CF80, label %CF84 + +CF84: ; preds = %CF84, %CF80 + %Cmp62 = icmp sge i32 undef, %B + br i1 %Cmp62, label %CF84, label %CF85 + +CF85: ; preds = %CF85, %CF84 + br label %CF85 +} diff --git a/test/CodeGen/PowerPC/asm-dialect.ll b/test/CodeGen/PowerPC/asm-dialect.ll new file mode 100644 index 0000000..e8fd251 --- /dev/null +++ b/test/CodeGen/PowerPC/asm-dialect.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s + +; This test verifies that we choose "assembler variant 1" (which GCC +; uses for "new-style mnemonics" as opposed to POWER mnemonics) when +; processing multi-variant inline asm statements, on all subtargets. + +; CHECK: subfe +; CHECK-NOT: sfe + +define i32 @test(i32 %in1, i32 %in2) { +entry: + %0 = tail call i32 asm "$(sfe$|subfe$) $0,$1,$2", "=r,r,r"(i32 %in1, i32 %in2) + ret i32 %0 +} + diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index 838db20..1737916 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { -; CHECK: exchange_and_add: +; CHECK-LABEL: exchange_and_add: ; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}} %tmp = atomicrmw add i32* %mem, i32 %val monotonic ; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}} @@ -9,7 +9,7 @@ define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { } define i32 @exchange_and_cmp(i32* %mem) nounwind { -; CHECK: exchange_and_cmp: +; CHECK-LABEL: exchange_and_cmp: ; CHECK: lwarx %tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic ; CHECK: stwcx. @@ -18,7 +18,7 @@ define i32 @exchange_and_cmp(i32* %mem) nounwind { } define i32 @exchange(i32* %mem, i32 %val) nounwind { -; CHECK: exchange: +; CHECK-LABEL: exchange: ; CHECK: lwarx %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic ; CHECK: stwcx. diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 40b4a2e..e56a779 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=ppc64 | FileCheck %s define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { -; CHECK: exchange_and_add: +; CHECK-LABEL: exchange_and_add: ; CHECK: ldarx %tmp = atomicrmw add i64* %mem, i64 %val monotonic ; CHECK: stdcx. @@ -9,7 +9,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { } define i64 @exchange_and_cmp(i64* %mem) nounwind { -; CHECK: exchange_and_cmp: +; CHECK-LABEL: exchange_and_cmp: ; CHECK: ldarx %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic ; CHECK: stdcx. @@ -18,7 +18,7 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind { } define i64 @exchange(i64* %mem, i64 %val) nounwind { -; CHECK: exchange: +; CHECK-LABEL: exchange: ; CHECK: ldarx %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic ; CHECK: stdcx. diff --git a/test/CodeGen/PowerPC/bv-pres-v8i1.ll b/test/CodeGen/PowerPC/bv-pres-v8i1.ll new file mode 100644 index 0000000..5bf84ed --- /dev/null +++ b/test/CodeGen/PowerPC/bv-pres-v8i1.ll @@ -0,0 +1,39 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD70() { +BB: + br label %CF78 + +CF78: ; preds = %CF87, %CF78, %BB + br i1 undef, label %CF78, label %CF87 + +CF87: ; preds = %CF78 + %Cmp19 = icmp sge <8 x i1> zeroinitializer, zeroinitializer + %Cmp26 = icmp slt i32 -1, undef + br i1 %Cmp26, label %CF78, label %CF79 + +CF79: ; preds = %CF79, %CF87 + br i1 undef, label %CF79, label %CF82 + +CF82: ; preds = %CF82, %CF79 + br i1 undef, label %CF82, label %CF84 + +CF84: ; preds = %CF82 + br label %CF + +CF: ; preds = %CF88, %CF, %CF84 + br i1 undef, label %CF, label %CF85 + +CF85: ; preds = %CF85, %CF + %I52 = insertelement <8 x i1> %Cmp19, i1 %Cmp26, i32 6 + %Cmp61 = icmp ult i32 477567, undef + br i1 %Cmp61, label %CF85, label %CF88 + +CF88: ; preds = %CF85 + %E63 = extractelement <8 x i1> %I52, i32 5 + br i1 %E63, label %CF, label %CF80 + +CF80: ; preds = %CF80, %CF88 + br label %CF80 +} diff --git a/test/CodeGen/PowerPC/bv-widen-undef.ll b/test/CodeGen/PowerPC/bv-widen-undef.ll new file mode 100644 index 0000000..9e58f0d --- /dev/null +++ b/test/CodeGen/PowerPC/bv-widen-undef.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD4357(i8) { +BB: + br label %CF + +CF: ; preds = %CF, %BB + br i1 undef, label %CF, label %CF77 + +CF77: ; preds = %CF81, %CF77, %CF + %Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8 -1>, <2 x i32> <i32 0, i32 undef> + br i1 undef, label %CF77, label %CF80 + +CF80: ; preds = %CF80, %CF77 + %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1> + %Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000 + br i1 %Cmp24, label %CF80, label %CF81 + +CF81: ; preds = %CF80 + %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0 + br label %CF77 +} diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll index f12152f..3eb30e9 100644 --- a/test/CodeGen/PowerPC/complex-return.ll +++ b/test/CodeGen/PowerPC/complex-return.ll @@ -23,7 +23,7 @@ entry: ret { ppc_fp128, ppc_fp128 } %0 } -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: lfd 3 ; CHECK: lfd 4 ; CHECK: lfd 2 @@ -49,7 +49,7 @@ entry: ret { float, float } %0 } -; CHECK: oof: +; CHECK-LABEL: oof: ; CHECK: lfs 2 ; CHECK: lfs 1 diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index b15011d..a9b4b36 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32 +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64 declare void @foo() @@ -18,7 +18,7 @@ entry: ; PPC32: mfcr 12 ; PPC32-NEXT: stw 12, 24(31) ; PPC32: lwz 12, 24(31) -; PPC32-NEXT: mtcrf 32, 12 +; PPC32-NEXT: mtocrf 32, 12 ; PPC64: .cfi_startproc ; PPC64: mfcr 12 @@ -29,7 +29,7 @@ entry: ; PPC64: .cfi_offset cr2, 8 ; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64: mtcrf 32, 12 +; PPC64: mtocrf 32, 12 ; PPC64: .cfi_endproc define i32 @test_cr234() nounwind { @@ -47,16 +47,16 @@ entry: ; PPC32: mfcr 12 ; PPC32-NEXT: stw 12, 24(31) ; PPC32: lwz 12, 24(31) -; PPC32-NEXT: mtcrf 32, 12 -; PPC32-NEXT: mtcrf 16, 12 -; PPC32-NEXT: mtcrf 8, 12 +; PPC32-NEXT: mtocrf 32, 12 +; PPC32-NEXT: mtocrf 16, 12 +; PPC32-NEXT: mtocrf 8, 12 ; PPC64: mfcr 12 ; PPC64: stw 12, 8(1) ; PPC64: stdu 1, -[[AMT:[0-9]+]](1) ; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64: mtcrf 32, 12 -; PPC64: mtcrf 16, 12 -; PPC64: mtcrf 8, 12 +; PPC64: mtocrf 32, 12 +; PPC64: mtocrf 16, 12 +; PPC64: mtocrf 8, 12 diff --git a/test/CodeGen/PowerPC/ctrloop-large-ec.ll b/test/CodeGen/PowerPC/ctrloop-large-ec.ll new file mode 100644 index 0000000..c18bdab --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-large-ec.ll @@ -0,0 +1,23 @@ +; RUN: llc -mcpu=ppc32 < %s +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-linux-gnu" + +define void @fn1() { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ] + %inc = add nsw i64 %inc3, 1 + %tobool = icmp eq i64 %inc, 0 + br i1 %tobool, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count. +; CHECK: @fn1 +; CHECK-NOT: mtctr +; CHECK: blr + diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index 21e3661..30fe19e 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s -; CHECK: main: +; CHECK-LABEL: main: target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -16,17 +16,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 720913, i32 12, metadata !6, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 720913, metadata !21, i32 12, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !"", metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} -!5 = metadata !{i32 720942, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13} ; [ DW_TAG_subprogram ] -!6 = metadata !{i32 720937, metadata !"dbg.c", metadata !"/src", null} ; [ DW_TAG_file_type ] -!7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 720942, metadata !21, null, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13, i32 0} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 720937, metadata !21} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 720917, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !9, metadata !9, metadata !10} -!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!10 = metadata !{i32 720911, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] -!11 = metadata !{i32 720911, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] -!12 = metadata !{i32 720932, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] +!11 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] +!12 = metadata !{i32 720932, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] !13 = metadata !{metadata !14} !14 = metadata !{metadata !15, metadata !16} !15 = metadata !{i32 721153, metadata !5, metadata !"argc", metadata !6, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] @@ -34,5 +34,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !17 = metadata !{i32 1, i32 14, metadata !5, null} !18 = metadata !{i32 1, i32 26, metadata !5, null} !19 = metadata !{i32 2, i32 3, metadata !20, null} -!20 = metadata !{i32 720907, metadata !5, i32 1, i32 34, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] - +!20 = metadata !{i32 720907, metadata !21, metadata !5, i32 1, i32 34, i32 0} ; [ DW_TAG_lexical_block ] +!21 = metadata !{metadata !"dbg.c", metadata !"/src"} diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll new file mode 100644 index 0000000..a18ada7 --- /dev/null +++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll @@ -0,0 +1,39 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.s = type { i32, i32 } + +declare void @bar(i32*, i32*) #0 + +define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 { +entry: + %0 = zext i32 %n to i64 + %vla = alloca i32, i64 %0, align 128 + %vla1 = alloca i32, i64 %0, align 128 + %a2 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %1 = load i32* %a2, align 4, !tbaa !0 + store i32 %1, i32* %vla1, align 128, !tbaa !0 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %2 = load i32* %b, align 4, !tbaa !0 + %arrayidx3 = getelementptr inbounds i32* %vla1, i64 1 + store i32 %2, i32* %arrayidx3, align 4, !tbaa !0 + call void @bar(i32* %vla1, i32* %vla) #0 + ret void + +; CHECK-LABEL: @goo + +; CHECK-DAG: li [[REG1:[0-9]+]], -128 +; CHECK-DAG: neg [[REG2:[0-9]+]], +; CHECK: and [[REG1]], [[REG2]], [[REG1]] +; CHECK: stdux {{[0-9]+}}, 1, [[REG1]] + +; CHECK: blr + +} + +attributes #0 = { nounwind } + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll index 36b4abd..47cfadd 100644 --- a/test/CodeGen/PowerPC/emptystruct.ll +++ b/test/CodeGen/PowerPC/emptystruct.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; This tests correct handling of empty aggregate parameters and return values. ; An empty parameter passed by value does not consume a protocol register or @@ -25,9 +25,8 @@ entry: ret void } -; CHECK: callee: +; CHECK-LABEL: callee: ; CHECK: std 4, -; CHECK: std 3, ; CHECK-NOT: std 5, ; CHECK-NOT: std 6, ; CHECK: blr @@ -43,9 +42,8 @@ entry: ret void } -; CHECK: caller: +; CHECK-LABEL: caller: ; CHECK: addi 4, -; CHECK: std 3, ; CHECK-NOT: std 5, ; CHECK-NOT: std 6, ; CHECK: bl callee diff --git a/test/CodeGen/PowerPC/floatPSA.ll b/test/CodeGen/PowerPC/floatPSA.ll index b5631a1..f14c736 100644 --- a/test/CodeGen/PowerPC/floatPSA.ll +++ b/test/CodeGen/PowerPC/floatPSA.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; This verifies that single-precision floating point values that can't ; be passed in registers are stored in the rightmost word of the parameter diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll index a173c91..db19761 100644 --- a/test/CodeGen/PowerPC/fma.ll +++ b/test/CodeGen/PowerPC/fma.ll @@ -4,7 +4,7 @@ define double @test_FMADD1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fadd double %D, %C ; <double> [#uses=1] ret double %E -; CHECK: test_FMADD1: +; CHECK-LABEL: test_FMADD1: ; CHECK: fmadd ; CHECK-NEXT: blr } @@ -13,7 +13,7 @@ define double @test_FMADD2(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fadd double %D, %C ; <double> [#uses=1] ret double %E -; CHECK: test_FMADD2: +; CHECK-LABEL: test_FMADD2: ; CHECK: fmadd ; CHECK-NEXT: blr } @@ -22,7 +22,7 @@ define double @test_FMSUB(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fsub double %D, %C ; <double> [#uses=1] ret double %E -; CHECK: test_FMSUB: +; CHECK-LABEL: test_FMSUB: ; CHECK: fmsub ; CHECK-NEXT: blr } @@ -32,7 +32,7 @@ define double @test_FNMADD1(double %A, double %B, double %C) { %E = fadd double %D, %C ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F -; CHECK: test_FNMADD1: +; CHECK-LABEL: test_FNMADD1: ; CHECK: fnmadd ; CHECK-NEXT: blr } @@ -42,7 +42,7 @@ define double @test_FNMADD2(double %A, double %B, double %C) { %E = fadd double %C, %D ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F -; CHECK: test_FNMADD2: +; CHECK-LABEL: test_FNMADD2: ; CHECK: fnmadd ; CHECK-NEXT: blr } @@ -51,7 +51,7 @@ define double @test_FNMSUB1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fsub double %C, %D ; <double> [#uses=1] ret double %E -; CHECK: test_FNMSUB1: +; CHECK-LABEL: test_FNMSUB1: ; CHECK: fnmsub ; CHECK-NEXT: blr } @@ -61,7 +61,7 @@ define double @test_FNMSUB2(double %A, double %B, double %C) { %E = fsub double %D, %C ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F -; CHECK: test_FNMSUB2: +; CHECK-LABEL: test_FNMSUB2: ; CHECK: fnmsub ; CHECK-NEXT: blr } @@ -71,7 +71,7 @@ define float @test_FNMSUBS(float %A, float %B, float %C) { %E = fsub float %D, %C ; <float> [#uses=1] %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] ret float %F -; CHECK: test_FNMSUBS: +; CHECK-LABEL: test_FNMSUBS: ; CHECK: fnmsubs ; CHECK-NEXT: blr } diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index 4b6f88b..fd06fd9 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -6,9 +6,9 @@ @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] define internal i32 @foo(i32 %i) nounwind { -; PIC: foo: -; STATIC: foo: -; PPC64: foo: +; PIC-LABEL: foo: +; STATIC-LABEL: foo: +; PPC64-LABEL: foo: entry: %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] %1 = icmp eq i8* %0, null ; <i1> [#uses=1] diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll new file mode 100644 index 0000000..fa9aa45 --- /dev/null +++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll @@ -0,0 +1,65 @@ +; RUN: llc -mtriple=powerpc64-bgq-linux -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +%struct.BG_CoordinateMapping_t = type { [4 x i8] } + +; Function Attrs: alwaysinline inlinehint nounwind +define zeroext i32 @Kernel_RanksToCoords(i64 %mapsize, %struct.BG_CoordinateMapping_t* %map, i64* %numentries) #0 { +entry: + %mapsize.addr = alloca i64, align 8 + %map.addr = alloca %struct.BG_CoordinateMapping_t*, align 8 + %numentries.addr = alloca i64*, align 8 + %r0 = alloca i64, align 8 + %r3 = alloca i64, align 8 + %r4 = alloca i64, align 8 + %r5 = alloca i64, align 8 + %tmp = alloca i64, align 8 + store i64 %mapsize, i64* %mapsize.addr, align 8 + store %struct.BG_CoordinateMapping_t* %map, %struct.BG_CoordinateMapping_t** %map.addr, align 8 + store i64* %numentries, i64** %numentries.addr, align 8 + store i64 1055, i64* %r0, align 8 + %0 = load i64* %mapsize.addr, align 8 + store i64 %0, i64* %r3, align 8 + %1 = load %struct.BG_CoordinateMapping_t** %map.addr, align 8 + %2 = ptrtoint %struct.BG_CoordinateMapping_t* %1 to i64 + store i64 %2, i64* %r4, align 8 + %3 = load i64** %numentries.addr, align 8 + %4 = ptrtoint i64* %3 to i64 + store i64 %4, i64* %r5, align 8 + %5 = load i64* %r0, align 8 + %6 = load i64* %r3, align 8 + %7 = load i64* %r4, align 8 + %8 = load i64* %r5, align 8 + %9 = call { i64, i64, i64, i64 } asm sideeffect "sc", "={r0},={r3},={r4},={r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 %5, i64 %6, i64 %7, i64 %8) #1, !srcloc !0 + +; CHECK-LABEL: @Kernel_RanksToCoords + +; These need to be 64-bit loads, not 32-bit loads (not lwz). +; CHECK-NOT: lwz + +; CHECK: #APP +; CHECK: sc +; CHECK: #NO_APP + +; CHECK: blr + + %asmresult = extractvalue { i64, i64, i64, i64 } %9, 0 + %asmresult1 = extractvalue { i64, i64, i64, i64 } %9, 1 + %asmresult2 = extractvalue { i64, i64, i64, i64 } %9, 2 + %asmresult3 = extractvalue { i64, i64, i64, i64 } %9, 3 + store i64 %asmresult, i64* %r0, align 8 + store i64 %asmresult1, i64* %r3, align 8 + store i64 %asmresult2, i64* %r4, align 8 + store i64 %asmresult3, i64* %r5, align 8 + %10 = load i64* %r3, align 8 + store i64 %10, i64* %tmp + %11 = load i64* %tmp + %conv = trunc i64 %11 to i32 + ret i32 %conv +} + +attributes #0 = { alwaysinline inlinehint nounwind } +attributes #1 = { nounwind } + +!0 = metadata !{i32 -2146895770} diff --git a/test/CodeGen/PowerPC/isel-rc-nox0.ll b/test/CodeGen/PowerPC/isel-rc-nox0.ll new file mode 100644 index 0000000..7d425cc --- /dev/null +++ b/test/CodeGen/PowerPC/isel-rc-nox0.ll @@ -0,0 +1,50 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@g_62 = external global [1 x [9 x i32]], align 4 + +; Function Attrs: nounwind +define void @main() #0 { +entry: + br i1 undef, label %cond.true, label %for.cond1.preheader.i + +cond.true: ; preds = %entry + br label %for.cond1.preheader.i + +for.cond1.preheader.i: ; preds = %for.cond1.preheader.i, %cond.true, %entry + br i1 undef, label %crc32_gentab.exit, label %for.cond1.preheader.i + +crc32_gentab.exit: ; preds = %for.cond1.preheader.i + %tobool.i19.i.i = icmp eq i32 undef, 0 + %retval.0.i.i.i = select i1 %tobool.i19.i.i, i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 6), i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 8) + br label %for.cond1.preheader.i2961.i + +for.cond1.preheader.i2961.i: ; preds = %for.inc44.i2977.i, %crc32_gentab.exit + call void @llvm.memset.p0i8.i64(i8* bitcast ([1 x [9 x i32]]* @g_62 to i8*), i8 -1, i64 36, i32 4, i1 false) #1 + %0 = load i32* %retval.0.i.i.i, align 4, !tbaa !0 + %tobool.i2967.i = icmp eq i32 %0, 0 + br label %for.body21.i2968.i + +for.body21.i2968.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.cond1.preheader.i2961.i + br i1 %tobool.i2967.i, label %safe_mod_func_int32_t_s_s.exit.i2974.i, label %for.inc44.i2977.i + +safe_mod_func_int32_t_s_s.exit.i2974.i: ; preds = %for.body21.i2968.i + br i1 undef, label %for.body21.i2968.i, label %for.inc44.i2977.i + +for.inc44.i2977.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.body21.i2968.i + br i1 undef, label %func_80.exit2978.i, label %for.cond1.preheader.i2961.i + +func_80.exit2978.i: ; preds = %for.inc44.i2977.i + unreachable +} + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/jaggedstructs.ll b/test/CodeGen/PowerPC/jaggedstructs.ll index a10c5dd..82d4fef 100644 --- a/test/CodeGen/PowerPC/jaggedstructs.ll +++ b/test/CodeGen/PowerPC/jaggedstructs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; This tests receiving and re-passing parameters consisting of structures ; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in @@ -18,25 +18,25 @@ entry: ret void } -; CHECK: std 6, 216(1) -; CHECK: std 5, 208(1) -; CHECK: std 4, 200(1) -; CHECK: std 3, 192(1) -; CHECK: lbz {{[0-9]+}}, 199(1) -; CHECK: lhz {{[0-9]+}}, 197(1) +; CHECK: std 6, 184(1) +; CHECK: std 5, 176(1) +; CHECK: std 4, 168(1) +; CHECK: std 3, 160(1) +; CHECK: lbz {{[0-9]+}}, 167(1) +; CHECK: lhz {{[0-9]+}}, 165(1) ; CHECK: stb {{[0-9]+}}, 55(1) ; CHECK: sth {{[0-9]+}}, 53(1) -; CHECK: lbz {{[0-9]+}}, 207(1) -; CHECK: lwz {{[0-9]+}}, 203(1) +; CHECK: lbz {{[0-9]+}}, 175(1) +; CHECK: lwz {{[0-9]+}}, 171(1) ; CHECK: stb {{[0-9]+}}, 63(1) ; CHECK: stw {{[0-9]+}}, 59(1) -; CHECK: lhz {{[0-9]+}}, 214(1) -; CHECK: lwz {{[0-9]+}}, 210(1) +; CHECK: lhz {{[0-9]+}}, 182(1) +; CHECK: lwz {{[0-9]+}}, 178(1) ; CHECK: sth {{[0-9]+}}, 70(1) ; CHECK: stw {{[0-9]+}}, 66(1) -; CHECK: lbz {{[0-9]+}}, 223(1) -; CHECK: lhz {{[0-9]+}}, 221(1) -; CHECK: lwz {{[0-9]+}}, 217(1) +; CHECK: lbz {{[0-9]+}}, 191(1) +; CHECK: lhz {{[0-9]+}}, 189(1) +; CHECK: lwz {{[0-9]+}}, 185(1) ; CHECK: stb {{[0-9]+}}, 79(1) ; CHECK: sth {{[0-9]+}}, 77(1) ; CHECK: stw {{[0-9]+}}, 73(1) diff --git a/test/CodeGen/PowerPC/mcm-1.ll b/test/CodeGen/PowerPC/mcm-1.ll index a57fb9d..4e31550 100644 --- a/test/CodeGen/PowerPC/mcm-1.ll +++ b/test/CodeGen/PowerPC/mcm-1.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; CHECK: test_external: +; CHECK-LABEL: test_external: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-10.ll b/test/CodeGen/PowerPC/mcm-10.ll index 4bec3e1..b479559 100644 --- a/test/CodeGen/PowerPC/mcm-10.ll +++ b/test/CodeGen/PowerPC/mcm-10.ll @@ -16,7 +16,7 @@ entry: ret i32 %0 } -; CHECK: test_fn_static: +; CHECK-LABEL: test_fn_static: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-11.ll b/test/CodeGen/PowerPC/mcm-11.ll index f2bc4c9..c49e865 100644 --- a/test/CodeGen/PowerPC/mcm-11.ll +++ b/test/CodeGen/PowerPC/mcm-11.ll @@ -16,7 +16,7 @@ entry: ret i32 %0 } -; CHECK: test_file_static: +; CHECK-LABEL: test_file_static: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-12.ll b/test/CodeGen/PowerPC/mcm-12.ll index 911305d..b31b605 100644 --- a/test/CodeGen/PowerPC/mcm-12.ll +++ b/test/CodeGen/PowerPC/mcm-12.ll @@ -13,6 +13,6 @@ entry: ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]: ; CHECK: .quad 4562098671269285104 -; CHECK: test_double_const: +; CHECK-LABEL: test_double_const: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-2.ll b/test/CodeGen/PowerPC/mcm-2.ll index f0dff4c..d4f40f7 100644 --- a/test/CodeGen/PowerPC/mcm-2.ll +++ b/test/CodeGen/PowerPC/mcm-2.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; MEDIUM: test_fn_static: +; MEDIUM-LABEL: test_fn_static: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) @@ -26,7 +26,7 @@ entry: ; MEDIUM: .local [[VAR]] ; MEDIUM: .comm [[VAR]],4,4 -; LARGE: test_fn_static: +; LARGE-LABEL: test_fn_static: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-3.ll b/test/CodeGen/PowerPC/mcm-3.ll index b790550..ce151fb 100644 --- a/test/CodeGen/PowerPC/mcm-3.ll +++ b/test/CodeGen/PowerPC/mcm-3.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; MEDIUM: test_file_static: +; MEDIUM-LABEL: test_file_static: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) @@ -28,7 +28,7 @@ entry: ; MEDIUM: [[VAR]]: ; MEDIUM: .long 5 -; LARGE: test_file_static: +; LARGE-LABEL: test_file_static: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll index 47c60c9..7d7b132 100644 --- a/test/CodeGen/PowerPC/mcm-4.ll +++ b/test/CodeGen/PowerPC/mcm-4.ll @@ -1,5 +1,5 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s ; Test correct code generation for medium and large code model ; for loading a value from the constant pool (TOC-relative). @@ -14,14 +14,14 @@ entry: ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM: .quad 4562098671269285104 -; MEDIUM: test_double_const: +; MEDIUM-LABEL: test_double_const: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: .quad 4562098671269285104 -; LARGE: test_double_const: +; LARGE-LABEL: test_double_const: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll index 1be27b7..92ddeca 100644 --- a/test/CodeGen/PowerPC/mcm-5.ll +++ b/test/CodeGen/PowerPC/mcm-5.ll @@ -51,7 +51,7 @@ sw.epilog: ; preds = %sw.bb3, %sw.default ret i32 %5 } -; CHECK: test_jump_table: +; CHECK-LABEL: test_jump_table: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]] diff --git a/test/CodeGen/PowerPC/mcm-6.ll b/test/CodeGen/PowerPC/mcm-6.ll index 35efaaa..f7838b4 100644 --- a/test/CodeGen/PowerPC/mcm-6.ll +++ b/test/CodeGen/PowerPC/mcm-6.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; CHECK: test_tentative: +; CHECK-LABEL: test_tentative: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-7.ll b/test/CodeGen/PowerPC/mcm-7.ll index 0dd39ee..7caa13b 100644 --- a/test/CodeGen/PowerPC/mcm-7.ll +++ b/test/CodeGen/PowerPC/mcm-7.ll @@ -18,7 +18,7 @@ entry: declare signext i32 @foo(i32 signext) -; CHECK: test_fnaddr: +; CHECK-LABEL: test_fnaddr: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: .section .toc diff --git a/test/CodeGen/PowerPC/mcm-8.ll b/test/CodeGen/PowerPC/mcm-8.ll index 3ece786..643548f 100644 --- a/test/CodeGen/PowerPC/mcm-8.ll +++ b/test/CodeGen/PowerPC/mcm-8.ll @@ -16,7 +16,7 @@ entry: ret i8 %1 } -; CHECK: test_avext: +; CHECK-LABEL: test_avext: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lbz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-9.ll b/test/CodeGen/PowerPC/mcm-9.ll index f366f45..e587f61 100644 --- a/test/CodeGen/PowerPC/mcm-9.ll +++ b/test/CodeGen/PowerPC/mcm-9.ll @@ -18,7 +18,7 @@ entry: ret i32 %0 } -; CHECK: test_external: +; CHECK-LABEL: test_external: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-default.ll b/test/CodeGen/PowerPC/mcm-default.ll index 19de253..8d4ff14 100644 --- a/test/CodeGen/PowerPC/mcm-default.ll +++ b/test/CodeGen/PowerPC/mcm-default.ll @@ -16,7 +16,7 @@ entry: ret i32 %0 } -; CHECK: test_external: +; CHECK-LABEL: test_external: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll index 4550c39..d3d05eb 100644 --- a/test/CodeGen/PowerPC/mcm-obj.ll +++ b/test/CodeGen/PowerPC/mcm-obj.ll @@ -1,6 +1,6 @@ -; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \ +; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \ +; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s ; FIXME: When asm-parse is available, could make this an assembly test. diff --git a/test/CodeGen/PowerPC/misched-inorder-latency.ll b/test/CodeGen/PowerPC/misched-inorder-latency.ll index 8fae7ad..b259ff1 100644 --- a/test/CodeGen/PowerPC/misched-inorder-latency.ll +++ b/test/CodeGen/PowerPC/misched-inorder-latency.ll @@ -6,7 +6,7 @@ target triple = "powerpc64-bgq-linux" ; %val1 is a load live out of %entry. It should be hoisted ; above the add. -; CHECK: testload: +; CHECK-LABEL: testload: ; CHECK: %entry ; CHECK: lwz ; CHECK: addi @@ -34,7 +34,7 @@ end: ; The prefetch gets a default latency of 3 cycles and should be hoisted ; above the add. ; -; CHECK: testprefetch: +; CHECK-LABEL: testprefetch: ; CHECK: %entry ; CHECK: dcbt ; CHECK: addi diff --git a/test/CodeGen/PowerPC/mulli64.ll b/test/CodeGen/PowerPC/mulli64.ll new file mode 100644 index 0000000..21bc9cc --- /dev/null +++ b/test/CodeGen/PowerPC/mulli64.ll @@ -0,0 +1,16 @@ +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %a) #0 { +entry: + %mul = mul nsw i64 %a, 3 + ret i64 %mul +} + +; CHECK-LABEL: @foo +; CHECK: mulli 3, 3, 3 +; CHECK: blr + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/ppc32-vacopy.ll b/test/CodeGen/PowerPC/ppc32-vacopy.ll new file mode 100644 index 0000000..bc39412 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc32-vacopy.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple="powerpc-unknown-linux-gnu" < %s | FileCheck %s +; PR15286 + +%va_list = type {i8, i8, i16, i8*, i8*} +declare void @llvm.va_copy(i8*, i8*) + +define void @test_vacopy() nounwind { +entry: + %0 = alloca %va_list + %1 = alloca %va_list + %2 = bitcast %va_list* %0 to i8* + %3 = bitcast %va_list* %1 to i8* + + call void @llvm.va_copy(i8* %3, i8* %2) + + ret void +} +; CHECK: test_vacopy: +; CHECK: lwz [[REG1:[0-9]+]], {{.*}} +; CHECK: lwz [[REG2:[0-9]+]], {{.*}} +; CHECK: lwz [[REG3:[0-9]+]], {{.*}} +; CHECK: stw [[REG1]], {{.*}} +; CHECK: stw [[REG2]], {{.*}} +; CHECK: stw [[REG3]], {{.*}} diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll index 10b70d0..764d3ce 100644 --- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; Verify internal alignment of long double in a struct. The double ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll index c382edb..1f3bb71 100644 --- a/test/CodeGen/PowerPC/ppc64-calls.ll +++ b/test/CodeGen/PowerPC/ppc64-calls.ll @@ -12,7 +12,7 @@ define weak void @foo_weak() nounwind { ; Calls to local function does not require the TOC restore 'nop' define void @test_direct() nounwind readnone { -; CHECK: test_direct: +; CHECK-LABEL: test_direct: tail call void @foo() nounwind ; CHECK: bl foo ; CHECK-NOT: nop @@ -22,7 +22,7 @@ define void @test_direct() nounwind readnone { ; Calls to weak function requires a TOC restore 'nop' because they ; may be overridden in a different module. define void @test_weak() nounwind readnone { -; CHECK: test_weak: +; CHECK-LABEL: test_weak: tail call void @foo_weak() nounwind ; CHECK: bl foo ; CHECK-NEXT: nop @@ -31,7 +31,7 @@ define void @test_weak() nounwind readnone { ; Indirect calls requires a full stub creation define void @test_indirect(void ()* nocapture %fp) nounwind { -; CHECK: test_indirect: +; CHECK-LABEL: test_indirect: tail call void %fp() nounwind ; CHECK: ld [[FP:[0-9]+]], 0(3) ; CHECK: ld 11, 16(3) @@ -44,7 +44,7 @@ define void @test_indirect(void ()* nocapture %fp) nounwind { ; Absolute vales should be have the TOC restore 'nop' define void @test_abs() nounwind { -; CHECK: test_abs: +; CHECK-LABEL: test_abs: tail call void inttoptr (i64 1024 to void ()*)() nounwind ; CHECK: bla 1024 ; CHECK-NEXT: nop @@ -55,7 +55,7 @@ declare double @sin(double) nounwind ; External functions call should also have a 'nop' define double @test_external(double %x) nounwind { -; CHECK: test_external: +; CHECK-LABEL: test_external: %call = tail call double @sin(double %x) nounwind ; CHECK: bl sin ; CHECK-NEXT: nop diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll index 7f30ef8..f349919 100644 --- a/test/CodeGen/PowerPC/ppc64-toc.ll +++ b/test/CodeGen/PowerPC/ppc64-toc.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu" define i64 @access_int64(i64 %a) nounwind readonly { entry: -; CHECK: access_int64: +; CHECK-LABEL: access_int64: ; CHECK-NEXT: .align 3 ; CHECK-NEXT: .quad .L.access_int64 ; CHECK-NEXT: .quad .TOC.@tocbase @@ -23,7 +23,7 @@ entry: define i64 @internal_static_var(i64 %a) nounwind { entry: -; CHECK: internal_static_var: +; CHECK-LABEL: internal_static_var: ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) %0 = load i64* @internal_static_var.x, align 8 %cmp = icmp eq i64 %0, %a @@ -33,7 +33,7 @@ entry: define i32 @access_double(double %a) nounwind readnone { entry: -; CHECK: access_double: +; CHECK-LABEL: access_double: ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) %cmp = fcmp oeq double %a, 2.000000e+00 %conv = zext i1 %cmp to i32 @@ -43,7 +43,7 @@ entry: define i32 @access_double_array(double %a, i32 %i) nounwind readonly { entry: -; CHECK: access_double_array: +; CHECK-LABEL: access_double_array: %idxprom = sext i32 %i to i64 %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom %0 = load double* %arrayidx, align 8 diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll index 3ae7385..4be65dd 100644 --- a/test/CodeGen/PowerPC/pr13891.ll +++ b/test/CodeGen/PowerPC/pr13891.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.foo = type { i8, i8 } define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline { -; CHECK: _Z5check3foos: +; CHECK-LABEL: _Z5check3foos: ; CHECK: sth 3, {{[0-9]+}}(1) ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1) entry: diff --git a/test/CodeGen/PowerPC/pr16556-2.ll b/test/CodeGen/PowerPC/pr16556-2.ll new file mode 100644 index 0000000..e2dae45 --- /dev/null +++ b/test/CodeGen/PowerPC/pr16556-2.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s + +; This test formerly failed because of wrong custom lowering for +; fptosi of ppc_fp128. + +target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "powerpc-unknown-linux-gnu" + +%core.time.TickDuration = type { i64 } + +@_D4core4time12TickDuration11ticksPerSecyl = global i64 0 +@.str5 = internal unnamed_addr constant [40 x i8] c"..\5Cldc\5Cruntime\5Cdruntime\5Csrc\5Ccore\5Ctime.d\00" +@.str83 = internal constant [10 x i8] c"null this\00" +@.modulefilename = internal constant { i32, i8* } { i32 39, i8* getelementptr inbounds ([40 x i8]* @.str5, i32 0, i32 0) } + +declare i8* @_d_assert_msg({ i32, i8* }, { i32, i8* }, i32) + + +define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(%core.time.TickDuration* %.this_arg) { +entry: + %unitsPerSec = alloca i64, align 8 + %tmp = icmp ne %core.time.TickDuration* %.this_arg, null + br i1 %tmp, label %noassert, label %assert + +assert: ; preds = %entry + %tmp1 = load { i32, i8* }* @.modulefilename + %0 = call i8* @_d_assert_msg({ i32, i8* } { i32 9, i8* getelementptr inbounds ([10 x i8]* @.str83, i32 0, i32 0) }, { i32, i8* } %tmp1, i32 1586) + unreachable + +noassert: ; preds = %entry + %tmp2 = getelementptr %core.time.TickDuration* %.this_arg, i32 0, i32 0 + %tmp3 = load i64* %tmp2 + %tmp4 = sitofp i64 %tmp3 to ppc_fp128 + %tmp5 = load i64* @_D4core4time12TickDuration11ticksPerSecyl + %tmp6 = sitofp i64 %tmp5 to ppc_fp128 + %tmp7 = fdiv ppc_fp128 %tmp6, 0xM80000000000000000000000000000000 + %tmp8 = fdiv ppc_fp128 %tmp4, %tmp7 + %tmp9 = fptosi ppc_fp128 %tmp8 to i64 + ret i64 %tmp9 +} + diff --git a/test/CodeGen/PowerPC/pr16556.ll b/test/CodeGen/PowerPC/pr16556.ll new file mode 100644 index 0000000..dc36f0b --- /dev/null +++ b/test/CodeGen/PowerPC/pr16556.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s + +; This test formerly failed due to no handling for a ppc_fp128 undef. + +target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "powerpc-unknown-linux-gnu" + +%core.time.TickDuration.37.125 = type { i64 } + +define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(%core.time.TickDuration.37.125* %.this_arg) { +entry: + br i1 undef, label %noassert, label %assert + +assert: ; preds = %entry + unreachable + +noassert: ; preds = %entry + %tmp9 = fptosi ppc_fp128 undef to i64 + ret i64 %tmp9 +} diff --git a/test/CodeGen/PowerPC/pr16573.ll b/test/CodeGen/PowerPC/pr16573.ll new file mode 100644 index 0000000..7a7a8de --- /dev/null +++ b/test/CodeGen/PowerPC/pr16573.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s | FileCheck %s + +target triple = "powerpc64-unknown-linux-gnu" + +define double @test() { + %1 = fptrunc ppc_fp128 0xM818F2887B9295809800000000032D000 to double + ret double %1 +} + +; CHECK: .quad -9111018957755033591 + diff --git a/test/CodeGen/PowerPC/reloc-align.ll b/test/CodeGen/PowerPC/reloc-align.ll new file mode 100644 index 0000000..bd5c4d6 --- /dev/null +++ b/test/CodeGen/PowerPC/reloc-align.ll @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/remap-crash.ll b/test/CodeGen/PowerPC/remap-crash.ll new file mode 100644 index 0000000..515f720 --- /dev/null +++ b/test/CodeGen/PowerPC/remap-crash.ll @@ -0,0 +1,57 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD13() { +BB: + br label %CF78 + +CF78: ; preds = %CF87, %CF86, %CF78, %BB + %Cmp = icmp ule <16 x i64> zeroinitializer, zeroinitializer + br i1 undef, label %CF78, label %CF86 + +CF86: ; preds = %CF78 + br i1 undef, label %CF78, label %CF84 + +CF84: ; preds = %CF84, %CF86 + br i1 undef, label %CF84, label %CF87 + +CF87: ; preds = %CF84 + br i1 undef, label %CF78, label %CF82 + +CF82: ; preds = %CF82, %CF87 + br i1 undef, label %CF82, label %CF83 + +CF83: ; preds = %CF82 + br label %CF + +CF: ; preds = %CF80, %CF81, %CF, %CF83 + br i1 undef, label %CF, label %CF81 + +CF81: ; preds = %CF + %Se = sext <16 x i1> %Cmp to <16 x i16> + br i1 undef, label %CF, label %CF80 + +CF80: ; preds = %CF81 + br i1 undef, label %CF, label %CF76 + +CF76: ; preds = %CF76, %CF80 + %Sl58 = select i1 undef, <16 x i16> %Se, <16 x i16> %Se + br label %CF76 +} + +define void @autogen_SD1067() { +BB: + %FC = sitofp <4 x i32> zeroinitializer to <4 x ppc_fp128> + br label %CF77 + +CF77: ; preds = %CF77, %BB + %brmerge = or i1 false, undef + br i1 %brmerge, label %CF77, label %CF85 + +CF85: ; preds = %CF77 + %Shuff19 = shufflevector <4 x ppc_fp128> %FC, <4 x ppc_fp128> %FC, <4 x i32> <i32 7, i32 1, i32 3, i32 5> + br label %CF75 + +CF75: ; preds = %CF75, %CF85 + br label %CF75 +} diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll new file mode 100644 index 0000000..e20a13f --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi-and.ll @@ -0,0 +1,44 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +define void @test() align 2 { +entry: + br i1 undef, label %codeRepl1, label %codeRepl31 + +codeRepl1: ; preds = %entry + br i1 undef, label %codeRepl4, label %codeRepl29 + +codeRepl4: ; preds = %codeRepl1 + br i1 undef, label %codeRepl12, label %codeRepl17 + +codeRepl12: ; preds = %codeRepl4 + unreachable + +codeRepl17: ; preds = %codeRepl4 + %0 = load i8* undef, align 2 + %1 = and i8 %0, 1 + %not.tobool.i.i.i = icmp eq i8 %1, 0 + %2 = select i1 %not.tobool.i.i.i, i16 0, i16 256 + %3 = load i8* undef, align 1 + %4 = and i8 %3, 1 + %not.tobool.i.1.i.i = icmp eq i8 %4, 0 + %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1 + %rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2 + store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2 + unreachable + +; CHECK: @test +; CHECK-DAG: slwi [[R1:[0-9]+]], +; CHECK-DAG: rlwinm [[R2:[0-9]+]], +; CHECK-DAG: srawi [[R3:[0-9]+]], [[R1]] +; CHECK-DAG: rlwinm [[R4:[0-9]+]], [[R3]], 0, 23, 23 +; CHECK: rlwimi [[R4]], [[R2]], 0, + +codeRepl29: ; preds = %codeRepl1 + unreachable + +codeRepl31: ; preds = %entry + ret void +} + diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll index 2b5e1c9..2c02900 100644 --- a/test/CodeGen/PowerPC/rounding-ops.ll +++ b/test/CodeGen/PowerPC/rounding-ops.ll @@ -7,10 +7,10 @@ define float @test1(float %x) nounwind { %call = tail call float @floorf(float %x) nounwind readnone ret float %call -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: frim 1, 1 -; CHECK-FM: test1: +; CHECK-FM-LABEL: test1: ; CHECK-FM: frim 1, 1 } @@ -20,10 +20,10 @@ define double @test2(double %x) nounwind { %call = tail call double @floor(double %x) nounwind readnone ret double %call -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: frim 1, 1 -; CHECK-FM: test2: +; CHECK-FM-LABEL: test2: ; CHECK-FM: frim 1, 1 } @@ -33,10 +33,10 @@ define float @test3(float %x) nounwind { %call = tail call float @nearbyintf(float %x) nounwind readnone ret float %call -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK-NOT: frin -; CHECK-FM: test3: +; CHECK-FM-LABEL: test3: ; CHECK-FM: frin 1, 1 } @@ -46,10 +46,10 @@ define double @test4(double %x) nounwind { %call = tail call double @nearbyint(double %x) nounwind readnone ret double %call -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK-NOT: frin -; CHECK-FM: test4: +; CHECK-FM-LABEL: test4: ; CHECK-FM: frin 1, 1 } @@ -59,10 +59,10 @@ define float @test5(float %x) nounwind { %call = tail call float @ceilf(float %x) nounwind readnone ret float %call -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: frip 1, 1 -; CHECK-FM: test5: +; CHECK-FM-LABEL: test5: ; CHECK-FM: frip 1, 1 } @@ -72,10 +72,10 @@ define double @test6(double %x) nounwind { %call = tail call double @ceil(double %x) nounwind readnone ret double %call -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: frip 1, 1 -; CHECK-FM: test6: +; CHECK-FM-LABEL: test6: ; CHECK-FM: frip 1, 1 } @@ -85,10 +85,10 @@ define float @test9(float %x) nounwind { %call = tail call float @truncf(float %x) nounwind readnone ret float %call -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: friz 1, 1 -; CHECK-FM: test9: +; CHECK-FM-LABEL: test9: ; CHECK-FM: friz 1, 1 } @@ -98,10 +98,10 @@ define double @test10(double %x) nounwind { %call = tail call double @trunc(double %x) nounwind readnone ret double %call -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: friz 1, 1 -; CHECK-FM: test10: +; CHECK-FM-LABEL: test10: ; CHECK-FM: friz 1, 1 } @@ -112,10 +112,10 @@ define void @test11(float %x, float* %y) nounwind { store float %call, float* %y ret void -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK-NOT: frin -; CHECK-FM: test11: +; CHECK-FM-LABEL: test11: ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]] ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]] ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2 @@ -131,10 +131,10 @@ define void @test12(double %x, double* %y) nounwind { store double %call, double* %y ret void -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK-NOT: frin -; CHECK-FM: test12: +; CHECK-FM-LABEL: test12: ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]] ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]] ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2 diff --git a/test/CodeGen/PowerPC/rs-undef-use.ll b/test/CodeGen/PowerPC/rs-undef-use.ll new file mode 100644 index 0000000..24dd5fd --- /dev/null +++ b/test/CodeGen/PowerPC/rs-undef-use.ll @@ -0,0 +1,48 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD156869(i8*, i64*) { +BB: + %A3 = alloca <2 x i1> + %A2 = alloca <8 x i32> + br label %CF + +CF: ; preds = %CF85, %CF, %BB + br i1 undef, label %CF, label %CF82.critedge + +CF82.critedge: ; preds = %CF + store i8 -59, i8* %0 + br label %CF82 + +CF82: ; preds = %CF82, %CF82.critedge + %L17 = load i8* %0 + %E18 = extractelement <2 x i64> undef, i32 0 + %PC = bitcast <2 x i1>* %A3 to i64* + br i1 undef, label %CF82, label %CF84.critedge + +CF84.critedge: ; preds = %CF82 + store i64 455385, i64* %PC + br label %CF84 + +CF84: ; preds = %CF84, %CF84.critedge + %L40 = load i64* %PC + store i64 -1, i64* %PC + %Sl46 = select i1 undef, i1 undef, i1 false + br i1 %Sl46, label %CF84, label %CF85 + +CF85: ; preds = %CF84 + %L47 = load i64* %PC + store i64 %E18, i64* %PC + %PC52 = bitcast <8 x i32>* %A2 to ppc_fp128* + store ppc_fp128 0xM4D436562A0416DE00000000000000000, ppc_fp128* %PC52 + %PC59 = bitcast i64* %1 to i8* + %Cmp61 = icmp slt i64 %L47, %L40 + br i1 %Cmp61, label %CF, label %CF77 + +CF77: ; preds = %CF77, %CF85 + br i1 undef, label %CF77, label %CF81 + +CF81: ; preds = %CF77 + store i8 %L17, i8* %PC59 + ret void +} diff --git a/test/CodeGen/PowerPC/set0-v8i16.ll b/test/CodeGen/PowerPC/set0-v8i16.ll new file mode 100644 index 0000000..13d51df --- /dev/null +++ b/test/CodeGen/PowerPC/set0-v8i16.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD367951() { +BB: + %Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24> + %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18> + %Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer + %E27 = extractelement <16 x i1> %Cmp11, i32 5 + br label %CF76 + +CF76: ; preds = %CF80, %CF76, %BB + br i1 undef, label %CF76, label %CF80 + +CF80: ; preds = %CF76 + %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff + br label %CF76 +} diff --git a/test/CodeGen/PowerPC/sj-ctr-loop.ll b/test/CodeGen/PowerPC/sj-ctr-loop.ll new file mode 100644 index 0000000..1866bcd --- /dev/null +++ b/test/CodeGen/PowerPC/sj-ctr-loop.ll @@ -0,0 +1,50 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.__jmp_buf_tag.1.15.17.21.25.49.53.55 = type { [64 x i64], i32, %struct.__sigset_t.0.14.16.20.24.48.52.54, [8 x i8] } +%struct.__sigset_t.0.14.16.20.24.48.52.54 = type { [16 x i64] } + +@env_sigill = external global [1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55], align 16 + +; CHECK-LABEL: @main +; CHECK-NOT: mtctr + +; Function Attrs: nounwind +define void @main() #0 { +entry: + br i1 undef, label %return, label %if.end + +if.end: ; preds = %entry + br i1 undef, label %for.body.lr.ph, label %for.end.thread + +for.end.thread: ; preds = %if.end + br label %return + +for.body.lr.ph: ; preds = %if.end + br label %for.body + +for.cond: ; preds = %for.body + %cmp2 = icmp slt i32 %inc, undef + br i1 %cmp2, label %for.body, label %for.end + +for.body: ; preds = %for.cond, %for.body.lr.ph + %i.032 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.cond ] + %0 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55]* @env_sigill to i8*)) + %inc = add nsw i32 %i.032, 1 + br i1 false, label %if.else, label %for.cond + +if.else: ; preds = %for.body + unreachable + +for.end: ; preds = %for.cond + unreachable + +return: ; preds = %for.end.thread, %entry + ret void +} + +; Function Attrs: nounwind +declare i32 @llvm.eh.sjlj.setjmp(i8*) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index 7ea35da..571f3b2 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -20,6 +20,7 @@ entry: ; CHECK: ld [[REG2:[0-9]+]], 8([[REG]]) ; CHECK: ld 1, 16([[REG]]) ; CHECK: mtctr [[REG2]] +; CHECK: ld 30, 32([[REG]]) ; CHECK: ld 2, 24([[REG]]) ; CHECK: bctr @@ -99,6 +100,52 @@ return: ; preds = %if.end, %if.then ; CHECK-NOAV: blr } +define signext i32 @main2() #0 { +entry: + %a = alloca i8, align 64 + call void @bar(i8* %a) + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %0 = call i8* @llvm.frameaddress(i32 0) + store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**) + %1 = call i8* @llvm.stacksave() + store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2) + %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*)) + %tobool = icmp ne i32 %2, 0 + br i1 %tobool, label %if.then, label %if.else + +if.then: ; preds = %entry + store i32 1, i32* %retval + br label %return + +if.else: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.else + store i32 0, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %3 = load i32* %retval + ret i32 %3 + +; CHECK: @main2 + +; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK: std 31, env_sigill@toc@l([[REG]]) +; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l +; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK: std 1, 16([[REG]]) +; CHECK: std 2, 24([[REG]]) +; CHECK: std 30, 32([[REG]]) +; CHECK: bcl 20, 31, + +; CHECK: blr +} + +declare void @bar(i8*) #3 + declare i8* @llvm.frameaddress(i32) #2 declare i8* @llvm.stacksave() #3 diff --git a/test/CodeGen/PowerPC/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll index 810630f..b81d941 100644 --- a/test/CodeGen/PowerPC/stack-protector.ll +++ b/test/CodeGen/PowerPC/stack-protector.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=ppc32 < %s -o - | grep "__stack_chk_guard" -; RUN: llc -march=ppc32 < %s -o - | grep "__stack_chk_fail" +; RUN: llc -march=ppc32 -mtriple=ppc32-unknown-linux < %s | FileCheck %s +; CHECK: __stack_chk_guard +; CHECK: __stack_chk_fail @"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll new file mode 100644 index 0000000..f7b6d19 --- /dev/null +++ b/test/CodeGen/PowerPC/stack-realign.ll @@ -0,0 +1,151 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.s = type { i32, i32 } + +declare void @bar(i32*) + +define void @goo(%struct.s* byval nocapture readonly %a) { +entry: + %x = alloca [2 x i32], align 32 + %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %0 = load i32* %a1, align 4, !tbaa !0 + %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0 + store i32 %0, i32* %arrayidx, align 32, !tbaa !0 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %1 = load i32* %b, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1 + store i32 %1, i32* %arrayidx2, align 4, !tbaa !0 + call void @bar(i32* %arrayidx) + ret void +} + +; CHECK-LABEL: @goo + +; CHECK-DAG: mflr 0 +; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-DAG: std 30, -16(1) +; CHECK-DAG: mr 30, 1 +; CHECK-DAG: std 0, 16(1) +; CHECK-DAG: subfic 0, [[REG]], -160 +; CHECK: stdux 1, 1, 0 + +; CHECK: .cfi_offset r30, -16 +; CHECK: .cfi_offset lr, 16 + +; CHECK: std 3, 48(30) + +; CHECK: ld 1, 0(1) +; CHECK-DAG: ld 0, 16(1) +; CHECK-DAG: ld 30, -16(1) +; CHECK-DAG: mtlr 0 +; CHECK: blr + +; CHECK-FP-LABEL: @goo + +; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-FP-DAG: std 31, -8(1) +; CHECK-FP-DAG: std 30, -16(1) +; CHECK-FP-DAG: mr 30, 1 +; CHECK-FP-DAG: std 0, 16(1) +; CHECK-FP-DAG: subfic 0, [[REG]], -160 +; CHECK-FP: stdux 1, 1, 0 + +; CHECK-FP: .cfi_offset r31, -8 +; CHECK-FP: .cfi_offset r30, -16 +; CHECK-FP: .cfi_offset lr, 16 + +; CHECK-FP: mr 31, 1 + +; CHECK-FP: std 3, 48(30) + +; CHECK-FP: ld 1, 0(1) +; CHECK-FP-DAG: ld 0, 16(1) +; CHECK-FP-DAG: ld 31, -8(1) +; CHECK-FP-DAG: ld 30, -16(1) +; CHECK-FP-DAG: mtlr 0 +; CHECK-FP: blr + +; The large-frame-size case. +define void @hoo(%struct.s* byval nocapture readonly %a) { +entry: + %x = alloca [200000 x i32], align 32 + %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %0 = load i32* %a1, align 4, !tbaa !0 + %arrayidx = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 0 + store i32 %0, i32* %arrayidx, align 32, !tbaa !0 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %1 = load i32* %b, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 1 + store i32 %1, i32* %arrayidx2, align 4, !tbaa !0 + call void @bar(i32* %arrayidx) + ret void +} + +; CHECK-LABEL: @hoo + +; CHECK-DAG: lis [[REG1:[0-9]+]], -13 +; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59 +; CHECK-DAG: mflr 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808 +; CHECK-DAG: std 30, -16(1) +; CHECK-DAG: mr 30, 1 +; CHECK-DAG: std 0, 16(1) +; CHECK-DAG: subfc 0, [[REG3]], [[REG2]] +; CHECK: stdux 1, 1, 0 + +; CHECK: blr + +; Make sure that the FP save area is still allocated correctly relative to +; where r30 is saved. +define void @loo(%struct.s* byval nocapture readonly %a) { +entry: + %x = alloca [2 x i32], align 32 + %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %0 = load i32* %a1, align 4, !tbaa !0 + %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0 + store i32 %0, i32* %arrayidx, align 32, !tbaa !0 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %1 = load i32* %b, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1 + store i32 %1, i32* %arrayidx2, align 4, !tbaa !0 + call void @bar(i32* %arrayidx) + call void asm sideeffect "", "~{f30}"() nounwind + ret void +} + +; CHECK-LABEL: @loo + +; CHECK-DAG: mflr 0 +; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-DAG: std 30, -32(1) +; CHECK-DAG: mr 30, 1 +; CHECK-DAG: std 0, 16(1) +; CHECK-DAG: subfic 0, [[REG]], -192 +; CHECK: stdux 1, 1, 0 + +; CHECK: stfd 30, -16(30) + +; CHECK: blr + +; CHECK-FP-LABEL: @loo + +; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-FP-DAG: std 31, -24(1) +; CHECK-FP-DAG: std 30, -32(1) +; CHECK-FP-DAG: mr 30, 1 +; CHECK-FP-DAG: std 0, 16(1) +; CHECK-FP-DAG: subfic 0, [[REG]], -192 +; CHECK-FP: stdux 1, 1, 0 + +; CHECK-FP: stfd 30, -16(30) + +; CHECK-FP: blr + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/std-unal-fi.ll b/test/CodeGen/PowerPC/std-unal-fi.ll new file mode 100644 index 0000000..8b9606e --- /dev/null +++ b/test/CodeGen/PowerPC/std-unal-fi.ll @@ -0,0 +1,119 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD4932(i8) { +BB: + %A4 = alloca i8 + %A = alloca <1 x ppc_fp128> + %Shuff = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 undef, i32 29, i32 31, i32 1, i32 3, i32 5> + br label %CF + +CF: ; preds = %CF80, %CF, %BB + %L5 = load i64* undef + store i8 %0, i8* %A4 + %Shuff7 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26> + %PC10 = bitcast i8* %A4 to ppc_fp128* + br i1 undef, label %CF, label %CF77 + +CF77: ; preds = %CF81, %CF83, %CF77, %CF + br i1 undef, label %CF77, label %CF82 + +CF82: ; preds = %CF82, %CF77 + %L19 = load i64* undef + store <1 x ppc_fp128> zeroinitializer, <1 x ppc_fp128>* %A + store i8 -65, i8* %A4 + br i1 undef, label %CF82, label %CF83 + +CF83: ; preds = %CF82 + %L34 = load i64* undef + br i1 undef, label %CF77, label %CF81 + +CF81: ; preds = %CF83 + %Shuff43 = shufflevector <16 x i32> %Shuff7, <16 x i32> undef, <16 x i32> <i32 15, i32 17, i32 19, i32 21, i32 23, i32 undef, i32 undef, i32 29, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13> + store ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128* %PC10 + br i1 undef, label %CF77, label %CF78 + +CF78: ; preds = %CF78, %CF81 + br i1 undef, label %CF78, label %CF79 + +CF79: ; preds = %CF79, %CF78 + br i1 undef, label %CF79, label %CF80 + +CF80: ; preds = %CF79 + store i64 %L19, i64* undef + %Cmp75 = icmp uge i32 206779, undef + br i1 %Cmp75, label %CF, label %CF76 + +CF76: ; preds = %CF80 + store i64 %L5, i64* undef + store i64 %L34, i64* undef + ret void +} + +define void @autogen_SD88042(i8*, i32*, i8) { +BB: + %A4 = alloca <2 x i1> + %A = alloca <16 x float> + %L = load i8* %0 + %Sl = select i1 false, <16 x float>* %A, <16 x float>* %A + %PC = bitcast <2 x i1>* %A4 to i64* + %Sl27 = select i1 false, i8 undef, i8 %L + br label %CF + +CF: ; preds = %CF78, %CF, %BB + %PC33 = bitcast i32* %1 to i32* + br i1 undef, label %CF, label %CF77 + +CF77: ; preds = %CF80, %CF77, %CF + store <16 x float> zeroinitializer, <16 x float>* %Sl + %L58 = load i32* %PC33 + store i8 0, i8* %0 + br i1 undef, label %CF77, label %CF80 + +CF80: ; preds = %CF77 + store i64 0, i64* %PC + %E67 = extractelement <8 x i1> zeroinitializer, i32 1 + br i1 %E67, label %CF77, label %CF78 + +CF78: ; preds = %CF80 + %Cmp73 = icmp eq i32 189865, %L58 + br i1 %Cmp73, label %CF, label %CF76 + +CF76: ; preds = %CF78 + store i8 %2, i8* %0 + store i8 %Sl27, i8* %0 + ret void +} + +define void @autogen_SD37497(i8*, i32*, i64*) { +BB: + %A1 = alloca i1 + %I8 = insertelement <1 x i32> <i32 -1>, i32 454855, i32 0 + %Cmp = icmp ult <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, undef + %L10 = load i64* %2 + %E11 = extractelement <4 x i1> %Cmp, i32 2 + br label %CF72 + +CF72: ; preds = %CF74, %CF72, %BB + store double 0xB47BB29A53790718, double* undef + %E18 = extractelement <1 x i32> <i32 -1>, i32 0 + %FC22 = sitofp <1 x i32> %I8 to <1 x float> + br i1 undef, label %CF72, label %CF74 + +CF74: ; preds = %CF72 + store i8 0, i8* %0 + %PC = bitcast i1* %A1 to i64* + %L31 = load i64* %PC + store i64 477323, i64* %PC + %Sl37 = select i1 false, i32* undef, i32* %1 + %Cmp38 = icmp ugt i1 undef, undef + br i1 %Cmp38, label %CF72, label %CF73 + +CF73: ; preds = %CF74 + store i64 %L31, i64* %PC + %B55 = fdiv <1 x float> undef, %FC22 + %Sl63 = select i1 %E11, i32* undef, i32* %Sl37 + store i32 %E18, i32* %Sl63 + store i64 %L10, i64* %PC + ret void +} diff --git a/test/CodeGen/PowerPC/store-update.ll b/test/CodeGen/PowerPC/store-update.ll index 538ed24..7b9e8f7 100644 --- a/test/CodeGen/PowerPC/store-update.ll +++ b/test/CodeGen/PowerPC/store-update.ll @@ -3,166 +3,166 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -define i8* @stbu(i8* %base, i8 zeroext %val) nounwind { +define i8* @test_stbu(i8* %base, i8 zeroext %val) nounwind { entry: %arrayidx = getelementptr inbounds i8* %base, i64 16 store i8 %val, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbu +; CHECK: @test_stbu ; CHECK: %entry ; CHECK-NEXT: stbu ; CHECK-NEXT: blr -define i8* @stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind { +define i8* @test_stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i8* %base, i64 %offset store i8 %val, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbux +; CHECK: @test_stbux ; CHECK: %entry ; CHECK-NEXT: stbux ; CHECK-NEXT: blr -define i16* @sthu(i16* %base, i16 zeroext %val) nounwind { +define i16* @test_sthu(i16* %base, i16 zeroext %val) nounwind { entry: %arrayidx = getelementptr inbounds i16* %base, i64 16 store i16 %val, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthu +; CHECK: @test_sthu ; CHECK: %entry ; CHECK-NEXT: sthu ; CHECK-NEXT: blr -define i16* @sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind { +define i16* @test_sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i16* %base, i64 %offset store i16 %val, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthux +; CHECK: @test_sthux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: sthux ; CHECK-NEXT: blr -define i32* @stwu(i32* %base, i32 zeroext %val) nounwind { +define i32* @test_stwu(i32* %base, i32 zeroext %val) nounwind { entry: %arrayidx = getelementptr inbounds i32* %base, i64 16 store i32 %val, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwu +; CHECK: @test_stwu ; CHECK: %entry ; CHECK-NEXT: stwu ; CHECK-NEXT: blr -define i32* @stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind { +define i32* @test_stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i32* %base, i64 %offset store i32 %val, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwux +; CHECK: @test_stwux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: stwux ; CHECK-NEXT: blr -define i8* @stbu8(i8* %base, i64 %val) nounwind { +define i8* @test_stbu8(i8* %base, i64 %val) nounwind { entry: %conv = trunc i64 %val to i8 %arrayidx = getelementptr inbounds i8* %base, i64 16 store i8 %conv, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbu +; CHECK: @test_stbu8 ; CHECK: %entry ; CHECK-NEXT: stbu ; CHECK-NEXT: blr -define i8* @stbux8(i8* %base, i64 %val, i64 %offset) nounwind { +define i8* @test_stbux8(i8* %base, i64 %val, i64 %offset) nounwind { entry: %conv = trunc i64 %val to i8 %arrayidx = getelementptr inbounds i8* %base, i64 %offset store i8 %conv, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbux +; CHECK: @test_stbux8 ; CHECK: %entry ; CHECK-NEXT: stbux ; CHECK-NEXT: blr -define i16* @sthu8(i16* %base, i64 %val) nounwind { +define i16* @test_sthu8(i16* %base, i64 %val) nounwind { entry: %conv = trunc i64 %val to i16 %arrayidx = getelementptr inbounds i16* %base, i64 16 store i16 %conv, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthu +; CHECK: @test_sthu ; CHECK: %entry ; CHECK-NEXT: sthu ; CHECK-NEXT: blr -define i16* @sthux8(i16* %base, i64 %val, i64 %offset) nounwind { +define i16* @test_sthux8(i16* %base, i64 %val, i64 %offset) nounwind { entry: %conv = trunc i64 %val to i16 %arrayidx = getelementptr inbounds i16* %base, i64 %offset store i16 %conv, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthux +; CHECK: @test_sthux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: sthux ; CHECK-NEXT: blr -define i32* @stwu8(i32* %base, i64 %val) nounwind { +define i32* @test_stwu8(i32* %base, i64 %val) nounwind { entry: %conv = trunc i64 %val to i32 %arrayidx = getelementptr inbounds i32* %base, i64 16 store i32 %conv, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwu +; CHECK: @test_stwu ; CHECK: %entry ; CHECK-NEXT: stwu ; CHECK-NEXT: blr -define i32* @stwux8(i32* %base, i64 %val, i64 %offset) nounwind { +define i32* @test_stwux8(i32* %base, i64 %val, i64 %offset) nounwind { entry: %conv = trunc i64 %val to i32 %arrayidx = getelementptr inbounds i32* %base, i64 %offset store i32 %conv, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwux +; CHECK: @test_stwux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: stwux ; CHECK-NEXT: blr -define i64* @stdu(i64* %base, i64 %val) nounwind { +define i64* @test_stdu(i64* %base, i64 %val) nounwind { entry: %arrayidx = getelementptr inbounds i64* %base, i64 16 store i64 %val, i64* %arrayidx, align 8 ret i64* %arrayidx } -; CHECK: @stdu +; CHECK: @test_stdu ; CHECK: %entry ; CHECK-NEXT: stdu ; CHECK-NEXT: blr -define i64* @stdux(i64* %base, i64 %val, i64 %offset) nounwind { +define i64* @test_stdux(i64* %base, i64 %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i64* %base, i64 %offset store i64 %val, i64* %arrayidx, align 8 ret i64* %arrayidx } -; CHECK: @stdux +; CHECK: @test_stdux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: stdux diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll index 2a17e74..5b8dead 100644 --- a/test/CodeGen/PowerPC/structsinmem.ll +++ b/test/CodeGen/PowerPC/structsinmem.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll index 54de606..fb3bd7c 100644 --- a/test/CodeGen/PowerPC/structsinregs.ll +++ b/test/CodeGen/PowerPC/structsinregs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/sub-bv-types.ll b/test/CodeGen/PowerPC/sub-bv-types.ll new file mode 100644 index 0000000..c72fae6 --- /dev/null +++ b/test/CodeGen/PowerPC/sub-bv-types.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD10521() { +BB: + %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 undef, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 undef, i32 22, i32 undef, i32 26, i32 undef, i32 30> + br label %CF + +CF: ; preds = %CF78, %CF, %BB + %I27 = insertelement <16 x i16> %Shuff7, i16 1360, i32 8 + %B28 = sub <16 x i16> %I27, %Shuff7 + br i1 undef, label %CF, label %CF78 + +CF78: ; preds = %CF + %B42 = xor <16 x i16> %B28, %Shuff7 + br label %CF +} diff --git a/test/CodeGen/PowerPC/svr4-redzone.ll b/test/CodeGen/PowerPC/svr4-redzone.ll index 91ff579..7c51b67 100644 --- a/test/CodeGen/PowerPC/svr4-redzone.ll +++ b/test/CodeGen/PowerPC/svr4-redzone.ll @@ -7,11 +7,11 @@ entry: %0 = add i32 1, 2 ret void } -; PPC32: regalloc: +; PPC32-LABEL: regalloc: ; PPC32-NOT: stwu 1, -{{[0-9]+}}(1) ; PPC32: blr -; PPC64: regalloc: +; PPC64-LABEL: regalloc: ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1) ; PPC64: blr @@ -20,10 +20,10 @@ entry: %0 = alloca i8, i32 4 ret void } -; PPC32: smallstack: +; PPC32-LABEL: smallstack: ; PPC32: stwu 1, -16(1) -; PPC64: smallstack: +; PPC64-LABEL: smallstack: ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1) ; PPC64: blr @@ -32,8 +32,8 @@ entry: %0 = alloca i8, i32 230 ret void } -; PPC32: bigstack: +; PPC32-LABEL: bigstack: ; PPC32: stwu 1, -240(1) -; PPC64: bigstack: +; PPC64-LABEL: bigstack: ; PPC64: stdu 1, -352(1) diff --git a/test/CodeGen/PowerPC/tls-2.ll b/test/CodeGen/PowerPC/tls-2.ll index 20d8fe4..c2faf90 100644 --- a/test/CodeGen/PowerPC/tls-2.ll +++ b/test/CodeGen/PowerPC/tls-2.ll @@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-freebsd10.0" @a = thread_local global i32 0, align 4 -;CHECK: localexec: +;CHECK-LABEL: localexec: define i32 @localexec() nounwind { entry: ;CHECK: addis [[REG1:[0-9]+]], 13, a@tprel@ha diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 2daa60a..4e0a822 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -5,8 +5,8 @@ target triple = "powerpc64-unknown-freebsd10.0" @a = thread_local global i32 0, align 4 -;OPT0: localexec: -;OPT1: localexec: +;OPT0-LABEL: localexec: +;OPT1-LABEL: localexec: define i32 @localexec() nounwind { entry: ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll new file mode 100644 index 0000000..2baac76 --- /dev/null +++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo() #0 { +entry: + call void @llvm.eh.unwind.init(), !dbg !9 + ret void, !dbg !10 +} + +; CHECK: @foo +; CHECK-NOT: .cfi_offset vrsave +; CHECK: blr + +; Function Attrs: nounwind +declare void @llvm.eh.unwind.init() #0 + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!8} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99] +!1 = metadata !{metadata !"/tmp/unwind-dw2.c", metadata !"/tmp"} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c] +!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{null} +!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 3} +!9 = metadata !{i32 2, i32 0, metadata !4, null} +!10 = metadata !{i32 3, i32 0, metadata !4, null} diff --git a/test/CodeGen/PowerPC/unwind-dw2.ll b/test/CodeGen/PowerPC/unwind-dw2.ll new file mode 100644 index 0000000..e58edff --- /dev/null +++ b/test/CodeGen/PowerPC/unwind-dw2.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo() #0 { +entry: + call void @llvm.eh.unwind.init() + ret void +} + +; Function Attrs: nounwind +declare void @llvm.eh.unwind.init() #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/vaddsplat.ll b/test/CodeGen/PowerPC/vaddsplat.ll index e65148a..4236fab 100644 --- a/test/CodeGen/PowerPC/vaddsplat.ll +++ b/test/CodeGen/PowerPC/vaddsplat.ll @@ -16,7 +16,7 @@ define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_pos_even: +; CHECK-LABEL: test_v4i32_pos_even: ; CHECK: vspltisw [[REG1:[0-9]+]], 9 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -27,7 +27,7 @@ define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_neg_even: +; CHECK-LABEL: test_v4i32_neg_even: ; CHECK: vspltisw [[REG1:[0-9]+]], -14 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -38,7 +38,7 @@ define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_pos_even: +; CHECK-LABEL: test_v8i16_pos_even: ; CHECK: vspltish [[REG1:[0-9]+]], 15 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -49,7 +49,7 @@ define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_neg_even: +; CHECK-LABEL: test_v8i16_neg_even: ; CHECK: vspltish [[REG1:[0-9]+]], -16 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -60,7 +60,7 @@ define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_pos_even: +; CHECK-LABEL: test_v16i8_pos_even: ; CHECK: vspltisb [[REG1:[0-9]+]], 8 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -71,7 +71,7 @@ define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_neg_even: +; CHECK-LABEL: test_v16i8_neg_even: ; CHECK: vspltisb [[REG1:[0-9]+]], -9 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -82,7 +82,7 @@ define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_pos_odd: +; CHECK-LABEL: test_v4i32_pos_odd: ; CHECK: vspltisw [[REG2:[0-9]+]], -16 ; CHECK: vspltisw [[REG1:[0-9]+]], 11 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -94,7 +94,7 @@ define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_neg_odd: +; CHECK-LABEL: test_v4i32_neg_odd: ; CHECK: vspltisw [[REG2:[0-9]+]], -16 ; CHECK: vspltisw [[REG1:[0-9]+]], -11 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -106,7 +106,7 @@ define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_pos_odd: +; CHECK-LABEL: test_v8i16_pos_odd: ; CHECK: vspltish [[REG2:[0-9]+]], -16 ; CHECK: vspltish [[REG1:[0-9]+]], 15 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -118,7 +118,7 @@ define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_neg_odd: +; CHECK-LABEL: test_v8i16_neg_odd: ; CHECK: vspltish [[REG2:[0-9]+]], -16 ; CHECK: vspltish [[REG1:[0-9]+]], -15 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -130,7 +130,7 @@ define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_pos_odd: +; CHECK-LABEL: test_v16i8_pos_odd: ; CHECK: vspltisb [[REG2:[0-9]+]], -16 ; CHECK: vspltisb [[REG1:[0-9]+]], 1 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -142,7 +142,7 @@ define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_neg_odd: +; CHECK-LABEL: test_v16i8_neg_odd: ; CHECK: vspltisb [[REG2:[0-9]+]], -16 ; CHECK: vspltisb [[REG1:[0-9]+]], -1 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]] diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll index 90f0480..dfd2056 100644 --- a/test/CodeGen/PowerPC/varargs.ll +++ b/test/CodeGen/PowerPC/varargs.ll @@ -7,14 +7,14 @@ define i8* @test1(i8** %foo) nounwind { ret i8* %A } -; P32: test1: +; P32-LABEL: test1: ; P32: lwz r2, 0(r3) ; P32: addi r4, r2, 4 ; P32: stw r4, 0(r3) ; P32: lwz r3, 0(r2) ; P32: blr -; P64: test1: +; P64-LABEL: test1: ; P64: ld r2, 0(r3) ; P64: addi r4, r2, 8 ; P64: std r4, 0(r3) diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll index eb41667..83e0e02 100644 --- a/test/CodeGen/PowerPC/vec_cmp.ll +++ b/test/CodeGen/PowerPC/vec_cmp.ll @@ -14,7 +14,7 @@ define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone { %sext = sext <2 x i1> %cmp to <2 x i8> ret <2 x i8> %sext } -; CHECK: v2si8_cmp: +; CHECK-LABEL: v2si8_cmp: ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -23,7 +23,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone { %sext = sext <4 x i1> %cmp to <4 x i8> ret <4 x i8> %sext } -; CHECK: v4si8_cmp: +; CHECK-LABEL: v4si8_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -32,7 +32,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone { %sext = sext <8 x i1> %cmp to <8 x i8> ret <8 x i8> %sext } -; CHECK: v8si8_cmp: +; CHECK-LABEL: v8si8_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -43,7 +43,7 @@ define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone { %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_eq: +; CHECK-LABEL: v16si8_cmp_eq: ; CHECK: vcmpequb 2, 2, 3 define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -52,7 +52,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_ne: +; CHECK-LABEL: v16si8_cmp_ne: ; CHECK: vcmpequb [[RET:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]] @@ -62,7 +62,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_le: +; CHECK-LABEL: v16si8_cmp_le: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -73,7 +73,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_le: +; CHECK-LABEL: v16ui8_cmp_le: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -84,7 +84,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_lt: +; CHECK-LABEL: v16si8_cmp_lt: ; CHECK: vcmpgtsb 2, 3, 2 define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -93,7 +93,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_lt: +; CHECK-LABEL: v16ui8_cmp_lt: ; CHECK: vcmpgtub 2, 3, 2 define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -102,7 +102,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_gt: +; CHECK-LABEL: v16si8_cmp_gt: ; CHECK: vcmpgtsb 2, 2, 3 define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -111,7 +111,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_gt: +; CHECK-LABEL: v16ui8_cmp_gt: ; CHECK: vcmpgtub 2, 2, 3 define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -120,7 +120,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_ge: +; CHECK-LABEL: v16si8_cmp_ge: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -131,7 +131,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_ge: +; CHECK-LABEL: v16ui8_cmp_ge: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -142,7 +142,7 @@ define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone { %sext = sext <32 x i1> %cmp to <32 x i8> ret <32 x i8> %sext } -; CHECK: v32si8_cmp: +; CHECK-LABEL: v32si8_cmp: ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -152,7 +152,7 @@ define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone { %sext = sext <2 x i1> %cmp to <2 x i16> ret <2 x i16> %sext } -; CHECK: v2si16_cmp: +; CHECK-LABEL: v2si16_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -161,7 +161,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone { %sext = sext <4 x i1> %cmp to <4 x i16> ret <4 x i16> %sext } -; CHECK: v4si16_cmp: +; CHECK-LABEL: v4si16_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -173,7 +173,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_eq: +; CHECK-LABEL: v8si16_cmp_eq: ; CHECK: vcmpequh 2, 2, 3 define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -182,7 +182,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_ne: +; CHECK-LABEL: v8si16_cmp_ne: ; CHECK: vcmpequh [[RET:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]] @@ -192,7 +192,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_le: +; CHECK-LABEL: v8si16_cmp_le: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -203,7 +203,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_le: +; CHECK-LABEL: v8ui16_cmp_le: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -214,7 +214,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_lt: +; CHECK-LABEL: v8si16_cmp_lt: ; CHECK: vcmpgtsh 2, 3, 2 define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -223,7 +223,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_lt: +; CHECK-LABEL: v8ui16_cmp_lt: ; CHECK: vcmpgtuh 2, 3, 2 define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -232,7 +232,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_gt: +; CHECK-LABEL: v8si16_cmp_gt: ; CHECK: vcmpgtsh 2, 2, 3 define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -241,7 +241,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_gt: +; CHECK-LABEL: v8ui16_cmp_gt: ; CHECK: vcmpgtuh 2, 2, 3 define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -250,7 +250,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_ge: +; CHECK-LABEL: v8si16_cmp_ge: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -261,7 +261,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_ge: +; CHECK-LABEL: v8ui16_cmp_ge: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -272,7 +272,7 @@ define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone { %sext = sext <16 x i1> %cmp to <16 x i16> ret <16 x i16> %sext } -; CHECK: v16si16_cmp: +; CHECK-LABEL: v16si16_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -282,7 +282,7 @@ define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone { %sext = sext <32 x i1> %cmp to <32 x i16> ret <32 x i16> %sext } -; CHECK: v32si16_cmp: +; CHECK-LABEL: v32si16_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -294,7 +294,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone { %sext = sext <2 x i1> %cmp to <2 x i32> ret <2 x i32> %sext } -; CHECK: v2si32_cmp: +; CHECK-LABEL: v2si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -306,7 +306,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_eq: +; CHECK-LABEL: v4si32_cmp_eq: ; CHECK: vcmpequw 2, 2, 3 define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -315,7 +315,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_ne: +; CHECK-LABEL: v4si32_cmp_ne: ; CHECK: vcmpequw [[RCMP:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RCMP]], [[RCMP]] @@ -325,7 +325,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_le: +; CHECK-LABEL: v4si32_cmp_le: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -336,7 +336,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_le: +; CHECK-LABEL: v4ui32_cmp_le: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -347,7 +347,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_lt: +; CHECK-LABEL: v4si32_cmp_lt: ; CHECK: vcmpgtsw 2, 3, 2 define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -356,7 +356,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_lt: +; CHECK-LABEL: v4ui32_cmp_lt: ; CHECK: vcmpgtuw 2, 3, 2 define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -365,7 +365,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_gt: +; CHECK-LABEL: v4si32_cmp_gt: ; CHECK: vcmpgtsw 2, 2, 3 define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -374,7 +374,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_gt: +; CHECK-LABEL: v4ui32_cmp_gt: ; CHECK: vcmpgtuw 2, 2, 3 define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -383,7 +383,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_ge: +; CHECK-LABEL: v4si32_cmp_ge: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -394,7 +394,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_ge: +; CHECK-LABEL: v4ui32_cmp_ge: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -405,7 +405,7 @@ define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone { %sext = sext <8 x i1> %cmp to <8 x i32> ret <8 x i32> %sext } -; CHECK: v8si32_cmp: +; CHECK-LABEL: v8si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -415,7 +415,7 @@ define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone { %sext = sext <16 x i1> %cmp to <16 x i32> ret <16 x i32> %sext } -; CHECK: v16si32_cmp: +; CHECK-LABEL: v16si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -427,7 +427,7 @@ define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone { %sext = sext <32 x i1> %cmp to <32 x i32> ret <32 x i32> %sext } -; CHECK: v32si32_cmp: +; CHECK-LABEL: v32si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -445,7 +445,7 @@ entry: %0 = bitcast <2 x i32> %sext to <2 x float> ret <2 x float> %0 } -; CHECK: v2f32_cmp: +; CHECK-LABEL: v2f32_cmp: ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -458,7 +458,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_eq: +; CHECK-LABEL: v4f32_cmp_eq: ; CHECK: vcmpeqfp 2, 2, 3 define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone { @@ -468,7 +468,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_ne: +; CHECK-LABEL: v4f32_cmp_ne: ; CHECK: vcmpeqfp [[RET:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]] @@ -479,7 +479,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_le: +; CHECK-LABEL: v4f32_cmp_le: ; CHECK: vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -491,7 +491,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_lt: +; CHECK-LABEL: v4f32_cmp_lt: ; CHECK: vcmpgtfp 2, 3, 2 define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone { @@ -501,7 +501,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_ge: +; CHECK-LABEL: v4f32_cmp_ge: ; CHECK: vcmpgefp 2, 2, 3 define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone { @@ -511,7 +511,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_gt: +; CHECK-LABEL: v4f32_cmp_gt: ; CHECK: vcmpgtfp 2, 2, 3 @@ -522,6 +522,6 @@ entry: %0 = bitcast <8 x i32> %sext to <8 x float> ret <8 x float> %0 } -; CHECK: v8f32_cmp: +; CHECK-LABEL: v8f32_cmp: ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index e4799e5..f16b9f5 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { store <4 x float> %tmp13, <4 x float>* %P3 ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: CPI } define <4 x i32> @test_30() nounwind { ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > -; CHECK: test_30: +; CHECK-LABEL: test_30: ; CHECK: vspltisw ; CHECK-NEXT: vadduwm ; CHECK-NEXT: blr @@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind { define <4 x i32> @test_29() nounwind { ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > -; CHECK: test_29: +; CHECK-LABEL: test_29: ; CHECK: vspltisw ; CHECK-NEXT: vspltisw ; CHECK-NEXT: vsubuwm @@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind { define <8 x i16> @test_n30() nounwind { ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > -; CHECK: test_n30: +; CHECK-LABEL: test_n30: ; CHECK: vspltish ; CHECK-NEXT: vadduhm ; CHECK-NEXT: blr @@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind { define <16 x i8> @test_n104() nounwind { ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > -; CHECK: test_n104: +; CHECK-LABEL: test_n104: ; CHECK: vspltisb ; CHECK-NEXT: vslb ; CHECK-NEXT: blr @@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind { define <4 x i32> @test_vsldoi() nounwind { ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > -; CHECK: test_vsldoi: +; CHECK-LABEL: test_vsldoi: ; CHECK: vspltisw ; CHECK-NEXT: vsldoi ; CHECK-NEXT: blr @@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind { define <8 x i16> @test_vsldoi_65023() nounwind { ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > -; CHECK: test_vsldoi_65023: +; CHECK-LABEL: test_vsldoi_65023: ; CHECK: vspltish ; CHECK-NEXT: vsldoi ; CHECK-NEXT: blr @@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind { define <4 x i32> @test_rol() nounwind { ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > -; CHECK: test_rol: +; CHECK-LABEL: test_rol: ; CHECK: vspltisw ; CHECK-NEXT: vrlw ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll index a475e94..a39ae91 100644 --- a/test/CodeGen/PowerPC/vec_conv.ll +++ b/test/CodeGen/PowerPC/vec_conv.ll @@ -17,7 +17,7 @@ entry: store <4 x i32> %1, <4 x i32>* %y, align 16 ret void } -;CHECK: v4f32_to_v4i32: +;CHECK-LABEL: v4f32_to_v4i32: ;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0 @@ -29,7 +29,7 @@ entry: store <4 x i32> %1, <4 x i32>* %y, align 16 ret void } -;CHECK: v4f32_to_v4u32: +;CHECK-LABEL: v4f32_to_v4u32: ;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0 @@ -41,7 +41,7 @@ entry: store <4 x float> %1, <4 x float>* %y, align 16 ret void } -;CHECK: v4i32_to_v4f32: +;CHECK-LABEL: v4i32_to_v4f32: ;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0 @@ -53,5 +53,5 @@ entry: store <4 x float> %1, <4 x float>* %y, align 16 ret void } -;CHECK: v4u32_to_v4f32: +;CHECK-LABEL: v4u32_to_v4f32: ;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0 diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll index 998645d..6373a26 100644 --- a/test/CodeGen/PowerPC/vec_extload.ll +++ b/test/CodeGen/PowerPC/vec_extload.ll @@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) { %c = sext <16 x i4> %b to <16 x i8> ret <16 x i8> %c } -; CHECK: v16si8_sext_in_reg: +; CHECK-LABEL: v16si8_sext_in_reg: ; CHECK: vslb ; CHECK: vsrab ; CHECK: blr @@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) { %c = zext <16 x i4> %b to <16 x i8> ret <16 x i8> %c } -; CHECK: v16si8_zext_in_reg: +; CHECK-LABEL: v16si8_zext_in_reg: ; CHECK: vspltisb [[VMASK:[0-9]+]], 15 ; CHECK-NEXT: vand 2, 2, [[VMASK]] @@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) { %c = sext <8 x i8> %b to <8 x i16> ret <8 x i16> %c } -; CHECK: v8si16_sext_in_reg: +; CHECK-LABEL: v8si16_sext_in_reg: ; CHECK: vslh ; CHECK: vsrah ; CHECK: blr @@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) { %c = zext <8 x i8> %b to <8 x i16> ret <8 x i16> %c } -; CHECK: v8si16_zext_in_reg: +; CHECK-LABEL: v8si16_zext_in_reg: ; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2) ; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]] ; CHECK-NEXT: vand 2, 2, [[VMASK]] @@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) { %c = sext <4 x i16> %b to <4 x i32> ret <4 x i32> %c } -; CHECK: v4si32_sext_in_reg: +; CHECK-LABEL: v4si32_sext_in_reg: ; CHECK: vslw ; CHECK: vsraw ; CHECK: blr @@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) { %c = zext <4 x i16> %b to <4 x i32> ret <4 x i32> %c } -; CHECK: v4si32_zext_in_reg: +; CHECK-LABEL: v4si32_zext_in_reg: ; CHECK: vspltisw [[VMASK:[0-9]+]], -16 ; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]] ; CHECK-NEXT: vand 2, 2, [[VMASK]] diff --git a/test/CodeGen/PowerPC/vec_fmuladd.ll b/test/CodeGen/PowerPC/vec_fmuladd.ll new file mode 100644 index 0000000..5683b60 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_fmuladd.ll @@ -0,0 +1,56 @@ +; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +declare <2 x float> @llvm.fmuladd.v2f32(<2 x float> %val, <2 x float>, <2 x float>) +declare <4 x float> @llvm.fmuladd.v4f32(<4 x float> %val, <4 x float>, <4 x float>) +declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>) +declare <2 x double> @llvm.fmuladd.v2f64(<2 x double> %val, <2 x double>, <2 x double>) +declare <4 x double> @llvm.fmuladd.v4f64(<4 x double> %val, <4 x double>, <4 x double>) + +define <2 x float> @v2f32_fmuladd(<2 x float> %x) nounwind readnone { +entry: + %fmuladd = call <2 x float> @llvm.fmuladd.v2f32 (<2 x float> %x, <2 x float> %x, <2 x float> %x) + ret <2 x float> %fmuladd +} +; fmuladd (<2 x float>) is promoted to fmuladd (<4 x float>) +; CHECK-LABEL: v2f32_fmuladd: +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <4 x float> @v4f32_fmuladd(<4 x float> %x) nounwind readnone { +entry: + %fmuladd = call <4 x float> @llvm.fmuladd.v4f32 (<4 x float> %x, <4 x float> %x, <4 x float> %x) + ret <4 x float> %fmuladd +} +; CHECK-LABEL: v4f32_fmuladd: +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <8 x float> @v8f32_fmuladd(<8 x float> %x) nounwind readnone { +entry: + %fmuladd = call <8 x float> @llvm.fmuladd.v8f32 (<8 x float> %x, <8 x float> %x, <8 x float> %x) + ret <8 x float> %fmuladd +} +; CHECK-LABEL: v8f32_fmuladd: +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <2 x double> @v2f64_fmuladd(<2 x double> %x) nounwind readnone { +entry: + %fmuladd = call <2 x double> @llvm.fmuladd.v2f64 (<2 x double> %x, <2 x double> %x, <2 x double> %x) + ret <2 x double> %fmuladd +} +; CHECK-LABEL: v2f64_fmuladd: +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <4 x double> @v4f64_fmuladd(<4 x double> %x) nounwind readnone { +entry: + %fmuladd = call <4 x double> @llvm.fmuladd.v4f64 (<4 x double> %x, <4 x double> %x, <4 x double> %x) + ret <4 x double> %fmuladd +} +; CHECK-LABEL: v4f64_fmuladd: +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll index 53bc75d..c376751 100644 --- a/test/CodeGen/PowerPC/vec_mul.ll +++ b/test/CodeGen/PowerPC/vec_mul.ll @@ -6,7 +6,7 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1] ret <4 x i32> %tmp3 } -; CHECK: test_v4i32: +; CHECK-LABEL: test_v4i32: ; CHECK: vmsumuhm ; CHECK-NOT: mullw @@ -16,7 +16,7 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) { %tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1] ret <8 x i16> %tmp3 } -; CHECK: test_v8i16: +; CHECK-LABEL: test_v8i16: ; CHECK: vmladduhm ; CHECK-NOT: mullw @@ -26,7 +26,7 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) { %tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1] ret <16 x i8> %tmp3 } -; CHECK: test_v16i8: +; CHECK-LABEL: test_v16i8: ; CHECK: vmuloub ; CHECK: vmuleub ; CHECK-NOT: mullw @@ -40,7 +40,7 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) { ; Check the creation of a negative zero float vector by creating a vector of ; all bits set and shifting it 31 bits to left, resulting a an vector of ; 4 x 0x80000000 (-0.0 as float). -; CHECK: test_float: +; CHECK-LABEL: test_float: ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1 ; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]] ; CHECK: vmaddfp diff --git a/test/CodeGen/PowerPC/vec_rounding.ll b/test/CodeGen/PowerPC/vec_rounding.ll index 7c55638..ace187b 100644 --- a/test/CodeGen/PowerPC/vec_rounding.ll +++ b/test/CodeGen/PowerPC/vec_rounding.ll @@ -12,7 +12,7 @@ define <2 x double> @floor_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: floor_v2f64: +; CHECK-LABEL: floor_v2f64: ; CHECK: frim ; CHECK: frim @@ -22,7 +22,7 @@ define <4 x double> @floor_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: floor_v4f64: +; CHECK-LABEL: floor_v4f64: ; CHECK: frim ; CHECK: frim ; CHECK: frim @@ -34,7 +34,7 @@ define <2 x double> @ceil_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: ceil_v2f64: +; CHECK-LABEL: ceil_v2f64: ; CHECK: frip ; CHECK: frip @@ -44,7 +44,7 @@ define <4 x double> @ceil_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: ceil_v4f64: +; CHECK-LABEL: ceil_v4f64: ; CHECK: frip ; CHECK: frip ; CHECK: frip @@ -56,7 +56,7 @@ define <2 x double> @trunc_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: trunc_v2f64: +; CHECK-LABEL: trunc_v2f64: ; CHECK: friz ; CHECK: friz @@ -66,7 +66,7 @@ define <4 x double> @trunc_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: trunc_v4f64: +; CHECK-LABEL: trunc_v4f64: ; CHECK: friz ; CHECK: friz ; CHECK: friz @@ -78,7 +78,7 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: nearbyint_v2f64: +; CHECK-LABEL: nearbyint_v2f64: ; CHECK: bl nearbyint ; CHECK: bl nearbyint @@ -88,7 +88,7 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: nearbyint_v4f64: +; CHECK-LABEL: nearbyint_v4f64: ; CHECK: bl nearbyint ; CHECK: bl nearbyint ; CHECK: bl nearbyint @@ -101,7 +101,7 @@ define <4 x float> @floor_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: floor_v4f32: +; CHECK-LABEL: floor_v4f32: ; CHECK: vrfim declare <8 x float> @llvm.floor.v8f32(<8 x float> %p) @@ -110,7 +110,7 @@ define <8 x float> @floor_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: floor_v8f32: +; CHECK-LABEL: floor_v8f32: ; CHECK: vrfim ; CHECK: vrfim @@ -120,7 +120,7 @@ define <4 x float> @ceil_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: ceil_v4f32: +; CHECK-LABEL: ceil_v4f32: ; CHECK: vrfip declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p) @@ -129,7 +129,7 @@ define <8 x float> @ceil_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: ceil_v8f32: +; CHECK-LABEL: ceil_v8f32: ; CHECK: vrfip ; CHECK: vrfip @@ -139,7 +139,7 @@ define <4 x float> @trunc_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: trunc_v4f32: +; CHECK-LABEL: trunc_v4f32: ; CHECK: vrfiz declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p) @@ -148,7 +148,7 @@ define <8 x float> @trunc_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: trunc_v8f32: +; CHECK-LABEL: trunc_v8f32: ; CHECK: vrfiz ; CHECK: vrfiz @@ -158,7 +158,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: nearbyint_v4f32: +; CHECK-LABEL: nearbyint_v4f32: ; CHECK: vrfin declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) @@ -167,6 +167,6 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: nearbyint_v8f32: +; CHECK-LABEL: nearbyint_v8f32: ; CHECK: vrfin ; CHECK: vrfin diff --git a/test/CodeGen/PowerPC/vec_sqrt.ll b/test/CodeGen/PowerPC/vec_sqrt.ll index 055da1a..a85c3ff 100644 --- a/test/CodeGen/PowerPC/vec_sqrt.ll +++ b/test/CodeGen/PowerPC/vec_sqrt.ll @@ -18,7 +18,7 @@ entry: ret <2 x float> %sqrt } ; sqrt (<2 x float>) is promoted to sqrt (<4 x float>) -; CHECK: v2f32_sqrt: +; CHECK-LABEL: v2f32_sqrt: ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} @@ -29,7 +29,7 @@ entry: %sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x) ret <4 x float> %sqrt } -; CHECK: v4f32_sqrt: +; CHECK-LABEL: v4f32_sqrt: ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} @@ -40,7 +40,7 @@ entry: %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x) ret <8 x float> %sqrt } -; CHECK: v8f32_sqrt: +; CHECK-LABEL: v8f32_sqrt: ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} @@ -55,7 +55,7 @@ entry: %sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x) ret <2 x double> %sqrt } -; CHECK: v2f64_sqrt: +; CHECK-LABEL: v2f64_sqrt: ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} @@ -64,7 +64,7 @@ entry: %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x) ret <4 x double> %sqrt } -; CHECK: v4f64_sqrt: +; CHECK-LABEL: v4f64_sqrt: ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll index e4c3b0d..859a85a 100644 --- a/test/CodeGen/PowerPC/vector.ll +++ b/test/CodeGen/PowerPC/vector.ll @@ -59,6 +59,14 @@ define void @test_div(%f8* %P, %f8* %Q, %f8* %S) { ret void } +define void @test_rem(%f8* %P, %f8* %Q, %f8* %S) { + %p = load %f8* %P ; <%f8> [#uses=1] + %q = load %f8* %Q ; <%f8> [#uses=1] + %R = frem %f8 %p, %q ; <%f8> [#uses=1] + store %f8 %R, %f8* %S + ret void +} + ;;; TEST VECTOR CONSTRUCTS define void @test_cst(%f4* %P, %f4* %S) { diff --git a/test/CodeGen/PowerPC/vrspill.ll b/test/CodeGen/PowerPC/vrspill.ll index 9fb3d03..c3d1bf8 100644 --- a/test/CodeGen/PowerPC/vrspill.ll +++ b/test/CodeGen/PowerPC/vrspill.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s ; This verifies that we generate correct spill/reload code for vector regs. @@ -13,7 +13,6 @@ entry: ret void } -; CHECK: stvx 2, 1, -; CHECK: lvx 2, 1, +; CHECK: stvx 2, declare void @foo(i32*) diff --git a/test/CodeGen/PowerPC/zero-not-run.ll b/test/CodeGen/PowerPC/zero-not-run.ll new file mode 100644 index 0000000..04c4277 --- /dev/null +++ b/test/CodeGen/PowerPC/zero-not-run.ll @@ -0,0 +1,27 @@ +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define internal i32* @func_65(i32* %p_66) #0 { +entry: + br i1 undef, label %for.body, label %for.end731 + +for.body: ; preds = %entry + %0 = load i32* undef, align 4 + %or31 = or i32 %0, 319143828 + store i32 %or31, i32* undef, align 4 + %cmp32 = icmp eq i32 319143828, %or31 + %conv33 = zext i1 %cmp32 to i32 + %conv34 = sext i32 %conv33 to i64 + %call35 = call i64 @safe_mod_func_uint64_t_u_u(i64 %conv34, i64 -10) + unreachable + +for.end731: ; preds = %entry + ret i32* undef +} + +; Function Attrs: nounwind +declare i64 @safe_mod_func_uint64_t_u_u(i64, i64) #0 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } |