diff options
Diffstat (limited to 'test/CodeGen/X86')
64 files changed, 910 insertions, 623 deletions
diff --git a/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/test/CodeGen/X86/2006-11-12-CSRetCC.ll index 91210ea..6ec9a48 100644 --- a/test/CodeGen/X86/2006-11-12-CSRetCC.ll +++ b/test/CodeGen/X86/2006-11-12-CSRetCC.ll @@ -1,9 +1,14 @@ -; RUN: llc < %s -march=x86 | grep {subl \$4, %esp} +; RUN: llc < %s -march=x86 | FileCheck %s target triple = "i686-pc-linux-gnu" @str = internal constant [9 x i8] c"%f+%f*i\0A\00" ; <[9 x i8]*> [#uses=1] define i32 @main() { +; CHECK: main: +; CHECK-NOT: ret +; CHECK: subl $4, %{{.*}} +; CHECK: ret + entry: %retval = alloca i32, align 4 ; <i32*> [#uses=1] %tmp = alloca { double, double }, align 16 ; <{ double, double }*> [#uses=4] diff --git a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll index 10bbe74..b0eb1c5 100644 --- a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll +++ b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=x86 | grep {orl \$1, %eax} -; RUN: llc < %s -march=x86 | grep {leal 3(,%eax,8)} +; RUN: llc < %s -march=x86 | FileCheck %s ;; This example can't fold the or into an LEA. define i32 @test(float ** %tmp2, i32 %tmp12) nounwind { +; CHECK: test: +; CHECK-NOT: ret +; CHECK: orl $1, %{{.*}} +; CHECK: ret + %tmp3 = load float** %tmp2 %tmp132 = shl i32 %tmp12, 2 ; <i32> [#uses=1] %tmp4 = bitcast float* %tmp3 to i8* ; <i8*> [#uses=1] @@ -12,9 +16,13 @@ define i32 @test(float ** %tmp2, i32 %tmp12) nounwind { ret i32 %tmp14 } - ;; This can! define i32 @test2(i32 %a, i32 %b) nounwind { +; CHECK: test2: +; CHECK-NOT: ret +; CHECK: leal 3(,%{{.*}},8) +; CHECK: ret + %c = shl i32 %a, 3 %d = or i32 %c, 3 ret i32 %d diff --git a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll index a8f0e57..b48ce84 100644 --- a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll +++ b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll @@ -1,13 +1,17 @@ ; PR1219 -; RUN: llc < %s -march=x86 | grep {movl \$1, %eax} +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i1 %X) { -old_entry1: - %hvar2 = zext i1 %X to i32 +; CHECK: test: +; CHECK-NOT: ret +; CHECK: movl $1, %eax +; CHECK: ret + + %hvar2 = zext i1 %X to i32 %C = icmp sgt i32 %hvar2, -1 br i1 %C, label %cond_true15, label %cond_true cond_true15: - ret i32 1 + ret i32 1 cond_true: - ret i32 2 + ret i32 2 } diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll index 30453d5..e2cd750 100644 --- a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll +++ b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll @@ -1,9 +1,14 @@ -; RUN: llc < %s -march=x86 | grep {psrlw \$8, %xmm0} +; RUN: llc < %s -march=x86 | FileCheck %s target datalayout = "e-p:32:32" target triple = "i686-apple-darwin9" define void @test() { - tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 ) - ret void +; CHECK: test: +; CHECK-NOT: ret +; CHECK: psrlw $8, %xmm0 +; CHECK: ret + + tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 ) + ret void } diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll index 8518d4c..15466a1 100644 --- a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll +++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | FileCheck %s +; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i686-apple-darwin | FileCheck %s ; CHECK: "_-[NSString(local) isNullOrNil].eh": diff --git a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll index 38d6aa6..6e9a629 100644 --- a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll +++ b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll @@ -1,10 +1,14 @@ -; RUN: llc < %s | grep {1 \$2 3} +; RUN: llc < %s | FileCheck %s ; rdar://5720231 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" define void @test() nounwind { -entry: +; CHECK: test: +; CHECK-NOT: ret +; CHECK: 1 $2 3 +; CHECK: ret + tail call void asm sideeffect " ${0:c} $1 ${2:c} ", "imr,imr,i,~{dirflag},~{fpsr},~{flags}"( i32 1, i32 2, i32 3 ) nounwind ret void } diff --git a/test/CodeGen/X86/2008-12-05-SpillerCrash.ll b/test/CodeGen/X86/2008-12-05-SpillerCrash.ll deleted file mode 100644 index 7fd2e6f..0000000 --- a/test/CodeGen/X86/2008-12-05-SpillerCrash.ll +++ /dev/null @@ -1,237 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9.5 -mattr=+sse41 -relocation-model=pic - - %struct.XXActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } - %struct.XXAlphaTest = type { float, i16, i8, i8 } - %struct.XXArrayRange = type { i8, i8, i8, i8 } - %struct.XXBlendMode = type { i16, i16, i16, i16, %struct.ZZIColor4, i16, i16, i8, i8, i8, i8 } - %struct.XXBBRec = type opaque - %struct.XXBBstate = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, %struct.XXProgramLimits, %struct.XXProgramLimits, i8, i8, i8, i8, %struct.ZZSBB, %struct.ZZSBB, [4 x %struct.ZZSBB], %struct.ZZSBB, %struct.ZZSBB, %struct.ZZSBB, [8 x %struct.ZZSBB], %struct.ZZSBB } - %struct.XXClearColor = type { double, %struct.ZZIColor4, %struct.ZZIColor4, float, i32 } - %struct.XXClipPlane = type { i32, [6 x %struct.ZZIColor4] } - %struct.XXColorBB = type { i16, i8, i8, [8 x i16], i8, i8, i8, i8 } - %struct.XXColorMatrix = type { [16 x float]*, %struct.XXImagingColorScale } - %struct.XXConfig = type { i32, float, %struct.ZZGTransformKey, %struct.ZZGTransformKey, i8, i8, i8, i8, i8, i8, i16, i32, i32, i32, %struct.XXPixelFormatInfo, %struct.XXPointLineLimits, %struct.XXPointLineLimits, %struct.XXRenderFeatures, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.XXTextureLimits, [3 x %struct.XXPipelineProgramLimits], %struct.XXFragmentProgramLimits, %struct.XXVertexProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXVertexDescriptor*, %struct.XXVertexDescriptor*, [3 x i32], [4 x i32], [0 x i32] } - %struct.XXContextRec = type { float, float, float, float, float, float, float, float, %struct.ZZIColor4, %struct.ZZIColor4, %struct.YYFPContext, [16 x [2 x %struct.PPStreamToken]], %struct.ZZGProcessor, %struct._YYConstants*, void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)*, %struct._YYFunction*, %struct.PPStreamToken*, void (%struct.XXContextRec*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, %struct.XXVertex*)*, %struct._YYFunction*, %struct._YYFunction*, %struct._YYFunction*, [4 x i32], [3 x i32], [3 x i32], float, float, float, %struct.PPStreamToken, i32, %struct.ZZSDrawable, %struct.XXFramebufferRec*, %struct.XXFramebufferRec*, %struct.XXRect, %struct.XXFormat, %struct.XXFormat, %struct.XXFormat, %struct.XXConfig*, %struct.XXBBstate, %struct.XXBBstate, %struct.XXSharedRec*, %struct.XXState*, %struct.XXPluginState*, %struct.XXVertex*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.XXProgramRec*, %struct.XXPipelineProgramRec*, %struct.YYTextures, %struct.XXStippleData, i8, i16, i8, i32, i32, i32, %struct.XXQueryRec*, %struct.XXQueryRec*, %struct.XXFallback, { void (i8*, i8*, i32, i8*)* } } - %struct.XXConvolution = type { %struct.ZZIColor4, %struct.XXImagingColorScale, i16, i16, [0 x i32], float*, i32, i32 } - %struct.XXCurrent16A = type { [8 x %struct.ZZIColor4], [16 x %struct.ZZIColor4], %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, [4 x float], %struct.XXPointLineLimits, float, float, float, float, i8, i8, i8, i8 } - %struct.XXDepthTest = type { i16, i16, i8, i8, i8, i8, double, double } - %struct.XXDrawableWindow = type { i32, i32, i32 } - %struct.XXFallback = type { float*, %struct.XXRenderDispatch*, %struct.XXConfig*, i8*, i8*, i32, i32 } - %struct.XXFenceRec = type opaque - %struct.XXFixedFunction = type { %struct.PPStreamToken* } - %struct.XXFogMode = type { %struct.ZZIColor4, float, float, float, float, float, i16, i16, i16, i8, i8 } - %struct.XXFormat = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i32, i32, i32 } - %struct.XXFragmentProgramLimits = type { i32, i32, i32, i16, i16, i32, i32 } - %struct.XXFramebufferAttachment = type { i16, i16, i32, i32, i32 } - %struct.XXFramebufferData = type { [10 x %struct.XXFramebufferAttachment], [8 x i16], i16, i16, i16, i8, i8, i32, i32 } - %struct.XXFramebufferRec = type { %struct.XXFramebufferData*, %struct.XXPluginFramebufferData*, %struct.XXFormat, i8, i8, i8, i8 } - %struct.XXGeometryShaderLimits = type { i32, i32, i32, i32, i32 } - %struct.XXHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } - %struct.XXHistogram = type { %struct.XXProgramLimits*, i32, i16, i8, i8 } - %struct.XXImagingColorScale = type { %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2 } - %struct.XXImagingSubset = type { %struct.XXConvolution, %struct.XXConvolution, %struct.XXConvolution, %struct.XXColorMatrix, %struct.XXMinmax, %struct.XXHistogram, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, i32, [0 x i32] } - %struct.XXLight = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, float, float, float, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, float, float, float, float } - %struct.XXLightModel = type { %struct.ZZIColor4, [8 x %struct.XXLight], [2 x %struct.XXMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 } - %struct.XXLightProduct = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4 } - %struct.XXLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 } - %struct.XXLogicOp = type { i16, i8, i8 } - %struct.XXMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXMaterial = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, float, float, float, float, [8 x %struct.XXLightProduct], %struct.ZZIColor4, [8 x i32] } - %struct.XXMinmax = type { %struct.XXMinmaxTable*, i16, i8, i8, [0 x i32] } - %struct.XXMinmaxTable = type { %struct.ZZIColor4, %struct.ZZIColor4 } - %struct.XXMipmaplevel = type { [4 x i32], [4 x i32], [4 x float], [4 x i32], i32, i32, float*, i8*, i16, i16, i16, i16, [2 x float] } - %struct.XXMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXPipelineProgramData = type { i16, i8, i8, i32, %struct.PPStreamToken*, i64, %struct.ZZIColor4*, i32, [0 x i32] } - %struct.XXPipelineProgramLimits = type { i32, i16, i16, i32, i16, i16, i32, i32 } - %struct.XXPipelineProgramRec = type { %struct.XXPipelineProgramData*, %struct.PPStreamToken*, %struct.XXContextRec*, { %struct._YYFunction*, \2, \2, [20 x i32], [64 x i32], i32, i32, i32 }*, i32, i32 } - %struct.XXPipelineProgramState = type { i8, i8, i8, i8, [0 x i32], %struct.ZZIColor4* } - %struct.XXPixelFormatInfo = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXPixelMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.XXPixelMode = type { float, float, %struct.XXPixelStore, %struct.XXPixelTransfer, %struct.XXPixelMap, %struct.XXImagingSubset, i32, i32 } - %struct.XXPixelPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 } - %struct.XXPixelStore = type { %struct.XXPixelPack, %struct.XXPixelPack } - %struct.XXPixelTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float } - %struct.XXPluginFramebufferData = type { [10 x %struct.XXTextureRec*], i8, i8, i8, i8 } - %struct.XXPluginProgramData = type { [3 x %struct.XXPipelineProgramRec*], %struct.XXBBRec**, i32, [0 x i32] } - %struct.XXPluginState = type { [16 x [5 x %struct.XXTextureRec*]], [3 x %struct.XXTextureRec*], [3 x %struct.XXPipelineProgramRec*], [3 x %struct.XXPipelineProgramRec*], %struct.XXProgramRec*, %struct.XXVertexArrayRec*, [16 x %struct.XXBBRec*], %struct.XXFramebufferRec*, %struct.XXFramebufferRec* } - %struct.XXPointLineLimits = type { float, float, float } - %struct.XXPointMode = type { float, float, float, float, %struct.XXPointLineLimits, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 } - %struct.XXPolygonMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXProgramData = type { i32, i32, i32, i32, %struct.PPStreamToken*, i32*, i32, i32, i32, i32, i8, i8, i8, i8, [0 x i32] } - %struct.XXProgramLimits = type { i32, i32, i32, i32 } - %struct.XXProgramRec = type { %struct.XXProgramData*, %struct.XXPluginProgramData*, %struct.ZZIColor4**, i32 } - %struct.XXQueryRec = type { i32, i32, %struct.XXQueryRec* } - %struct.XXRect = type { i32, i32, i32, i32, i32, i32 } - %struct.XXRegisterCombiners = type { i8, i8, i8, i8, i32, [2 x %struct.ZZIColor4], [8 x %struct.XXRegisterCombinersPerStageState], %struct.XXRegisterCombinersFinalStageState } - %struct.XXRegisterCombinersFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XXRegisterCombinersPerVariableState] } - %struct.XXRegisterCombinersPerPortionState = type { [4 x %struct.XXRegisterCombinersPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 } - %struct.XXRegisterCombinersPerStageState = type { [2 x %struct.XXRegisterCombinersPerPortionState], [2 x %struct.ZZIColor4] } - %struct.XXRegisterCombinersPerVariableState = type { i16, i16, i16, i16 } - %struct.XXRenderDispatch = type { void (%struct.XXContextRec*, i32, float)*, void (%struct.XXContextRec*, i32)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, float, float, i8*, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32*)*, void (%struct.XXContextRec*, i32, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, %struct.XXFenceRec*)*, void (%struct.XXContextRec*, i32, %struct.XXQueryRec*)*, void (%struct.XXContextRec*, %struct.XXQueryRec*)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*, %struct.ZZIColor4*, %struct.XXCurrent16A*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32)*, i32 (%struct.XXContextRec*, %struct.XXBBRec*, i32, i32, i8*)*, void (%struct.XXContextRec*, i32)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXQueryRec*)*, void (%struct.XXContextRec*)* } - %struct.XXRenderFeatures = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXSWRSurfaceRec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i8*, [4 x i8*], i32 } - %struct.XXScissorTest = type { %struct.XXProgramLimits, i8, i8, i8, i8 } - %struct.XXSharedData = type { } - %struct.XXSharedRec = type { %struct.__ZZarrayelementDrawInfoListType, %struct.XXSharedData*, i32, i8, i8, i8, i8 } - %struct.XXState = type <{ i16, i16, i16, i16, i32, i32, [256 x %struct.ZZIColor4], [128 x %struct.ZZIColor4], %struct.XXViewport, %struct.XXTransform, %struct.XXLightModel, %struct.XXActiveTextureTargets, %struct.XXAlphaTest, %struct.XXBlendMode, %struct.XXClearColor, %struct.XXColorBB, %struct.XXDepthTest, %struct.XXArrayRange, %struct.XXFogMode, %struct.XXHintMode, %struct.XXLineMode, %struct.XXLogicOp, %struct.XXMaskMode, %struct.XXPixelMode, %struct.XXPointMode, %struct.XXPolygonMode, %struct.XXScissorTest, i32, %struct.XXStencilTest, [8 x %struct.XXTextureMode], [16 x %struct.XXTextureImageMode], %struct.XXArrayRange, [8 x %struct.XXTextureCoordGen], %struct.XXClipPlane, %struct.XXMultisample, %struct.XXRegisterCombiners, %struct.XXArrayRange, %struct.XXArrayRange, [3 x %struct.XXPipelineProgramState], %struct.XXArrayRange, %struct.XXTransformFeedback, i32*, %struct.XXFixedFunction, [1 x i32] }> - %struct.XXStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] } - %struct.XXStippleData = type { i32, i16, i16, [32 x [32 x i8]] } - %struct.XXTextureCoordGen = type { { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, i8, i8, i8, i8 } - %struct.XXTextureGeomState = type { i16, i16, i16, i16, i16, i8, i8, i8, i8, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [6 x i16], [6 x i16] } - %struct.XXTextureImageMode = type { float } - %struct.XXTextureLevel = type { i32, i32, i16, i16, i16, i8, i8, i16, i16, i16, i16, i8* } - %struct.XXTextureLimits = type { float, float, i16, i16, i16, i16, i16, i16, i16, i16, i16, i8, i8, [16 x i16], i32 } - %struct.XXTextureMode = type { %struct.ZZIColor4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float } - %struct.XXTextureParamState = type { i16, i16, i16, i16, i16, i16, %struct.ZZIColor4, float, float, float, float, i16, i16, i16, i16, float, i16, i8, i8, i32, i8* } - %struct.XXTextureRec = type { [4 x float], %struct.XXTextureState*, %struct.XXMipmaplevel*, %struct.XXMipmaplevel*, float, float, float, float, i8, i8, i8, i8, i16, i16, i16, i16, i32, float, [2 x %struct.PPStreamToken] } - %struct.XXTextureState = type { i16, i8, i8, i16, i16, float, i32, %struct.XXSWRSurfaceRec*, %struct.XXTextureParamState, %struct.XXTextureGeomState, i16, i16, i8*, %struct.XXTextureLevel, [1 x [15 x %struct.XXTextureLevel]] } - %struct.XXTransform = type <{ [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }> - %struct.XXTransformFeedback = type { i8, i8, i8, i8, [0 x i32], [16 x i32], [16 x i32] } - %struct.XXVertex = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.ZZIColor4, float, i8, i8, i8, i8, float, float, i32, i32, i32, i32, [4 x float], [2 x %struct.XXMaterial*], [2 x i32], [8 x %struct.ZZIColor4] } - %struct.XXVertexArrayRec = type opaque - %struct.XXVertexDescriptor = type { i8, i8, i8, i8, [0 x i32] } - %struct.XXVertexProgramLimits = type { i16, i16, i32, i32 } - %struct.XXViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float } - %struct.ZZGColorTable = type { i32, i32, i32, i8* } - %struct.ZZGOperation = type { i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, %struct.ZZGColorTable, %struct.ZZGColorTable, %struct.ZZGColorTable } - %struct.ZZGProcessor = type { void (%struct.XXPixelMode*, %struct.ZZGOperation*, %struct._ZZGProcessorData*, %union._ZZGFunctionKey*)*, %struct._YYFunction*, %union._ZZGFunctionKey*, %struct._ZZGProcessorData* } - %struct.ZZGTransformKey = type { i32, i32 } - %struct.ZZIColor4 = type { float, float, float, float } - %struct.ZZSBB = type { i8* } - %struct.ZZSDrawable = type { %struct.ZZSWindowRec* } - %struct.ZZSWindowRec = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, i32, i32, %struct.ZZSDrawable, i8*, i8*, i8*, i8*, i8*, [4 x i8*], i32, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, %struct.XXDrawableWindow, i32, i32, i8*, i8* } - %struct.ZZTCoord2 = type { float, float } - %struct.YYFPContext = type { float, i32, i32, i32, float, [3 x float] } - %struct.YYFragmentAttrib = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [8 x <4 x float>] } - %struct.YYTextures = type { [16 x %struct.XXTextureRec*] } - %struct.PPStreamToken = type { { i16, i16, i32 } } - %struct._ZZGProcessorData = type { void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, i8* (i32)*, void (i8*)* } - %struct._YYConstants = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [4096 x i8], [8 x float], [48 x float], [128 x float], [528 x i8], { void (i8*, i8*, i32, i8*)*, float (float)*, float (float)*, float (float)*, i32 (float)* } } - %struct._YYFunction = type opaque - %struct.__ZZarrayelementDrawInfoListType = type { i32, [40 x i8] } - %union._ZZGFunctionKey = type opaque -@llvm.used = appending global [1 x i8*] [ i8* bitcast (void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)* @t to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define void @t(%struct.XXContextRec* %ctx, i32 %x, i32 %y, %struct.YYFragmentAttrib* %start, %struct.YYFragmentAttrib* %deriv, i32 %num_frags) nounwind { -entry: - %tmp7485.i.i.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp8382.i.i.i = extractelement <4 x i32> zeroinitializer, i32 1 ; <i32> [#uses=1] - %tmp8383.i.i.i = extractelement <4 x i32> zeroinitializer, i32 2 ; <i32> [#uses=2] - %tmp8384.i.i.i = extractelement <4 x i32> zeroinitializer, i32 3 ; <i32> [#uses=2] - br label %bb7551.i.i.i - -bb4426.i.i.i: ; preds = %bb7551.i.i.i - %0 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1] - %1 = bitcast [4 x i32]* %0 to <4 x i32>* ; <<4 x i32>*> [#uses=1] - %2 = load <4 x i32>* %1, align 16 ; <<4 x i32>> [#uses=1] - %3 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1] - %4 = bitcast [4 x i32]* %3 to <4 x i32>* ; <<4 x i32>*> [#uses=1] - %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1] - %6 = shufflevector <4 x i32> %2, <4 x i32> %5, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x i32>> [#uses=1] - %7 = bitcast <4 x i32> %6 to <2 x i64> ; <<2 x i64>> [#uses=1] - %8 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %7, <2 x i32> < i32 1, i32 3 > ; <<2 x i64>> [#uses=1] - %9 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8382.i.i.i, i32 6 ; <float**> [#uses=1] - %10 = load float** %9, align 4 ; <float*> [#uses=1] - %11 = bitcast float* %10 to i8* ; <i8*> [#uses=1] - %12 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 6 ; <float**> [#uses=1] - %13 = load float** %12, align 4 ; <float*> [#uses=1] - %14 = bitcast float* %13 to i8* ; <i8*> [#uses=1] - %15 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 6 ; <float**> [#uses=1] - %16 = load float** %15, align 4 ; <float*> [#uses=1] - %17 = bitcast float* %16 to i8* ; <i8*> [#uses=1] - %tmp7308.i.i.i = and <2 x i64> zeroinitializer, %8 ; <<2 x i64>> [#uses=1] - %18 = bitcast <2 x i64> %tmp7308.i.i.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %19 = mul <4 x i32> %18, zeroinitializer ; <<4 x i32>> [#uses=1] - %20 = add <4 x i32> %19, zeroinitializer ; <<4 x i32>> [#uses=3] - %21 = load i32* null, align 4 ; <i32> [#uses=0] - %22 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> zeroinitializer) nounwind readnone ; <<4 x float>> [#uses=1] - %23 = fmul <4 x float> %22, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2114.i119.i.i = extractelement <4 x i32> %20, i32 1 ; <i32> [#uses=1] - %24 = shl i32 %tmp2114.i119.i.i, 2 ; <i32> [#uses=1] - %25 = getelementptr i8* %11, i32 %24 ; <i8*> [#uses=1] - %26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1] - %27 = load i32* %26, align 4 ; <i32> [#uses=1] - %28 = or i32 %27, -16777216 ; <i32> [#uses=1] - %tmp1927.i120.i.i = insertelement <4 x i32> undef, i32 %28, i32 0 ; <<4 x i32>> [#uses=1] - %29 = bitcast <4 x i32> %tmp1927.i120.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %30 = shufflevector <16 x i8> %29, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %31 = bitcast <16 x i8> %30 to <8 x i16> ; <<8 x i16>> [#uses=1] - %32 = shufflevector <8 x i16> %31, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %33 = bitcast <8 x i16> %32 to <4 x i32> ; <<4 x i32>> [#uses=1] - %34 = shufflevector <4 x i32> %33, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %35 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %34) nounwind readnone ; <<4 x float>> [#uses=1] - %36 = fmul <4 x float> %35, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2113.i124.i.i = extractelement <4 x i32> %20, i32 2 ; <i32> [#uses=1] - %37 = shl i32 %tmp2113.i124.i.i, 2 ; <i32> [#uses=1] - %38 = getelementptr i8* %14, i32 %37 ; <i8*> [#uses=1] - %39 = bitcast i8* %38 to i32* ; <i32*> [#uses=1] - %40 = load i32* %39, align 4 ; <i32> [#uses=1] - %41 = or i32 %40, -16777216 ; <i32> [#uses=1] - %tmp1963.i125.i.i = insertelement <4 x i32> undef, i32 %41, i32 0 ; <<4 x i32>> [#uses=1] - %42 = bitcast <4 x i32> %tmp1963.i125.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %43 = shufflevector <16 x i8> %42, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %44 = bitcast <16 x i8> %43 to <8 x i16> ; <<8 x i16>> [#uses=1] - %45 = shufflevector <8 x i16> %44, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %46 = bitcast <8 x i16> %45 to <4 x i32> ; <<4 x i32>> [#uses=1] - %47 = shufflevector <4 x i32> %46, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %48 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %47) nounwind readnone ; <<4 x float>> [#uses=1] - %49 = fmul <4 x float> %48, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2112.i129.i.i = extractelement <4 x i32> %20, i32 3 ; <i32> [#uses=1] - %50 = shl i32 %tmp2112.i129.i.i, 2 ; <i32> [#uses=1] - %51 = getelementptr i8* %17, i32 %50 ; <i8*> [#uses=1] - %52 = bitcast i8* %51 to i32* ; <i32*> [#uses=1] - %53 = load i32* %52, align 4 ; <i32> [#uses=1] - %54 = or i32 %53, -16777216 ; <i32> [#uses=1] - %tmp1999.i130.i.i = insertelement <4 x i32> undef, i32 %54, i32 0 ; <<4 x i32>> [#uses=1] - %55 = bitcast <4 x i32> %tmp1999.i130.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %56 = shufflevector <16 x i8> %55, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %57 = bitcast <16 x i8> %56 to <8 x i16> ; <<8 x i16>> [#uses=1] - %58 = shufflevector <8 x i16> %57, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %59 = bitcast <8 x i16> %58 to <4 x i32> ; <<4 x i32>> [#uses=1] - %60 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %61 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %60) nounwind readnone ; <<4 x float>> [#uses=1] - %62 = fmul <4 x float> %61, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %63 = fmul <4 x float> %23, zeroinitializer ; <<4 x float>> [#uses=1] - %64 = fadd <4 x float> zeroinitializer, %63 ; <<4 x float>> [#uses=1] - %65 = fmul <4 x float> %36, zeroinitializer ; <<4 x float>> [#uses=1] - %66 = fadd <4 x float> zeroinitializer, %65 ; <<4 x float>> [#uses=1] - %67 = fmul <4 x float> %49, zeroinitializer ; <<4 x float>> [#uses=1] - %68 = fadd <4 x float> zeroinitializer, %67 ; <<4 x float>> [#uses=1] - %69 = fmul <4 x float> %62, zeroinitializer ; <<4 x float>> [#uses=1] - %70 = fadd <4 x float> zeroinitializer, %69 ; <<4 x float>> [#uses=1] - %tmp7452.i.i.i = bitcast <4 x float> %64 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7454.i.i.i = and <4 x i32> %tmp7452.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7459.i.i.i = or <4 x i32> %tmp7454.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7460.i.i.i = bitcast <4 x i32> %tmp7459.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7468.i.i.i = bitcast <4 x float> %66 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7470.i.i.i = and <4 x i32> %tmp7468.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7475.i.i.i = or <4 x i32> %tmp7470.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7476.i.i.i = bitcast <4 x i32> %tmp7475.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7479.i.i.i = bitcast <4 x float> %.279.1.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7480.i.i.i = and <4 x i32> zeroinitializer, %tmp7479.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7484.i.i.i = bitcast <4 x float> %68 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7486.i.i.i = and <4 x i32> %tmp7484.i.i.i, %tmp7485.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7491.i.i.i = or <4 x i32> %tmp7486.i.i.i, %tmp7480.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7492.i.i.i = bitcast <4 x i32> %tmp7491.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7495.i.i.i = bitcast <4 x float> %.380.1.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7496.i.i.i = and <4 x i32> zeroinitializer, %tmp7495.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7500.i.i.i = bitcast <4 x float> %70 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7502.i.i.i = and <4 x i32> %tmp7500.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7507.i.i.i = or <4 x i32> %tmp7502.i.i.i, %tmp7496.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7508.i.i.i = bitcast <4 x i32> %tmp7507.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %indvar.next.i.i.i = add i32 %aniso.0.i.i.i, 1 ; <i32> [#uses=1] - br label %bb7551.i.i.i - -bb7551.i.i.i: ; preds = %bb4426.i.i.i, %entry - %.077.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7460.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0] - %.178.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7476.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0] - %.279.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7492.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1] - %.380.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7508.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1] - %aniso.0.i.i.i = phi i32 [ 0, %entry ], [ %indvar.next.i.i.i, %bb4426.i.i.i ] ; <i32> [#uses=1] - br i1 false, label %glvmInterpretFPTransformFour6.exit, label %bb4426.i.i.i - -glvmInterpretFPTransformFour6.exit: ; preds = %bb7551.i.i.i - unreachable -} - -declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone diff --git a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll index 2e148ad..d64c966 100644 --- a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll +++ b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll @@ -1,18 +1,24 @@ -; RUN: llc < %s -march=x86 | grep {\$-81920} | count 3 -; RUN: llc < %s -march=x86 | grep {\$4294885376} | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s ; ModuleID = 'shant.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin9.6" define void @f() nounwind { -entry: +; CHECK: f: +; CHECK-NOT: ret +; CHECK: foo $-81920 +; CHECK-NOT: ret +; CHECK: foo $-81920 +; CHECK-NOT: ret +; CHECK: foo $-81920 +; CHECK-NOT: ret +; CHECK: foo $4294885376 +; CHECK: ret + call void asm sideeffect "foo $0", "n,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind call void asm sideeffect "foo $0", "i,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind call void asm sideeffect "foo $0", "e,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind call void asm sideeffect "foo $0", "Z,~{dirflag},~{fpsr},~{flags}"(i64 4294885376) nounwind - br label %return - -return: ; preds = %entry ret void } diff --git a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll deleted file mode 100644 index f739216..0000000 --- a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll +++ /dev/null @@ -1,121 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 77 -; rdar://6802189 - -; Test if linearscan is unfavoring registers for allocation to allow more reuse -; of reloads from stack slots. - - %struct.SHA_CTX = type { i32, i32, i32, i32, i32, i32, i32, [16 x i32], i32 } - -define fastcc void @sha1_block_data_order(%struct.SHA_CTX* nocapture %c, i8* %p, i64 %num) nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %asmtmp511 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=3] - %asmtmp513 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=2] - %asmtmp516 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1] - %asmtmp517 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2] - %0 = xor i32 0, %asmtmp513 ; <i32> [#uses=0] - %1 = add i32 0, %asmtmp517 ; <i32> [#uses=1] - %2 = add i32 %1, 0 ; <i32> [#uses=1] - %3 = add i32 %2, 0 ; <i32> [#uses=1] - %asmtmp519 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1] - %4 = xor i32 0, %asmtmp511 ; <i32> [#uses=1] - %asmtmp520 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %4) nounwind ; <i32> [#uses=2] - %5 = xor i32 0, %asmtmp516 ; <i32> [#uses=1] - %6 = xor i32 %5, %asmtmp519 ; <i32> [#uses=1] - %7 = add i32 %asmtmp513, -899497514 ; <i32> [#uses=1] - %8 = add i32 %7, %asmtmp520 ; <i32> [#uses=1] - %9 = add i32 %8, %6 ; <i32> [#uses=1] - %10 = add i32 %9, 0 ; <i32> [#uses=1] - %asmtmp523 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=1] - %asmtmp525 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %3) nounwind ; <i32> [#uses=2] - %11 = xor i32 0, %asmtmp525 ; <i32> [#uses=1] - %12 = add i32 0, %11 ; <i32> [#uses=1] - %13 = add i32 %12, 0 ; <i32> [#uses=2] - %asmtmp528 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %10) nounwind ; <i32> [#uses=1] - %14 = xor i32 0, %asmtmp520 ; <i32> [#uses=1] - %asmtmp529 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %14) nounwind ; <i32> [#uses=1] - %asmtmp530 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %13) nounwind ; <i32> [#uses=1] - %15 = add i32 0, %asmtmp530 ; <i32> [#uses=1] - %16 = xor i32 0, %asmtmp523 ; <i32> [#uses=1] - %asmtmp532 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %16) nounwind ; <i32> [#uses=2] - %asmtmp533 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %15) nounwind ; <i32> [#uses=1] - %17 = xor i32 %13, %asmtmp528 ; <i32> [#uses=1] - %18 = xor i32 %17, 0 ; <i32> [#uses=1] - %19 = add i32 %asmtmp525, -899497514 ; <i32> [#uses=1] - %20 = add i32 %19, %asmtmp532 ; <i32> [#uses=1] - %21 = add i32 %20, %18 ; <i32> [#uses=1] - %22 = add i32 %21, %asmtmp533 ; <i32> [#uses=1] - %23 = xor i32 0, %asmtmp511 ; <i32> [#uses=1] - %24 = xor i32 %23, 0 ; <i32> [#uses=1] - %asmtmp535 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %24) nounwind ; <i32> [#uses=3] - %25 = add i32 0, %asmtmp535 ; <i32> [#uses=1] - %26 = add i32 %25, 0 ; <i32> [#uses=1] - %27 = add i32 %26, 0 ; <i32> [#uses=1] - %28 = xor i32 0, %asmtmp529 ; <i32> [#uses=0] - %29 = xor i32 %22, 0 ; <i32> [#uses=1] - %30 = xor i32 %29, 0 ; <i32> [#uses=1] - %31 = add i32 0, %30 ; <i32> [#uses=1] - %32 = add i32 %31, 0 ; <i32> [#uses=3] - %asmtmp541 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2] - %asmtmp542 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %32) nounwind ; <i32> [#uses=1] - %33 = add i32 0, %asmtmp541 ; <i32> [#uses=1] - %34 = add i32 %33, 0 ; <i32> [#uses=1] - %35 = add i32 %34, %asmtmp542 ; <i32> [#uses=1] - %asmtmp543 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %27) nounwind ; <i32> [#uses=2] - %36 = xor i32 0, %asmtmp535 ; <i32> [#uses=0] - %37 = xor i32 %32, 0 ; <i32> [#uses=1] - %38 = xor i32 %37, %asmtmp543 ; <i32> [#uses=1] - %39 = add i32 0, %38 ; <i32> [#uses=1] - %40 = add i32 %39, 0 ; <i32> [#uses=2] - %asmtmp546 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %32) nounwind ; <i32> [#uses=1] - %asmtmp547 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2] - %41 = add i32 0, -899497514 ; <i32> [#uses=1] - %42 = add i32 %41, %asmtmp547 ; <i32> [#uses=1] - %43 = add i32 %42, 0 ; <i32> [#uses=1] - %44 = add i32 %43, 0 ; <i32> [#uses=3] - %asmtmp549 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %35) nounwind ; <i32> [#uses=2] - %45 = xor i32 0, %asmtmp541 ; <i32> [#uses=1] - %asmtmp550 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %45) nounwind ; <i32> [#uses=2] - %asmtmp551 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %44) nounwind ; <i32> [#uses=1] - %46 = xor i32 %40, %asmtmp546 ; <i32> [#uses=1] - %47 = xor i32 %46, %asmtmp549 ; <i32> [#uses=1] - %48 = add i32 %asmtmp543, -899497514 ; <i32> [#uses=1] - %49 = add i32 %48, %asmtmp550 ; <i32> [#uses=1] - %50 = add i32 %49, %47 ; <i32> [#uses=1] - %51 = add i32 %50, %asmtmp551 ; <i32> [#uses=1] - %asmtmp552 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %40) nounwind ; <i32> [#uses=2] - %52 = xor i32 %44, %asmtmp549 ; <i32> [#uses=1] - %53 = xor i32 %52, %asmtmp552 ; <i32> [#uses=1] - %54 = add i32 0, %53 ; <i32> [#uses=1] - %55 = add i32 %54, 0 ; <i32> [#uses=2] - %asmtmp555 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %44) nounwind ; <i32> [#uses=2] - %56 = xor i32 0, %asmtmp532 ; <i32> [#uses=1] - %57 = xor i32 %56, %asmtmp547 ; <i32> [#uses=1] - %asmtmp556 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %57) nounwind ; <i32> [#uses=1] - %58 = add i32 0, %asmtmp556 ; <i32> [#uses=1] - %59 = add i32 %58, 0 ; <i32> [#uses=1] - %60 = add i32 %59, 0 ; <i32> [#uses=1] - %asmtmp558 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %51) nounwind ; <i32> [#uses=1] - %61 = xor i32 %asmtmp517, %asmtmp511 ; <i32> [#uses=1] - %62 = xor i32 %61, %asmtmp535 ; <i32> [#uses=1] - %63 = xor i32 %62, %asmtmp550 ; <i32> [#uses=1] - %asmtmp559 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %63) nounwind ; <i32> [#uses=1] - %64 = xor i32 %55, %asmtmp555 ; <i32> [#uses=1] - %65 = xor i32 %64, %asmtmp558 ; <i32> [#uses=1] - %asmtmp561 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %55) nounwind ; <i32> [#uses=1] - %66 = add i32 %asmtmp552, -899497514 ; <i32> [#uses=1] - %67 = add i32 %66, %65 ; <i32> [#uses=1] - %68 = add i32 %67, %asmtmp559 ; <i32> [#uses=1] - %69 = add i32 %68, 0 ; <i32> [#uses=1] - %70 = add i32 %69, 0 ; <i32> [#uses=1] - store i32 %70, i32* null, align 4 - %71 = add i32 0, %60 ; <i32> [#uses=1] - store i32 %71, i32* null, align 4 - %72 = add i32 0, %asmtmp561 ; <i32> [#uses=1] - store i32 %72, i32* null, align 4 - %73 = add i32 0, %asmtmp555 ; <i32> [#uses=1] - store i32 %73, i32* null, align 4 - br label %bb -} diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll index 1e7a418..0700323 100644 --- a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll +++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll @@ -22,8 +22,11 @@ return: ; preds = %entry define void @t2() nounwind ssp { entry: ; CHECK: t2: -; CHECK: movl %eax, %ecx -; CHECK: %ecx = foo (%ecx, %eax) +; CHECK: movl +; CHECK: [[D2:%e.x]] = foo +; CHECK: ([[D2]], +; CHECK-NOT: [[D2]] +; CHECK: ) %b = alloca i32 ; <i32*> [#uses=2] %a = alloca i32 ; <i32*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] diff --git a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll index c5d3d16..739a27a 100644 --- a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll +++ b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll @@ -22,6 +22,7 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %0 = type { %"union gimple_statement_d"* } %"BITMAP_WORD[]" = type [2 x i64] +%"uchar[]" = type [1 x i8] %"char[]" = type [4 x i8] %"enum dom_state[]" = type [2 x i32] %"int[]" = type [4 x i32] @@ -61,6 +62,7 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %"struct gimple_seq_d" = type { %"struct gimple_seq_node_d"*, %"struct gimple_seq_node_d"*, %"struct gimple_seq_d"* } %"struct gimple_seq_node_d" = type { %"union gimple_statement_d"*, %"struct gimple_seq_node_d"*, %"struct gimple_seq_node_d"* } %"struct gimple_statement_base" = type { i8, i8, i16, i32, i32, i32, %"struct basic_block_def"*, %"union tree_node"* } +%"struct phi_arg_d[]" = type [1 x %"struct phi_arg_d"] %"struct gimple_statement_phi" = type { %"struct gimple_statement_base", i32, i32, %"union tree_node"*, %"struct phi_arg_d[]" } %"struct htab" = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i64, i64, i64, i32, i32, i8* (i64, i64)*, void (i8*)*, i8*, i8* (i8*, i64, i64)*, void (i8*, i8*)*, i32 } %"struct iv" = type { %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, i8, i8, i32 } @@ -78,7 +80,6 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %"struct object_block" = type { %"union section"*, i32, i64, %"struct VEC_rtx_gc"*, %"struct VEC_rtx_gc"* } %"struct obstack" = type { i64, %"struct _obstack_chunk"*, i8*, i8*, i8*, i64, i32, %"struct _obstack_chunk"* (i8*, i64)*, void (i8*, %"struct _obstack_chunk"*)*, i8*, i8 } %"struct phi_arg_d" = type { %"struct ssa_use_operand_d", %"union tree_node"*, i32 } -%"struct phi_arg_d[]" = type [1 x %"struct phi_arg_d"] %"struct pointer_map_t" = type opaque %"struct pt_solution" = type { i8, %"struct bitmap_head_def"* } %"struct rtx_def" = type { i16, i8, i8, %"union u" } @@ -98,7 +99,6 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %"struct unnamed_section" = type { %"struct section_common", void (i8*)*, i8*, %"union section"* } %"struct use_optype_d" = type { %"struct use_optype_d"*, %"struct ssa_use_operand_d" } %"struct version_info" = type { %"union tree_node"*, %"struct iv"*, i8, i32, i8 } -%"uchar[]" = type [1 x i8] %"union basic_block_il_dependent" = type { %"struct gimple_bb_info"* } %"union edge_def_insns" = type { %"struct gimple_seq_d"* } %"union gimple_statement_d" = type { %"struct gimple_statement_phi" } diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll index 1c7c28c..9a5958e 100644 --- a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll +++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s ; rdar://7842028 ; Do not delete partially dead copy instructions. diff --git a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll index bb1db59..05f581a 100644 --- a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll +++ b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll @@ -1,4 +1,4 @@ -; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic -disable-fp-elim < %s | FileCheck %s +; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s ; <rdar://problem/8124405> %struct.type = type { %struct.subtype*, i32, i8, i32, i8, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, [256 x i32], i32, [257 x i32], [257 x i32], i32*, i16*, i8*, i32, i32, i32, i32, i32, [256 x i8], [16 x i8], [256 x i8], [4096 x i8], [16 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, i32*, i32* } diff --git a/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll b/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll index be7d94c..e96da94 100644 --- a/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll +++ b/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=i486 +; RUN: llc < %s -mcpu=core2 ; PR7375 ; ; This function contains a block (while.cond) with a lonely RFP use that is diff --git a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll index eaede30..1b33977 100644 --- a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll +++ b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -combiner-alias-analysis -march=x86-64 | FileCheck %s +; RUN: llc < %s -combiner-alias-analysis -march=x86-64 -mcpu=core2 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.4" diff --git a/test/CodeGen/X86/2010-11-09-MOVLPS.ll b/test/CodeGen/X86/2010-11-09-MOVLPS.ll index 2368f3f..710cb86 100644 --- a/test/CodeGen/X86/2010-11-09-MOVLPS.ll +++ b/test/CodeGen/X86/2010-11-09-MOVLPS.ll @@ -5,11 +5,11 @@ target triple = "x86_64-unknown-linux-gnu" module asm "\09.ident\09\22GCC: (GNU) 4.5.2 20100914 (prerelease) LLVM: 114628\22" +%"int[]" = type [4 x i32] %0 = type { %"int[]" } %float = type float %"float[]" = type [4 x float] %int = type i32 -%"int[]" = type [4 x i32] %"long unsigned int" = type i64 define void @swizzle(i8* %a, %0* %b, %0* %c) nounwind { diff --git a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll index 07b1971..c6f4b49 100644 --- a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll +++ b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=yonah | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s ; Reduced from JavaScriptCore %"class.JSC::CodeLocationCall" = type { [8 x i8] } diff --git a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll new file mode 100644 index 0000000..7632034 --- /dev/null +++ b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=x86-64 < %s -disable-fp-elim | FileCheck %s + +; This test is checking that we don't crash and we don't incorrectly fold +; a large displacement and a frame index into a single lea. +; <rdar://problem/9763308> + +declare void @bar([39 x i8]*) +define i32 @f(i64 %a, i64 %b) nounwind readnone { +entry: + %stack_main = alloca [39 x i8] + call void @bar([39 x i8]* %stack_main) + %tmp6 = add i64 %a, -2147483647 + %.sum = add i64 %tmp6, %b + %tmp8 = getelementptr inbounds [39 x i8]* %stack_main, i64 0, i64 %.sum + %tmp9 = load i8* %tmp8, align 1 + %tmp10 = sext i8 %tmp9 to i32 + ret i32 %tmp10 +} +; CHECK: f: +; CHECK: movsbl -2147483647 diff --git a/test/CodeGen/X86/allrem-moddi3.ll b/test/CodeGen/X86/allrem-moddi3.ll new file mode 100644 index 0000000..0c3d04f --- /dev/null +++ b/test/CodeGen/X86/allrem-moddi3.ll @@ -0,0 +1,19 @@ +; Test that, for a 64 bit signed rem, a libcall to allrem is made on Windows +; unless we have libgcc. + +; RUN: llc < %s -mtriple i386-pc-win32 | FileCheck %s +; RUN: llc < %s -mtriple i386-pc-cygwin | FileCheck %s -check-prefix USEMODDI +; RUN: llc < %s -mtriple i386-pc-mingw32 | FileCheck %s -check-prefix USEMODDI +; PR10305 +; END. + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly { +entry: + %conv4 = sext i32 %argc to i64 + %div = srem i64 84, %conv4 + %conv7 = trunc i64 %div to i32 + ret i32 %conv7 +} + +; CHECK: allrem +; USEMODDI: moddi3 diff --git a/test/CodeGen/X86/asm-global-imm.ll b/test/CodeGen/X86/asm-global-imm.ll index 96da224..6c569d6 100644 --- a/test/CodeGen/X86/asm-global-imm.ll +++ b/test/CodeGen/X86/asm-global-imm.ll @@ -1,7 +1,4 @@ -; RUN: llc < %s -march=x86 -relocation-model=static | \ -; RUN: grep {test1 \$_GV} -; RUN: llc < %s -march=x86 -relocation-model=static | \ -; RUN: grep {test2 _GV} +; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s ; PR882 target datalayout = "e-p:32:32" @@ -10,7 +7,13 @@ target triple = "i686-apple-darwin9.0.0d2" @str = external global [12 x i8] ; <[12 x i8]*> [#uses=1] define void @foo() { -entry: +; CHECK: foo: +; CHECK-NOT: ret +; CHECK: test1 $_GV +; CHECK-NOT: ret +; CHECK: test2 _GV +; CHECK: ret + tail call void asm sideeffect "test1 $0", "i,~{dirflag},~{fpsr},~{flags}"( i32* @GV ) tail call void asm sideeffect "test2 ${0:c}", "i,~{dirflag},~{fpsr},~{flags}"( i32* @GV ) ret void diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll index 9db6f6f..164252d 100644 --- a/test/CodeGen/X86/atomic-or.ll +++ b/test/CodeGen/X86/atomic-or.ll @@ -11,7 +11,7 @@ entry: ; CHECK: t1: ; CHECK: movl $2147483648, %eax ; CHECK: lock -; CHECK-NEXT: orq %rax, (%rdi) +; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}}) %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648) call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) ret void @@ -26,7 +26,7 @@ entry: ; CHECK: t2: ; CHECK-NOT: movl ; CHECK: lock -; CHECK-NEXT: orq $2147483644, (%rdi) +; CHECK-NEXT: orq $2147483644, (%r{{.*}}) %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644) call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) ret void diff --git a/test/CodeGen/X86/avx-128.ll b/test/CodeGen/X86/avx-128.ll index c29cb5d..57a3826 100644 --- a/test/CodeGen/X86/avx-128.ll +++ b/test/CodeGen/X86/avx-128.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s @z = common global <4 x float> zeroinitializer, align 16 @@ -20,3 +20,35 @@ entry: store double %conv, double* %d, align 8 ret void } + +; CHECK: vcvtsi2sdq (% +define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i64* %e, align 8 + %conv = sitofp i64 %tmp1 to double + ret double %conv +} + +; CHECK: vcvtsi2sd (% +define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i32* %e, align 4 + %conv = sitofp i32 %tmp1 to double + ret double %conv +} + +; CHECK: vcvtsi2ss (% +define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i32* %e, align 4 + %conv = sitofp i32 %tmp1 to float + ret float %conv +} + +; CHECK: vcvtsi2ssq (% +define float @funcD(i64* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i64* %e, align 8 + %conv = sitofp i64 %tmp1 to float + ret float %conv +} diff --git a/test/CodeGen/X86/avx-256-arith.ll b/test/CodeGen/X86/avx-256-arith.ll new file mode 100644 index 0000000..5c512db --- /dev/null +++ b/test/CodeGen/X86/avx-256-arith.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vaddpd +define <4 x double> @addpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <4 x double> %x, %y + ret <4 x double> %add.i +} + +; CHECK: vaddpd LCP{{.*}}(%rip) +define <4 x double> @addpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00> + ret <4 x double> %add.i +} + +; CHECK: vaddps +define <8 x float> @addps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <8 x float> %x, %y + ret <8 x float> %add.i +} + +; CHECK: vaddps LCP{{.*}}(%rip) +define <8 x float> @addps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000> + ret <8 x float> %add.i +} + +; CHECK: vsubpd +define <4 x double> @subpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %sub.i = fsub <4 x double> %x, %y + ret <4 x double> %sub.i +} + +; CHECK: vsubpd (% +define <4 x double> @subpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <4 x double>* %x, align 32 + %sub.i = fsub <4 x double> %y, %tmp2 + ret <4 x double> %sub.i +} + +; CHECK: vsubps +define <8 x float> @subps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %sub.i = fsub <8 x float> %x, %y + ret <8 x float> %sub.i +} + +; CHECK: vsubps (% +define <8 x float> @subps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <8 x float>* %x, align 32 + %sub.i = fsub <8 x float> %y, %tmp2 + ret <8 x float> %sub.i +} + +; CHECK: vmulpd +define <4 x double> @mulpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <4 x double> %x, %y + ret <4 x double> %mul.i +} + +; CHECK: vmulpd LCP{{.*}}(%rip) +define <4 x double> @mulpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00> + ret <4 x double> %mul.i +} + +; CHECK: vmulps +define <8 x float> @mulps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <8 x float> %x, %y + ret <8 x float> %mul.i +} + +; CHECK: vmulps LCP{{.*}}(%rip) +define <8 x float> @mulps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000> + ret <8 x float> %mul.i +} + +; CHECK: vdivpd +define <4 x double> @divpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <4 x double> %x, %y + ret <4 x double> %div.i +} + +; CHECK: vdivpd LCP{{.*}}(%rip) +define <4 x double> @divpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00> + ret <4 x double> %div.i +} + +; CHECK: vdivps +define <8 x float> @divps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <8 x float> %x, %y + ret <8 x float> %div.i +} + +; CHECK: vdivps LCP{{.*}}(%rip) +define <8 x float> @divps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000> + ret <8 x float> %div.i +} + diff --git a/test/CodeGen/X86/avx-256-arith.s b/test/CodeGen/X86/avx-256-arith.s new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/test/CodeGen/X86/avx-256-arith.s diff --git a/test/CodeGen/X86/avx-256-logic.ll b/test/CodeGen/X86/avx-256-logic.ll new file mode 100644 index 0000000..d9e5d08 --- /dev/null +++ b/test/CodeGen/X86/avx-256-logic.ll @@ -0,0 +1,161 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vandpd +define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %1 = bitcast <4 x double> %y to <4 x i64> + %and.i = and <4 x i64> %0, %1 + %2 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vandpd LCP{{.*}}(%rip) +define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %y to <4 x i64> + %and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> + %1 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %1 +} + +; CHECK: vandps +define <8 x float> @andps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %1 = bitcast <8 x float> %y to <8 x i32> + %and.i = and <8 x i32> %0, %1 + %2 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vandps LCP{{.*}}(%rip) +define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %y to <8 x i32> + %and.i = and <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938> + %1 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %1 +} + +; CHECK: vxorpd +define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %1 = bitcast <4 x double> %y to <4 x i64> + %xor.i = xor <4 x i64> %0, %1 + %2 = bitcast <4 x i64> %xor.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vxorpd LCP{{.*}}(%rip) +define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %y to <4 x i64> + %xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> + %1 = bitcast <4 x i64> %xor.i to <4 x double> + ret <4 x double> %1 +} + +; CHECK: vxorps +define <8 x float> @xorps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %1 = bitcast <8 x float> %y to <8 x i32> + %xor.i = xor <8 x i32> %0, %1 + %2 = bitcast <8 x i32> %xor.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vxorps LCP{{.*}}(%rip) +define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %y to <8 x i32> + %xor.i = xor <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938> + %1 = bitcast <8 x i32> %xor.i to <8 x float> + ret <8 x float> %1 +} + +; CHECK: vorpd +define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %1 = bitcast <4 x double> %y to <4 x i64> + %or.i = or <4 x i64> %0, %1 + %2 = bitcast <4 x i64> %or.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vorpd LCP{{.*}}(%rip) +define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %y to <4 x i64> + %or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> + %1 = bitcast <4 x i64> %or.i to <4 x double> + ret <4 x double> %1 +} + +; CHECK: vorps +define <8 x float> @orps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %1 = bitcast <8 x float> %y to <8 x i32> + %or.i = or <8 x i32> %0, %1 + %2 = bitcast <8 x i32> %or.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vorps LCP{{.*}}(%rip) +define <8 x float> @orps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %y to <8 x i32> + %or.i = or <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938> + %1 = bitcast <8 x i32> %or.i to <8 x float> + ret <8 x float> %1 +} + +; CHECK: vandnpd +define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1> + %1 = bitcast <4 x double> %y to <4 x i64> + %and.i = and <4 x i64> %1, %neg.i + %2 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vandnpd (% +define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <4 x double>* %x, align 32 + %0 = bitcast <4 x double> %y to <4 x i64> + %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1> + %1 = bitcast <4 x double> %tmp2 to <4 x i64> + %and.i = and <4 x i64> %1, %neg.i + %2 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vandnps +define <8 x float> @andnotps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> + %1 = bitcast <8 x float> %y to <8 x i32> + %and.i = and <8 x i32> %1, %neg.i + %2 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vandnps (% +define <8 x float> @andnotps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <8 x float>* %x, align 32 + %0 = bitcast <8 x float> %y to <8 x i32> + %neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> + %1 = bitcast <8 x float> %tmp2 to <8 x i32> + %and.i = and <8 x i32> %1, %neg.i + %2 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %2 +} diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll new file mode 100644 index 0000000..5196089 --- /dev/null +++ b/test/CodeGen/X86/avx-load-store.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vmovaps +; CHECK: vmovaps +; CHECK: vmovapd +; CHECK: vmovapd +; CHECK: vmovaps +; CHECK: vmovaps +define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind uwtable ssp { +entry: + %0 = bitcast double* %d to <4 x double>* + %tmp1.i = load <4 x double>* %0, align 32 + %1 = bitcast float* %f to <8 x float>* + %tmp1.i17 = load <8 x float>* %1, align 32 + %tmp1.i16 = load <4 x i64>* %i, align 32 + tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind + store <4 x double> %tmp1.i, <4 x double>* %0, align 32 + store <8 x float> %tmp1.i17, <8 x float>* %1, align 32 + store <4 x i64> %tmp1.i16, <4 x i64>* %i, align 32 + ret void +} + +declare void @dummy(<4 x double>, <8 x float>, <4 x i64>) + diff --git a/test/CodeGen/X86/change-compare-stride-0.ll b/test/CodeGen/X86/change-compare-stride-0.ll index d520a6f..3a383ee 100644 --- a/test/CodeGen/X86/change-compare-stride-0.ll +++ b/test/CodeGen/X86/change-compare-stride-0.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep {cmpl \$-478,} %t -; RUN: not grep inc %t -; RUN: not grep {leal 1(} %t -; RUN: not grep {leal -1(} %t -; RUN: grep dec %t | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind { +; CHECK: borf: +; CHECK-NOT: inc +; CHECK-NOT: leal 1( +; CHECK-NOT: leal -1( +; CHECK: decl +; CHECK-NEXT: cmpl $-478 +; CHECK: ret + bb4.thread: br label %bb2.outer diff --git a/test/CodeGen/X86/change-compare-stride-1.ll b/test/CodeGen/X86/change-compare-stride-1.ll index a9ddbdb..eee3b79 100644 --- a/test/CodeGen/X86/change-compare-stride-1.ll +++ b/test/CodeGen/X86/change-compare-stride-1.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: grep {cmpq \$-478,} %t -; RUN: not grep inc %t -; RUN: not grep {leal 1(} %t -; RUN: not grep {leal -1(} %t -; RUN: grep dec %t | count 1 +; RUN: llc < %s -march=x86-64 | FileCheck %s define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind { +; CHECK: borf: +; CHECK-NOT: inc +; CHECK-NOT: leal 1( +; CHECK-NOT: leal -1( +; CHECK: decq +; CHECK-NEXT: cmpq $-478 +; CHECK: ret + bb4.thread: br label %bb2.outer diff --git a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll index cb63809..a3933e2 100644 --- a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll +++ b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll @@ -1,6 +1,4 @@ -; RUN: llc %s -o - --x86-asm-syntax=att | grep {cmp. \$10} -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-apple-darwin9" +; RUN: llc -march=x86 < %s | FileCheck %s ; The comparison happens after the relevant use, so the stride can easily ; be changed. The comparison can be done in a narrower mode than the @@ -9,6 +7,11 @@ target triple = "x86_64-apple-darwin9" ; could be made simpler. define void @foo() nounwind { +; CHECK: foo: +; CHECK-NOT: ret +; CHECK: cmpl $10 +; CHECK: ret + entry: br label %loop diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 7c4e64c..b5b1ad4 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -215,3 +215,104 @@ bb2: } declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone + +; PR10277 +; This test has dead code elimination caused by remat during spilling. +; DCE causes a live interval to break into connected components. +; One of the components is spilled. + +%t2 = type { i8 } +%t9 = type { %t10 } +%t10 = type { %t11 } +%t11 = type { %t12 } +%t12 = type { %t13*, %t13*, %t13* } +%t13 = type { %t14*, %t15, %t15 } +%t14 = type opaque +%t15 = type { i8, i32, i32 } +%t16 = type { %t17, i8* } +%t17 = type { %t18 } +%t18 = type { %t19 } +%t19 = type { %t20*, %t20*, %t20* } +%t20 = type { i32, i32 } +%t21 = type { %t13* } + +define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { +bb: + %tmp = load %t9** undef, align 4, !tbaa !0 + %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0 + %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 + br label %bb4 + +bb4: ; preds = %bb37, %bb + %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ] + %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ] + br i1 undef, label %bb34, label %bb7 + +bb7: ; preds = %bb4 + %tmp8 = load i32* undef, align 4 + %tmp9 = and i96 %tmp6, 4294967040 + %tmp10 = zext i32 %tmp8 to i96 + %tmp11 = shl nuw nsw i96 %tmp10, 32 + %tmp12 = or i96 %tmp9, %tmp11 + %tmp13 = or i96 %tmp12, 1 + %tmp14 = load i32* undef, align 4 + %tmp15 = and i96 %tmp5, 4294967040 + %tmp16 = zext i32 %tmp14 to i96 + %tmp17 = shl nuw nsw i96 %tmp16, 32 + %tmp18 = or i96 %tmp15, %tmp17 + %tmp19 = or i96 %tmp18, 1 + %tmp20 = load i8* undef, align 1 + %tmp21 = and i8 %tmp20, 1 + %tmp22 = icmp ne i8 %tmp21, 0 + %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13 + %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19 + store i96 %tmp24, i96* undef, align 4 + %tmp25 = load %t13** %tmp3, align 4 + %tmp26 = icmp eq %t13* %tmp25, undef + br i1 %tmp26, label %bb28, label %bb27 + +bb27: ; preds = %bb7 + br label %bb29 + +bb28: ; preds = %bb7 + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + br label %bb29 + +bb29: ; preds = %bb28, %bb27 + store i96 %tmp23, i96* undef, align 4 + %tmp30 = load %t13** %tmp3, align 4 + br i1 false, label %bb33, label %bb31 + +bb31: ; preds = %bb29 + %tmp32 = getelementptr inbounds %t13* %tmp30, i32 1 + store %t13* %tmp32, %t13** %tmp3, align 4 + br label %bb37 + +bb33: ; preds = %bb29 + unreachable + +bb34: ; preds = %bb4 + br i1 undef, label %bb36, label %bb35 + +bb35: ; preds = %bb34 + store %t13* null, %t13** %tmp3, align 4 + br label %bb37 + +bb36: ; preds = %bb34 + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + br label %bb37 + +bb37: ; preds = %bb36, %bb35, %bb31 + %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ] + %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ] + %tmp40 = add i32 undef, 1 + br label %bb4 +} + +declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*) + +declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*) + +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind + +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/dag-rauw-cse.ll b/test/CodeGen/X86/dag-rauw-cse.ll index edcfeb7..eca8c86 100644 --- a/test/CodeGen/X86/dag-rauw-cse.ll +++ b/test/CodeGen/X86/dag-rauw-cse.ll @@ -1,7 +1,11 @@ -; RUN: llc < %s -march=x86 | grep {orl \$1} +; RUN: llc < %s -march=x86 | FileCheck %s ; PR3018 define i32 @test(i32 %A) nounwind { +; CHECK: test: +; CHECK-NOT: ret +; CHECK: orl $1 +; CHECK: ret %B = or i32 %A, 1 %C = or i32 %B, 1 %D = and i32 %C, 7057 diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index 08e3272..87c1be5 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -40,7 +40,7 @@ entry: %div = sdiv i16 %x, 33 ; <i32> [#uses=1] ret i16 %div ; CHECK: test4: -; CHECK: imull $1986, %eax, %eax +; CHECK: imull $1986, %eax, % } define i32 @test5(i32 %A) nounwind { diff --git a/test/CodeGen/X86/fma.ll b/test/CodeGen/X86/fma.ll new file mode 100644 index 0000000..5deedb9 --- /dev/null +++ b/test/CodeGen/X86/fma.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s + +; CHECK: test_f32 +; CHECK: _fmaf + +define float @test_f32(float %a, float %b, float %c) nounwind readnone ssp { +entry: + %call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone + ret float %call +} + +; CHECK: test_f64 +; CHECK: _fma + +define double @test_f64(double %a, double %b, double %c) nounwind readnone ssp { +entry: + %call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone + ret double %call +} + +; CHECK: test_f80 +; CHECK: _fmal + +define x86_fp80 @test_f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone ssp { +entry: + %call = tail call x86_fp80 @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone + ret x86_fp80 %call +} + +declare float @llvm.fma.f32(float, float, float) nounwind readnone +declare double @llvm.fma.f64(double, double, double) nounwind readnone +declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) nounwind readnone diff --git a/test/CodeGen/X86/fold-add.ll b/test/CodeGen/X86/fold-add.ll index 5e80ea5..63e7d36 100644 --- a/test/CodeGen/X86/fold-add.ll +++ b/test/CodeGen/X86/fold-add.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep {cmpb \$0, (%r.\*,%r.\*)} +; RUN: llc < %s -march=x86-64 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin9.6" @@ -7,6 +7,11 @@ target triple = "x86_64-apple-darwin9.6" @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)] ; <[1 x i8*]*> [#uses=0] define fastcc i32 @longest_match(i32 %cur_match) nounwind { +; CHECK: longest_match: +; CHECK-NOT: ret +; CHECK: cmpb $0, (%r{{.*}},%r{{.*}}) +; CHECK: ret + entry: %0 = load i32* @prev_length, align 4 ; <i32> [#uses=3] %1 = zext i32 %cur_match to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/fp-stack-2results.ll b/test/CodeGen/X86/fp-stack-2results.ll index e986e36..c8da9ea 100644 --- a/test/CodeGen/X86/fp-stack-2results.ll +++ b/test/CodeGen/X86/fp-stack-2results.ll @@ -5,7 +5,7 @@ ; This is basically this code on x86-64: ; _Complex long double test() { return 1.0; } -define {x86_fp80, x86_fp80} @test() { +define %0 @test() { %A = fpext double 1.0 to x86_fp80 %B = fpext double 0.0 to x86_fp80 %mrv = insertvalue %0 undef, x86_fp80 %A, 0 @@ -18,7 +18,7 @@ define {x86_fp80, x86_fp80} @test() { ; fld1 ; fld %st(0) ; ret -define {x86_fp80, x86_fp80} @test2() { +define %0 @test2() { %A = fpext double 1.0 to x86_fp80 %mrv = insertvalue %0 undef, x86_fp80 %A, 0 %mrv1 = insertvalue %0 %mrv, x86_fp80 %A, 1 @@ -27,39 +27,39 @@ define {x86_fp80, x86_fp80} @test2() { ; Uses both values. define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() - %b = extractvalue {x86_fp80,x86_fp80} %a, 0 + %a = call %0 @test() + %b = extractvalue %0 %a, 0 store x86_fp80 %b, x86_fp80* %P1 - %c = extractvalue {x86_fp80,x86_fp80} %a, 1 + %c = extractvalue %0 %a, 1 store x86_fp80 %c, x86_fp80* %P2 ret void } ; Uses both values, requires fxch define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() - %b = extractvalue {x86_fp80,x86_fp80} %a, 1 + %a = call %0 @test() + %b = extractvalue %0 %a, 1 store x86_fp80 %b, x86_fp80* %P1 - %c = extractvalue {x86_fp80,x86_fp80} %a, 0 + %c = extractvalue %0 %a, 0 store x86_fp80 %c, x86_fp80* %P2 ret void } ; Uses ST(0), ST(1) is dead but must be popped. define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() - %b = extractvalue {x86_fp80,x86_fp80} %a, 0 + %a = call %0 @test() + %b = extractvalue %0 %a, 0 store x86_fp80 %b, x86_fp80* %P1 ret void } ; Uses ST(1), ST(0) is dead and must be popped. define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() + %a = call %0 @test() - %c = extractvalue {x86_fp80,x86_fp80} %a, 1 + %c = extractvalue %0 %a, 1 store x86_fp80 %c, x86_fp80* %P2 ret void } diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll index 16e13f8..488444c 100644 --- a/test/CodeGen/X86/h-registers-2.ll +++ b/test/CodeGen/X86/h-registers-2.ll @@ -1,14 +1,19 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep {movzbl %\[abcd\]h,} %t | count 1 -; RUN: grep {shll \$3,} %t | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s ; Use an h register, but don't omit the explicit shift for ; non-address use(s). define i32 @foo(i8* %x, i32 %y) nounwind { +; CHECK: foo: +; CHECK-NOT: ret +; CHECK: movzbl %{{[abcd]h}}, +; CHECK-NOT: ret +; CHECK: shll $3, +; CHECK: ret + %t0 = lshr i32 %y, 8 ; <i32> [#uses=1] %t1 = and i32 %t0, 255 ; <i32> [#uses=2] - %t2 = shl i32 %t1, 3 + %t2 = shl i32 %t1, 3 %t3 = getelementptr i8* %x, i32 %t2 ; <i8*> [#uses=1] store i8 77, i8* %t3, align 4 ret i32 %t2 diff --git a/test/CodeGen/X86/inline-asm-error.ll b/test/CodeGen/X86/inline-asm-error.ll index 29c5ae5..134d6e9 100644 --- a/test/CodeGen/X86/inline-asm-error.ll +++ b/test/CodeGen/X86/inline-asm-error.ll @@ -5,10 +5,8 @@ ; RUN: FileCheck %s < %t2 ; RUN: FileCheck %s < %t3 -; The register allocator must fail on this function, and it should print the -; inline asm in the diagnostic. -; CHECK: LLVM ERROR: Ran out of registers during register allocation! -; CHECK: INLINEASM <es:hello world> +; The register allocator must fail on this function. +; CHECK: error: ran out of registers during register allocation define void @f(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, i32 %x7, i32 %x8, i32 %x9) nounwind ssp { entry: diff --git a/test/CodeGen/X86/inline-asm-q-regs.ll b/test/CodeGen/X86/inline-asm-q-regs.ll index 321fd30..1c8e2f9 100644 --- a/test/CodeGen/X86/inline-asm-q-regs.ll +++ b/test/CodeGen/X86/inline-asm-q-regs.ll @@ -3,8 +3,20 @@ %0 = type { i64, i64, i64, i64, i64 } ; type %0 -define void @t() nounwind { +define void @test1() nounwind { entry: %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] ret void } + +; PR9602 +define void @test2(float %tmp) nounwind { + call void asm sideeffect "$0", "q"(float %tmp) nounwind + call void asm sideeffect "$0", "Q"(float %tmp) nounwind + ret void +} + +define void @test3(double %tmp) nounwind { + call void asm sideeffect "$0", "q"(double %tmp) nounwind + ret void +} diff --git a/test/CodeGen/X86/inline-asm.ll b/test/CodeGen/X86/inline-asm.ll index c66d7a8..eef6c2f 100644 --- a/test/CodeGen/X86/inline-asm.ll +++ b/test/CodeGen/X86/inline-asm.ll @@ -23,3 +23,23 @@ define void @test4() nounwind { tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind ret void } + +; rdar://9738585 +define i32 @test5() nounwind { +entry: + %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind + ret i32 0 +} + +; rdar://9777108 PR10352 +define void @test6(i1 zeroext %desired) nounwind { +entry: + tail call void asm sideeffect "foo $0", "q,~{dirflag},~{fpsr},~{flags}"(i1 %desired) nounwind + ret void +} + +define void @test7(i1 zeroext %desired, i32* %p) nounwind { +entry: + %0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind + ret void +} diff --git a/test/CodeGen/X86/isel-sink.ll b/test/CodeGen/X86/isel-sink.ll index 0f94b23..d275533 100644 --- a/test/CodeGen/X86/isel-sink.ll +++ b/test/CodeGen/X86/isel-sink.ll @@ -1,8 +1,14 @@ -; RUN: llc < %s -march=x86 | not grep lea -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 | \ -; RUN: grep {movl \$4, (.*,.*,4)} +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i32* %X, i32 %B) { +; CHECK: test: +; CHECK-NOT: ret +; CHECK-NOT: lea +; CHECK: mov{{.}} $4, ({{.*}},{{.*}},4) +; CHECK: ret +; CHECK: mov{{.}} ({{.*}},{{.*}},4), +; CHECK: ret + ; This gep should be sunk out of this block into the load/store users. %P = getelementptr i32* %X, i32 %B %G = icmp ult i32 %B, 1234 @@ -14,5 +20,3 @@ F: %V = load i32* %P ret i32 %V } - - diff --git a/test/CodeGen/X86/loop-strength-reduce2.ll b/test/CodeGen/X86/loop-strength-reduce2.ll index 9b53adb..689ee1c 100644 --- a/test/CodeGen/X86/loop-strength-reduce2.ll +++ b/test/CodeGen/X86/loop-strength-reduce2.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | grep {\$pb} | grep mov +; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | FileCheck %s ; ; Make sure the PIC label flags2-"L1$pb" is not moved up to the preheader. +; CHECK: mov{{.}} {{.*}}$pb @flags2 = internal global [8193 x i8] zeroinitializer, align 32 ; <[8193 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/lsr-nonaffine.ll b/test/CodeGen/X86/lsr-nonaffine.ll index 4771646..d0d2bbd 100644 --- a/test/CodeGen/X86/lsr-nonaffine.ll +++ b/test/CodeGen/X86/lsr-nonaffine.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -march=x86-64 -o - < %s | FileCheck %s +; RUN: llc -asm-verbose=false -march=x86-64 -mtriple=x86_64-apple-darwin -o - < %s | FileCheck %s ; LSR should leave non-affine expressions alone because it currently ; doesn't know how to do anything with them, and when it tries, it diff --git a/test/CodeGen/X86/lsr-redundant-addressing.ll b/test/CodeGen/X86/lsr-redundant-addressing.ll index aaa1426..cb0ac8b 100644 --- a/test/CodeGen/X86/lsr-redundant-addressing.ll +++ b/test/CodeGen/X86/lsr-redundant-addressing.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86-64 < %s | fgrep {addq $-16,} | count 1 +; RUN: llc -march=x86-64 < %s | FileCheck %s ; rdar://9081094 ; LSR shouldn't create lots of redundant address computations. @@ -10,6 +10,12 @@ @isa = external hidden unnamed_addr constant [13 x %1], align 32 define void @main_bb.i() nounwind { +; CHECK: main_bb.i: +; CHECK-NOT: ret +; CHECK: addq $-16, +; CHECK-NOT: ret +; CHECK: ret + bb: br label %bb38 diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll index 4770519..1f87089 100644 --- a/test/CodeGen/X86/lsr-reuse-trunc.ll +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -5,8 +5,9 @@ ; stick with indexing here. ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] -; CHECK: movaps -; CHECK: [[X3]], (%{{rdi|rcx}},%rax,4) +; CHECK: cvtdq2ps +; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] +; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) ; CHECK: addq $4, %rax ; CHECK: cmpl %eax, (%{{rdx|r8}}) ; CHECK-NEXT: jg diff --git a/test/CodeGen/X86/membarrier.ll b/test/CodeGen/X86/membarrier.ll new file mode 100644 index 0000000..42f8ef5 --- /dev/null +++ b/test/CodeGen/X86/membarrier.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86-64 -mattr=-sse -O0 +; PR9675 + +define i32 @t() { +entry: + %i = alloca i32, align 4 + store i32 1, i32* %i, align 4 + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1) + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + ret i32 0 +} + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll index 72342cb..f43b0bf 100644 --- a/test/CodeGen/X86/memcpy.ll +++ b/test/CodeGen/X86/memcpy.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=DARWIN declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll index a34a978..528c4bc 100644 --- a/test/CodeGen/X86/peep-test-3.ll +++ b/test/CodeGen/X86/peep-test-3.ll @@ -9,7 +9,7 @@ entry: %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1] %1 = and i32 %0, 3 ; <i32> [#uses=1] %2 = xor i32 %IA, 1 ; <i32> [#uses=1] -; CHECK: orl %ecx, %edx +; CHECK: orl %e ; CHECK-NEXT: je %3 = or i32 %2, %1 ; <i32> [#uses=1] %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll index b6761e3..8c16dc6 100644 --- a/test/CodeGen/X86/pic_jumptable.ll +++ b/test/CodeGen/X86/pic_jumptable.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | grep -F .text._Z3fooILi1EEvi,"axG",@progbits,_Z3fooILi1EEvi,comdat -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | FileCheck %s +; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false \ +; RUN: | FileCheck %s --check-prefix=CHECK-LINUX +; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false \ +; RUN: | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI' ; rdar://6971437 ; rdar://7738756 declare void @_Z3bari(i32) +; CHECK-LINUX: .text._Z3fooILi1EEvi,"axG",@progbits,_Z3fooILi1EEvi,comdat define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind { entry: ; CHECK: L0$pb diff --git a/test/CodeGen/X86/pr2182.ll b/test/CodeGen/X86/pr2182.ll index f97663c..2a8bb35 100644 --- a/test/CodeGen/X86/pr2182.ll +++ b/test/CodeGen/X86/pr2182.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {addl \$3, (%eax)} | count 4 +; RUN: llc < %s | FileCheck %s ; PR2182 target datalayout = @@ -7,18 +7,25 @@ target triple = "i386-apple-darwin8" @x = weak global i32 0 ; <i32*> [#uses=8] define void @loop_2() nounwind { -entry: - %tmp = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1 = add i32 %tmp, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1, i32* @x, align 4 - %tmp.1 = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1.1 = add i32 %tmp.1, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1.1, i32* @x, align 4 - %tmp.2 = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1.2 = add i32 %tmp.2, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1.2, i32* @x, align 4 - %tmp.3 = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1.3 = add i32 %tmp.3, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1.3, i32* @x, align 4 - ret void +; CHECK: loop_2: +; CHECK-NOT: ret +; CHECK: addl $3, (%{{.*}}) +; CHECK-NEXT: addl $3, (%{{.*}}) +; CHECK-NEXT: addl $3, (%{{.*}}) +; CHECK-NEXT: addl $3, (%{{.*}}) +; CHECK-NEXT: ret + + %tmp = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1 = add i32 %tmp, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1, i32* @x, align 4 + %tmp.1 = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1.1 = add i32 %tmp.1, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1.1, i32* @x, align 4 + %tmp.2 = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1.2 = add i32 %tmp.2, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1.2, i32* @x, align 4 + %tmp.3 = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1.3 = add i32 %tmp.3, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1.3, i32* @x, align 4 + ret void } diff --git a/test/CodeGen/X86/pr2623.ll b/test/CodeGen/X86/pr2623.ll deleted file mode 100644 index 5d0eb5d..0000000 --- a/test/CodeGen/X86/pr2623.ll +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: llc < %s -; PR2623 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-unknown-freebsd7.0" - %.objc_id = type { %.objc_id }* - %.objc_selector = type { i8*, i8* }* -@.objc_sel_ptr = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr13 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr14 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr15 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr16 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr17 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr18 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr19 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr20 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr21 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - -@.objc_untyped_selector_alias = alias internal %.objc_selector* @.objc_sel_ptr15 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias1 = alias internal %.objc_selector* @.objc_sel_ptr ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias2 = alias internal %.objc_selector* @.objc_sel_ptr17 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias3 = alias internal %.objc_selector* @.objc_sel_ptr16 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias4 = alias internal %.objc_selector* @.objc_sel_ptr13 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias7 = alias internal %.objc_selector* @.objc_sel_ptr14 ; <%.objc_selector*> [#uses=0] -@getRange = alias internal %.objc_selector* @.objc_sel_ptr18 ; <%.objc_selector*> [#uses=0] -@"valueWithRange:" = alias internal %.objc_selector* @.objc_sel_ptr21 ; <%.objc_selector*> [#uses=0] -@rangeValue = alias internal %.objc_selector* @.objc_sel_ptr20 ; <%.objc_selector*> [#uses=0] -@"printRange:" = alias internal %.objc_selector* @.objc_sel_ptr19 ; <%.objc_selector*> [#uses=0] - -define void @"._objc_method_SmalltalkTool()-run"(i8* %self, %.objc_selector %_cmd) { -entry: - br i1 false, label %small_int_messagerangeValue, label %real_object_messagerangeValue - -small_int_messagerangeValue: ; preds = %entry - br label %Continue - -real_object_messagerangeValue: ; preds = %entry - br label %Continue - -Continue: ; preds = %real_object_messagerangeValue, %small_int_messagerangeValue - %rangeValue = phi { i32, i32 } [ undef, %small_int_messagerangeValue ], [ undef, %real_object_messagerangeValue ] ; <{ i32, i32 }> [#uses=1] - call void (%.objc_id, %.objc_selector, ...)* null( %.objc_id null, %.objc_selector null, { i32, i32 } %rangeValue ) - ret void -} diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll index 38c9f32..63676d9 100644 --- a/test/CodeGen/X86/pr3216.ll +++ b/test/CodeGen/X86/pr3216.ll @@ -1,14 +1,18 @@ -; RUN: llc < %s -march=x86 | grep {sar. \$5} +; RUN: llc < %s -march=x86 | FileCheck %s @foo = global i8 127 define i32 @main() nounwind { -entry: - %tmp = load i8* @foo - %bf.lo = lshr i8 %tmp, 5 - %bf.lo.cleared = and i8 %bf.lo, 7 - %0 = shl i8 %bf.lo.cleared, 5 - %bf.val.sext = ashr i8 %0, 5 - %conv = sext i8 %bf.val.sext to i32 - ret i32 %conv +; CHECK: main: +; CHECK-NOT: ret +; CHECK: sar{{.}} $5 +; CHECK: ret + + %tmp = load i8* @foo + %bf.lo = lshr i8 %tmp, 5 + %bf.lo.cleared = and i8 %bf.lo, 7 + %1 = shl i8 %bf.lo.cleared, 5 + %bf.val.sext = ashr i8 %1, 5 + %conv = sext i8 %bf.val.sext to i32 + ret i32 %conv } diff --git a/test/CodeGen/X86/pr3317.ll b/test/CodeGen/X86/pr3317.ll index 9d6626b..d83daf0 100644 --- a/test/CodeGen/X86/pr3317.ll +++ b/test/CodeGen/X86/pr3317.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=x86 ; PR3317 +%VT = type [0 x i32 (...)*] %ArraySInt16 = type { %JavaObject, i8*, [0 x i16] } %ArraySInt8 = type { %JavaObject, i8*, [0 x i8] } %Attribut = type { %ArraySInt16*, i32, i32 } @@ -14,7 +15,6 @@ %JavaObject = type { %VT*, %JavaCommonClass*, i8* } %TaskClassMirror = type { i32, i8* } %UTF8 = type { %JavaObject, i8*, [0 x i16] } - %VT = type [0 x i32 (...)*] declare void @jnjvmNullPointerException() diff --git a/test/CodeGen/X86/reghinting.ll b/test/CodeGen/X86/reghinting.ll new file mode 100644 index 0000000..87f65ed --- /dev/null +++ b/test/CodeGen/X86/reghinting.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s +; PR10221 + +;; The registers %x and %y must both spill across the finit call. +;; Check that they are spilled early enough that not copies are needed for the +;; fadd and fpext. + +; CHECK: pr10221 +; CHECK-NOT: movaps +; CHECK: movss +; CHECK-NEXT: movss +; CHECK-NEXT: addss +; CHECK-NEXT: cvtss2sd +; CHECK-NEXT: finit + +define i32 @pr10221(float %x, float %y, i8** nocapture %_retval) nounwind uwtable ssp { +entry: + %add = fadd float %x, %y + %conv = fpext float %add to double + %call = tail call i32 @finit(double %conv) nounwind + %tobool = icmp eq i32 %call, 0 + br i1 %tobool, label %return, label %if.end + +if.end: ; preds = %entry + tail call void @foo(float %x, float %y) nounwind + br label %return + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ 0, %if.end ], [ 5, %entry ] + ret i32 %retval.0 +} + +declare i32 @finit(double) + +declare void @foo(float, float) diff --git a/test/CodeGen/X86/sdiv-exact.ll b/test/CodeGen/X86/sdiv-exact.ll new file mode 100644 index 0000000..48bb883 --- /dev/null +++ b/test/CodeGen/X86/sdiv-exact.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=x86 < %s | FileCheck %s + +define i32 @test1(i32 %x) { + %div = sdiv exact i32 %x, 25 + ret i32 %div +; CHECK: test1: +; CHECK: imull $-1030792151, 4(%esp) +; CHECK-NEXT: ret +} + +define i32 @test2(i32 %x) { + %div = sdiv exact i32 %x, 24 + ret i32 %div +; CHECK: test2: +; CHECK: sarl $3 +; CHECK-NEXT: imull $-1431655765 +; CHECK-NEXT: ret +} diff --git a/test/CodeGen/X86/shift-codegen.ll b/test/CodeGen/X86/shift-codegen.ll index 4cba183..7d961e8 100644 --- a/test/CodeGen/X86/shift-codegen.ll +++ b/test/CodeGen/X86/shift-codegen.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -relocation-model=static -march=x86 | \ -; RUN: grep {shll \$3} | count 2 +; RUN: llc < %s -relocation-model=static -march=x86 | FileCheck %s ; This should produce two shll instructions, not any lea's. @@ -9,19 +8,31 @@ target triple = "i686-apple-darwin8" define void @fn1() { -entry: - %tmp = load i32* @Y ; <i32> [#uses=1] - %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1] - %tmp2 = load i32* @X ; <i32> [#uses=1] - %tmp3 = or i32 %tmp1, %tmp2 ; <i32> [#uses=1] - store i32 %tmp3, i32* @X - ret void +; CHECK: fn1: +; CHECK-NOT: ret +; CHECK-NOT: lea +; CHECK: shll $3 +; CHECK-NOT: lea +; CHECK: ret + + %tmp = load i32* @Y ; <i32> [#uses=1] + %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1] + %tmp2 = load i32* @X ; <i32> [#uses=1] + %tmp3 = or i32 %tmp1, %tmp2 ; <i32> [#uses=1] + store i32 %tmp3, i32* @X + ret void } define i32 @fn2(i32 %X, i32 %Y) { -entry: - %tmp2 = shl i32 %Y, 3 ; <i32> [#uses=1] - %tmp4 = or i32 %tmp2, %X ; <i32> [#uses=1] - ret i32 %tmp4 +; CHECK: fn2: +; CHECK-NOT: ret +; CHECK-NOT: lea +; CHECK: shll $3 +; CHECK-NOT: lea +; CHECK: ret + + %tmp2 = shl i32 %Y, 3 ; <i32> [#uses=1] + %tmp4 = or i32 %tmp2, %X ; <i32> [#uses=1] + ret i32 %tmp4 } diff --git a/test/CodeGen/X86/sse1.ll b/test/CodeGen/X86/sse1.ll index 73f88ae..9b2e05b 100644 --- a/test/CodeGen/X86/sse1.ll +++ b/test/CodeGen/X86/sse1.ll @@ -1,6 +1,6 @@ ; Tests for SSE1 and below, without SSE2+. ; RUN: llc < %s -march=x86 -mcpu=pentium3 -O3 | FileCheck %s -; RUN: llc < %s -march=x86-64 -mcpu=pentium3 -O3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s define <8 x i16> @test1(<8 x i32> %a) nounwind { ; CHECK: test1 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 8c2e58d..8b3a317 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -1,6 +1,6 @@ -; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+. +; These are tests for SSE3 codegen. -; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \ +; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \ ; RUN: | FileCheck %s --check-prefix=X64 ; Test for v8xi16 lowering where we extract the first element of the vector and @@ -169,10 +169,10 @@ define internal void @t10() nounwind { ; X64: t10: ; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax ; X64: unpcklpd [[X1:%xmm[0-9]+]] -; X64: pshuflw $8, [[X1]], [[X1]] -; X64: pinsrw $2, %eax, [[X1]] +; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]] +; X64: pinsrw $2, %eax, [[X2]] ; X64: pextrw $6, [[X0]], %eax -; X64: pinsrw $3, %eax, [[X1]] +; X64: pinsrw $3, %eax, [[X2]] } diff --git a/test/CodeGen/X86/switch-bt.ll b/test/CodeGen/X86/switch-bt.ll index 9f491d4..8e39342 100644 --- a/test/CodeGen/X86/switch-bt.ll +++ b/test/CodeGen/X86/switch-bt.ll @@ -79,3 +79,23 @@ if.end: ; preds = %entry } declare void @bar() + +define void @test3(i32 %x) nounwind { +; CHECK: test3: +; CHECK: cmpl $5 +; CHECK: ja +; CHECK: cmpl $4 +; CHECK: jne + switch i32 %x, label %if.end [ + i32 0, label %if.then + i32 1, label %if.then + i32 2, label %if.then + i32 3, label %if.then + i32 5, label %if.then + ] +if.then: + tail call void @bar() nounwind + ret void +if.end: + ret void +} diff --git a/test/CodeGen/X86/testl-commute.ll b/test/CodeGen/X86/testl-commute.ll index 3d5f672..0e6f636 100644 --- a/test/CodeGen/X86/testl-commute.ll +++ b/test/CodeGen/X86/testl-commute.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {testl.*\(%r.i\), %} | count 3 +; RUN: llc < %s | FileCheck %s ; rdar://5671654 ; The loads should fold into the testl instructions, no matter how ; the inputs are commuted. @@ -7,6 +7,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin7" define i32 @test(i32* %P, i32* %G) nounwind { +; CHECK: test: +; CHECK-NOT: ret +; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: ret + entry: %0 = load i32* %P, align 4 ; <i32> [#uses=3] %1 = load i32* %G, align 4 ; <i32> [#uses=1] @@ -23,6 +28,11 @@ bb1: ; preds = %entry } define i32 @test2(i32* %P, i32* %G) nounwind { +; CHECK: test2: +; CHECK-NOT: ret +; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: ret + entry: %0 = load i32* %P, align 4 ; <i32> [#uses=3] %1 = load i32* %G, align 4 ; <i32> [#uses=1] @@ -37,7 +47,13 @@ bb: ; preds = %entry bb1: ; preds = %entry ret i32 %0 } + define i32 @test3(i32* %P, i32* %G) nounwind { +; CHECK: test3: +; CHECK-NOT: ret +; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: ret + entry: %0 = load i32* %P, align 4 ; <i32> [#uses=3] %1 = load i32* %G, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/tlv-1.ll b/test/CodeGen/X86/tlv-1.ll index 42940f1..5773260 100644 --- a/test/CodeGen/X86/tlv-1.ll +++ b/test/CodeGen/X86/tlv-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple x86_64-apple-darwin -mcpu=core2 | FileCheck %s %struct.A = type { [48 x i8], i32, i32, i32 } diff --git a/test/CodeGen/X86/twoaddr-remat.ll b/test/CodeGen/X86/twoaddr-remat.ll deleted file mode 100644 index 4940c78..0000000 --- a/test/CodeGen/X86/twoaddr-remat.ll +++ /dev/null @@ -1,67 +0,0 @@ -; RUN: llc < %s -march=x86 | grep 59796 | count 3 - - %Args = type %Value* - %Exec = type opaque* - %Identifier = type opaque* - %JSFunction = type %Value (%Exec, %Scope, %Value, %Args) - %PropertyNameArray = type opaque* - %Scope = type opaque* - %Value = type opaque* - -declare i1 @X1(%Exec) readonly - -declare %Value @X2(%Exec) - -declare i32 @X3(%Exec, %Value) - -declare %Value @X4(i32) readnone - -define internal %Value @fast3bitlookup(%Exec %exec, %Scope %scope, %Value %this, %Args %args) nounwind { -prologue: - %eh_check = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1] - br i1 %eh_check, label %exception, label %no_exception - -exception: ; preds = %no_exception, %prologue - %rethrow_result = tail call %Value @X2( %Exec %exec ) ; <%Value> [#uses=1] - ret %Value %rethrow_result - -no_exception: ; preds = %prologue - %args_intptr = bitcast %Args %args to i32* ; <i32*> [#uses=1] - %argc_val = load i32* %args_intptr ; <i32> [#uses=1] - %cmpParamArgc = icmp sgt i32 %argc_val, 0 ; <i1> [#uses=1] - %arg_ptr = getelementptr %Args %args, i32 1 ; <%Args> [#uses=1] - %arg_val = load %Args %arg_ptr ; <%Value> [#uses=1] - %ext_arg_val = select i1 %cmpParamArgc, %Value %arg_val, %Value inttoptr (i32 5 to %Value) ; <%Value> [#uses=1] - %toInt325 = tail call i32 @X3( %Exec %exec, %Value %ext_arg_val ) ; <i32> [#uses=3] - %eh_check6 = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1] - br i1 %eh_check6, label %exception, label %no_exception7 - -no_exception7: ; preds = %no_exception - %shl_tmp_result = shl i32 %toInt325, 1 ; <i32> [#uses=1] - %rhs_masked13 = and i32 %shl_tmp_result, 14 ; <i32> [#uses=1] - %ashr_tmp_result = lshr i32 59796, %rhs_masked13 ; <i32> [#uses=1] - %and_tmp_result15 = and i32 %ashr_tmp_result, 3 ; <i32> [#uses=1] - %ashr_tmp_result3283 = lshr i32 %toInt325, 2 ; <i32> [#uses=1] - %rhs_masked38 = and i32 %ashr_tmp_result3283, 14 ; <i32> [#uses=1] - %ashr_tmp_result39 = lshr i32 59796, %rhs_masked38 ; <i32> [#uses=1] - %and_tmp_result41 = and i32 %ashr_tmp_result39, 3 ; <i32> [#uses=1] - %addconv = add i32 %and_tmp_result15, %and_tmp_result41 ; <i32> [#uses=1] - %ashr_tmp_result6181 = lshr i32 %toInt325, 5 ; <i32> [#uses=1] - %rhs_masked67 = and i32 %ashr_tmp_result6181, 6 ; <i32> [#uses=1] - %ashr_tmp_result68 = lshr i32 59796, %rhs_masked67 ; <i32> [#uses=1] - %and_tmp_result70 = and i32 %ashr_tmp_result68, 3 ; <i32> [#uses=1] - %addconv82 = add i32 %addconv, %and_tmp_result70 ; <i32> [#uses=3] - %rangetmp = add i32 %addconv82, 536870912 ; <i32> [#uses=1] - %rangecmp = icmp ult i32 %rangetmp, 1073741824 ; <i1> [#uses=1] - br i1 %rangecmp, label %NumberLiteralIntFast, label %NumberLiteralIntSlow - -NumberLiteralIntFast: ; preds = %no_exception7 - %imm_shift = shl i32 %addconv82, 2 ; <i32> [#uses=1] - %imm_or = or i32 %imm_shift, 3 ; <i32> [#uses=1] - %imm_val = inttoptr i32 %imm_or to %Value ; <%Value> [#uses=1] - ret %Value %imm_val - -NumberLiteralIntSlow: ; preds = %no_exception7 - %toVal = call %Value @X4( i32 %addconv82 ) ; <%Value> [#uses=1] - ret %Value %toVal -} diff --git a/test/CodeGen/X86/vec_insert-2.ll b/test/CodeGen/X86/vec_insert-2.ll index b08044b..dee91fd 100644 --- a/test/CodeGen/X86/vec_insert-2.ll +++ b/test/CodeGen/X86/vec_insert-2.ll @@ -1,25 +1,42 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep {\$36,} | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep shufps | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep pinsrw | count 1 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movhpd | count 1 -; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep unpcklpd | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X32 %s +; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind { - %tmp1 = insertelement <4 x float> %tmp, float %s, i32 3 - ret <4 x float> %tmp1 +; X32: t1: +; X32: shufps $36 +; X32: ret + + %tmp1 = insertelement <4 x float> %tmp, float %s, i32 3 + ret <4 x float> %tmp1 } define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind { - %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3 - ret <4 x i32> %tmp1 +; X32: t2: +; X32: shufps $36 +; X32: ret + + %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3 + ret <4 x i32> %tmp1 } define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind { - %tmp1 = insertelement <2 x double> %tmp, double %s, i32 1 - ret <2 x double> %tmp1 +; X32: t3: +; X32: movhpd +; X32: ret + +; X64: t3: +; X64: unpcklpd +; X64: ret + + %tmp1 = insertelement <2 x double> %tmp, double %s, i32 1 + ret <2 x double> %tmp1 } define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind { - %tmp1 = insertelement <8 x i16> %tmp, i16 %s, i32 5 - ret <8 x i16> %tmp1 +; X32: t4: +; X32: pinsrw +; X32: ret + + %tmp1 = insertelement <8 x i16> %tmp, i16 %s, i32 5 + ret <8 x i16> %tmp1 } diff --git a/test/CodeGen/X86/vec_set-A.ll b/test/CodeGen/X86/vec_set-A.ll index f05eecf..92dda4c 100644 --- a/test/CodeGen/X86/vec_set-A.ll +++ b/test/CodeGen/X86/vec_set-A.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movl.*\$1, %} +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; CHECK: movl $1, %{{.*}} define <2 x i64> @test1() nounwind { entry: ret <2 x i64> < i64 1, i64 0 > diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll index 3fff849..46b0e18 100644 --- a/test/CodeGen/X86/vector.ll +++ b/test/CodeGen/X86/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llc < %s -march=x86 -mcpu=i386 > %t -; RUN: llc < %s -march=x86 -mcpu=yonah > %t +; RUN: llc < %s -march=x86 -mcpu=yonah >> %t %d8 = type <8 x double> %f1 = type <1 x float> |