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-rw-r--r--test/MC/ARM/arm_fixups.s2
-rw-r--r--test/MC/ARM/basic-arm-instructions.s7
-rw-r--r--test/MC/ARM/basic-thumb-instructions.s22
-rw-r--r--test/MC/ARM/basic-thumb2-instructions.s34
-rw-r--r--test/MC/ARM/elf-reloc-condcall.s23
-rw-r--r--test/MC/ARM/lit.local.cfg9
-rw-r--r--test/MC/ARM/neon-add-encoding.s81
-rw-r--r--test/MC/ARM/neon-shift-encoding.s222
-rw-r--r--test/MC/ARM/neon-shuffle-encoding.s4
-rw-r--r--test/MC/ARM/neon-sub-encoding.s26
-rw-r--r--test/MC/ARM/neon-vst-encoding.s8
-rw-r--r--test/MC/ARM/neon-vswp.s7
-rw-r--r--test/MC/ARM/vfp4.s50
13 files changed, 416 insertions, 79 deletions
diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s
index 2f34748..74dfb99 100644
--- a/test/MC/ARM/arm_fixups.s
+++ b/test/MC/ARM/arm_fixups.s
@@ -3,7 +3,7 @@
bl _printf
@ CHECK: bl _printf @ encoding: [A,A,A,0xeb]
-@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_bl
+@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbl
mov r9, :lower16:(_foo)
movw r9, :lower16:(_foo)
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 4ae1ac7..4788ac7 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -382,13 +382,16 @@ Lforward:
@------------------------------------------------------------------------------
bl _bar
+ bleq _bar
blx _bar
blls #28634268
blx #32424576
blx #16212288
@ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
-@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_bl
+@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbl
+@ CHECK: bleq _bar @ encoding: [A,A,A,0x0b]
+@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_condbl
@ CHECK: blx _bar @ encoding: [A,A,A,0xfa]
@ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx
@ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b]
@@ -494,6 +497,7 @@ Lforward:
cmp r7, r8, ror r2
cmp r1, r6, rrx
cmp r0, #-2
+ cmp lr, #0
@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
@@ -508,6 +512,7 @@ Lforward:
@ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1]
@ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1]
@ CHECK: cmn r0, #2 @ encoding: [0x02,0x00,0x70,0xe3]
+@ CHECK: cmp lr, #0 @ encoding: [0x00,0x00,0x5e,0xe3]
@------------------------------------------------------------------------------
diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index 6e830cd..bc2605c 100644
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -59,12 +59,16 @@ _func:
add sp, sp, #4
add r2, sp, #8
add r2, sp, #1020
+ add sp, sp, #-8
+ add sp, #-8
@ CHECK: add sp, #4 @ encoding: [0x01,0xb0]
@ CHECK: add sp, #508 @ encoding: [0x7f,0xb0]
@ CHECK: add sp, #4 @ encoding: [0x01,0xb0]
@ CHECK: add r2, sp, #8 @ encoding: [0x02,0xaa]
@ CHECK: add r2, sp, #1020 @ encoding: [0xff,0xaa]
+@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
+@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
@------------------------------------------------------------------------------
@@ -93,10 +97,16 @@ _func:
asrs r2, r3, #32
asrs r2, r3, #5
asrs r2, r3, #1
+ asrs r5, #21
+ asrs r5, r5, #21
+ asrs r3, r5, #21
@ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
@ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
@ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
+@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
+@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
+@ CHECK: asrs r3, r5, #21 @ encoding: [0x6b,0x15]
@------------------------------------------------------------------------------
@@ -315,9 +325,15 @@ _func:
@------------------------------------------------------------------------------
lsls r4, r5, #0
lsls r4, r5, #4
+ lsls r3, #12
+ lsls r3, r3, #12
+ lsls r1, r3, #12
@ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00]
@ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01]
+@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
+@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
+@ CHECK: lsls r1, r3, #12 @ encoding: [0x19,0x03]
@------------------------------------------------------------------------------
@@ -333,9 +349,15 @@ _func:
@------------------------------------------------------------------------------
lsrs r1, r3, #1
lsrs r1, r3, #32
+ lsrs r4, #20
+ lsrs r4, r4, #20
+ lsrs r2, r4, #20
@ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
@ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
+@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
+@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
+@ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d]
@------------------------------------------------------------------------------
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index ce97ca6..d2e208b 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -75,6 +75,8 @@ _func:
adds r1, r2, #0x1f0
add r2, #1
add r0, r0, #32
+ adds r2, r2, #56
+ adds r2, #56
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
@@ -89,6 +91,8 @@ _func:
@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
@ CHECK: add.w r2, r2, #1 @ encoding: [0x02,0xf1,0x01,0x02]
@ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00]
+@ CHECK: adds r2, #56 @ encoding: [0x38,0x32]
+@ CHECK: adds r2, #56 @ encoding: [0x38,0x32]
@------------------------------------------------------------------------------
@@ -368,7 +372,8 @@ _func:
cmp sp, r6, lsr #1
cmp r2, r5, asr #24
cmp r1, r4, ror #15
- cmp r0, #-2
+ cmp r2, #-2
+ cmp r9, #1
@ CHECK: cmp.w r5, #65280 @ encoding: [0xb5,0xf5,0x7f,0x4f]
@ CHECK: cmp.w r4, r12 @ encoding: [0xb4,0xeb,0x0c,0x0f]
@@ -377,7 +382,9 @@ _func:
@ CHECK: cmp.w sp, r6, lsr #1 @ encoding: [0xbd,0xeb,0x56,0x0f]
@ CHECK: cmp.w r2, r5, asr #24 @ encoding: [0xb2,0xeb,0x25,0x6f]
@ CHECK: cmp.w r1, r4, ror #15 @ encoding: [0xb1,0xeb,0xf4,0x3f]
-@ CHECK: cmn.w r0, #2 @ encoding: [0x10,0xf1,0x02,0x0f]
+@ CHECK: cmn.w r2, #2 @ encoding: [0x12,0xf1,0x02,0x0f]
+@ CHECK: cmp.w r9, #1 @ encoding: [0xb9,0xf1,0x01,0x0f]
+
@------------------------------------------------------------------------------
@ DBG
@@ -1130,6 +1137,8 @@ _func:
moveq r1, #12
movne.w r1, #12
mov.w r6, #450
+ it lo
+ movlo r1, #-1
@ alias for mvn
mov r3, #-3
@@ -1149,7 +1158,8 @@ _func:
@ CHECK: moveq r1, #12 @ encoding: [0x0c,0x21]
@ CHECK: movne.w r1, #12 @ encoding: [0x4f,0xf0,0x0c,0x01]
@ CHECK: mov.w r6, #450 @ encoding: [0x4f,0xf4,0xe1,0x76]
-
+@ CHECK: it lo @ encoding: [0x38,0xbf]
+@ CHECK: movlo.w r1, #-1 @ encoding: [0x4f,0xf0,0xff,0x31]
@ CHECK: mvn r3, #2 @ encoding: [0x6f,0xf0,0x02,0x03]
@------------------------------------------------------------------------------
@@ -1258,6 +1268,7 @@ _func:
msr spsr_fc, r0
msr SPSR_fsxc, r5
msr cpsr_fsxc, r8
+ msr cpsr, r3
@ CHECK: msr APSR_nzcvq, r1 @ encoding: [0x81,0xf3,0x00,0x88]
@ CHECK: msr APSR_g, r2 @ encoding: [0x82,0xf3,0x00,0x84]
@@ -1273,6 +1284,7 @@ _func:
@ CHECK: msr SPSR_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89]
@ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
@ CHECK: msr CPSR_fsxc, r8 @ encoding: [0x88,0xf3,0x00,0x8f]
+@ CHECK: msr CPSR_fc, r3 @ encoding: [0x83,0xf3,0x00,0x89]
@------------------------------------------------------------------------------
@@ -2644,6 +2656,8 @@ _func:
subs r1, r2, #0x1f0
sub r2, #1
sub r0, r0, #32
+ subs r2, r2, #56
+ subs r2, #56
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
@ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f]
@@ -2658,6 +2672,8 @@ _func:
@ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71]
@ CHECK: sub.w r2, r2, #1 @ encoding: [0xa2,0xf1,0x01,0x02]
@ CHECK: sub.w r0, r0, #32 @ encoding: [0xa0,0xf1,0x20,0x00]
+@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a]
+@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a]
@------------------------------------------------------------------------------
@@ -2670,6 +2686,12 @@ _func:
sub r4, r5, r6, asr #5
sub r4, r5, r6, ror #5
sub.w r5, r2, r12, rrx
+ sub r2, sp, ip
+ sub sp, sp, ip
+ sub sp, ip
+ sub.w r2, sp, ip
+ sub.w sp, sp, ip
+ sub.w sp, ip
@ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04]
@ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14]
@@ -2678,6 +2700,12 @@ _func:
@ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14]
@ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14]
@ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
+@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02]
+@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
+@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
+@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02]
+@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
+@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d]
@------------------------------------------------------------------------------
diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s
new file mode 100644
index 0000000..dcc62d3
--- /dev/null
+++ b/test/MC/ARM/elf-reloc-condcall.s
@@ -0,0 +1,23 @@
+// RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj %s -o - | \
+// RUN: elf-dump | FileCheck -check-prefix=OBJ %s
+
+ bleq some_label
+ bl some_label
+ blx some_label
+// OBJ: .rel.text
+
+// OBJ: 'r_offset', 0x00000000
+// OBJ-NEXT: 'r_sym', 0x000004
+// OBJ-NEXT: 'r_type', 0x1d
+
+// OBJ: 'r_offset', 0x00000004
+// OBJ-NEXT: 'r_sym', 0x000004
+// OBJ-NEXT: 'r_type', 0x1c
+
+// OBJ: 'r_offset', 0x00000008
+// OBJ-NEXT: 'r_sym', 0x000004
+// OBJ-NEXT: 'r_type', 0x1c
+
+// OBJ: .symtab
+// OBJ: Symbol 4
+// OBJ-NEXT: some_label \ No newline at end of file
diff --git a/test/MC/ARM/lit.local.cfg b/test/MC/ARM/lit.local.cfg
index 92d3ff3..5700913 100644
--- a/test/MC/ARM/lit.local.cfg
+++ b/test/MC/ARM/lit.local.cfg
@@ -1,13 +1,6 @@
config.suffixes = ['.ll', '.c', '.cpp', '.s']
-def getRoot(config):
- if not config.parent:
- return config
- return getRoot(config.parent)
-
-root = getRoot(config)
-
-targets = set(root.targets_to_build.split())
+targets = set(config.root.targets_to_build.split())
if not 'ARM' in targets:
config.unsupported = True
diff --git a/test/MC/ARM/neon-add-encoding.s b/test/MC/ARM/neon-add-encoding.s
index 1fdfa4c..50c8f85 100644
--- a/test/MC/ARM/neon-add-encoding.s
+++ b/test/MC/ARM/neon-add-encoding.s
@@ -64,31 +64,86 @@
vhadd.u16 q8, q8, q9
@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3]
vhadd.u32 q8, q8, q9
-
-@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2]
+
+
+ vhadd.s8 d11, d24
+ vhadd.s16 d12, d23
+ vhadd.s32 d13, d22
+ vhadd.u8 d14, d21
+ vhadd.u16 d15, d20
+ vhadd.u32 d16, d19
+ vhadd.s8 q1, q12
+ vhadd.s16 q2, q11
+ vhadd.s32 q3, q10
+ vhadd.u8 q4, q9
+ vhadd.u16 q5, q8
+ vhadd.u32 q6, q7
+
+@ CHECK: vhadd.s8 d11, d11, d24 @ encoding: [0x28,0xb0,0x0b,0xf2]
+@ CHECK: vhadd.s16 d12, d12, d23 @ encoding: [0x27,0xc0,0x1c,0xf2]
+@ CHECK: vhadd.s32 d13, d13, d22 @ encoding: [0x26,0xd0,0x2d,0xf2]
+@ CHECK: vhadd.u8 d14, d14, d21 @ encoding: [0x25,0xe0,0x0e,0xf3]
+@ CHECK: vhadd.u16 d15, d15, d20 @ encoding: [0x24,0xf0,0x1f,0xf3]
+@ CHECK: vhadd.u32 d16, d16, d19 @ encoding: [0xa3,0x00,0x60,0xf3]
+@ CHECK: vhadd.s8 q1, q1, q12 @ encoding: [0x68,0x20,0x02,0xf2]
+@ CHECK: vhadd.s16 q2, q2, q11 @ encoding: [0x66,0x40,0x14,0xf2]
+@ CHECK: vhadd.s32 q3, q3, q10 @ encoding: [0x64,0x60,0x26,0xf2]
+@ CHECK: vhadd.u8 q4, q4, q9 @ encoding: [0x62,0x80,0x08,0xf3]
+@ CHECK: vhadd.u16 q5, q5, q8 @ encoding: [0x60,0xa0,0x1a,0xf3]
+@ CHECK: vhadd.u32 q6, q6, q7 @ encoding: [0x4e,0xc0,0x2c,0xf3]
+
vrhadd.s8 d16, d16, d17
-@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2]
vrhadd.s16 d16, d16, d17
-@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2]
vrhadd.s32 d16, d16, d17
-@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3]
vrhadd.u8 d16, d16, d17
-@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3]
vrhadd.u16 d16, d16, d17
-@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3]
vrhadd.u32 d16, d16, d17
-@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2]
vrhadd.s8 q8, q8, q9
-@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2]
vrhadd.s16 q8, q8, q9
-@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2]
vrhadd.s32 q8, q8, q9
-@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3]
vrhadd.u8 q8, q8, q9
-@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3]
vrhadd.u16 q8, q8, q9
-@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3]
vrhadd.u32 q8, q8, q9
+ @ Two-operand forms.
+ vrhadd.s8 d16, d17
+ vrhadd.s16 d16, d17
+ vrhadd.s32 d16, d17
+ vrhadd.u8 d16, d17
+ vrhadd.u16 d16, d17
+ vrhadd.u32 d16, d17
+ vrhadd.s8 q8, q9
+ vrhadd.s16 q8, q9
+ vrhadd.s32 q8, q9
+ vrhadd.u8 q8, q9
+ vrhadd.u16 q8, q9
+ vrhadd.u32 q8, q9
+
+@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3]
+@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3]
+
+@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3]
+@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3]
+
vqadd.s8 d16, d16, d17
vqadd.s16 d16, d16, d17
diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s
index cd450a8..3c97f8b 100644
--- a/test/MC/ARM/neon-shift-encoding.s
+++ b/test/MC/ARM/neon-shift-encoding.s
@@ -250,113 +250,124 @@ _foo:
@ CHECK: vsli.64 q7, q7, #63 @ encoding: [0xde,0xe5,0xbf,0xf3]
-@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2]
vshll.s8 q8, d16, #7
-@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2]
vshll.s16 q8, d16, #15
-@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2]
vshll.s32 q8, d16, #31
-@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3]
vshll.u8 q8, d16, #7
-@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3]
vshll.u16 q8, d16, #15
-@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3]
vshll.u32 q8, d16, #31
-@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3]
vshll.i8 q8, d16, #8
-@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3]
vshll.i16 q8, d16, #16
-@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3]
vshll.i32 q8, d16, #32
-@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
+
+@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2]
+@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2]
+@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2]
+@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3]
+@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3]
+@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3]
+@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3]
+@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3]
+@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3]
+
vshrn.i16 d16, q8, #8
-@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
vshrn.i32 d16, q8, #16
-@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
vshrn.i64 d16, q8, #32
-@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2]
+
+@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
+@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
+@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
+
vrshl.s8 d16, d17, d16
-@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2]
vrshl.s16 d16, d17, d16
-@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2]
vrshl.s32 d16, d17, d16
-@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf2]
vrshl.s64 d16, d17, d16
-@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3]
vrshl.u8 d16, d17, d16
-@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3]
vrshl.u16 d16, d17, d16
-@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3]
vrshl.u32 d16, d17, d16
-@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3]
vrshl.u64 d16, d17, d16
-@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2]
vrshl.s8 q8, q9, q8
-@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2]
vrshl.s16 q8, q9, q8
-@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2]
vrshl.s32 q8, q9, q8
-@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2]
vrshl.s64 q8, q9, q8
-@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3]
vrshl.u8 q8, q9, q8
-@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3]
vrshl.u16 q8, q9, q8
-@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3]
vrshl.u32 q8, q9, q8
-@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3]
vrshl.u64 q8, q9, q8
-@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2]
+
+@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2]
+@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2]
+@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2]
+@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf2]
+@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3]
+@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3]
+@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3]
+@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3]
+@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2]
+@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2]
+@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2]
+@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2]
+@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3]
+@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3]
+@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3]
+@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3]
+
vrshr.s8 d16, d16, #8
-@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2]
vrshr.s16 d16, d16, #16
-@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2]
vrshr.s32 d16, d16, #32
-@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2]
vrshr.s64 d16, d16, #64
-@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
vrshr.u8 d16, d16, #8
-@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3]
vrshr.u16 d16, d16, #16
-@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3]
vrshr.u32 d16, d16, #32
-@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3]
vrshr.u64 d16, d16, #64
-@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2]
vrshr.s8 q8, q8, #8
-@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2]
vrshr.s16 q8, q8, #16
-@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2]
vrshr.s32 q8, q8, #32
-@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2]
vrshr.s64 q8, q8, #64
-@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3]
vrshr.u8 q8, q8, #8
-@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3]
vrshr.u16 q8, q8, #16
-@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3]
vrshr.u32 q8, q8, #32
-@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
vrshr.u64 q8, q8, #64
-@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2]
+
+@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2]
+@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2]
+@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2]
+@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2]
+@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
+@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3]
+@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3]
+@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3]
+@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2]
+@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2]
+@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2]
+@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2]
+@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3]
+@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3]
+@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3]
+@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
+
+
vrshrn.i16 d16, q8, #8
-@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2]
vrshrn.i32 d16, q8, #16
-@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
vrshrn.i64 d16, q8, #32
-@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
vqrshrn.s16 d16, q8, #4
-@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
vqrshrn.s32 d16, q8, #13
-@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
vqrshrn.s64 d16, q8, #13
-@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3]
vqrshrn.u16 d16, q8, #4
-@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3]
vqrshrn.u32 d16, q8, #13
-@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3]
vqrshrn.u64 d16, q8, #13
+@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2]
+@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2]
+@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
+@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
+@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
+@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
+@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3]
+@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3]
+@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3]
+
+
@ Optional destination operand variants.
vshl.s8 q4, q5
vshl.s16 q4, q5
@@ -417,3 +428,108 @@ _foo:
@ CHECK: vshl.i16 d4, d4, #10 @ encoding: [0x14,0x45,0x9a,0xf2]
@ CHECK: vshl.i32 d4, d4, #17 @ encoding: [0x14,0x45,0xb1,0xf2]
@ CHECK: vshl.i64 d4, d4, #43 @ encoding: [0x94,0x45,0xab,0xf2]
+
+ @ Two-operand VRSHL forms.
+ vrshl.s8 d11, d4
+ vrshl.s16 d12, d5
+ vrshl.s32 d13, d6
+ vrshl.s64 d14, d7
+ vrshl.u8 d15, d8
+ vrshl.u16 d16, d9
+ vrshl.u32 d17, d10
+ vrshl.u64 d18, d11
+ vrshl.s8 q1, q8
+ vrshl.s16 q2, q15
+ vrshl.s32 q3, q14
+ vrshl.s64 q4, q13
+ vrshl.u8 q5, q12
+ vrshl.u16 q6, q11
+ vrshl.u32 q7, q10
+ vrshl.u64 q8, q9
+
+@ CHECK: vrshl.s8 d11, d11, d4 @ encoding: [0x0b,0xb5,0x04,0xf2]
+@ CHECK: vrshl.s16 d12, d12, d5 @ encoding: [0x0c,0xc5,0x15,0xf2]
+@ CHECK: vrshl.s32 d13, d13, d6 @ encoding: [0x0d,0xd5,0x26,0xf2]
+@ CHECK: vrshl.s64 d14, d14, d7 @ encoding: [0x0e,0xe5,0x37,0xf2]
+@ CHECK: vrshl.u8 d15, d15, d8 @ encoding: [0x0f,0xf5,0x08,0xf3]
+@ CHECK: vrshl.u16 d16, d16, d9 @ encoding: [0x20,0x05,0x59,0xf3]
+@ CHECK: vrshl.u32 d17, d17, d10 @ encoding: [0x21,0x15,0x6a,0xf3]
+@ CHECK: vrshl.u64 d18, d18, d11 @ encoding: [0x22,0x25,0x7b,0xf3]
+@ CHECK: vrshl.s8 q1, q1, q8 @ encoding: [0xc2,0x25,0x00,0xf2]
+@ CHECK: vrshl.s16 q2, q2, q15 @ encoding: [0xc4,0x45,0x1e,0xf2]
+@ CHECK: vrshl.s32 q3, q3, q14 @ encoding: [0xc6,0x65,0x2c,0xf2]
+@ CHECK: vrshl.s64 q4, q4, q13 @ encoding: [0xc8,0x85,0x3a,0xf2]
+@ CHECK: vrshl.u8 q5, q5, q12 @ encoding: [0xca,0xa5,0x08,0xf3]
+@ CHECK: vrshl.u16 q6, q6, q11 @ encoding: [0xcc,0xc5,0x16,0xf3]
+@ CHECK: vrshl.u32 q7, q7, q10 @ encoding: [0xce,0xe5,0x24,0xf3]
+@ CHECK: vrshl.u64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf3]
+
+
+@ Two-operand forms.
+ vshr.s8 d15, #8
+ vshr.s16 d12, #16
+ vshr.s32 d13, #32
+ vshr.s64 d14, #64
+ vshr.u8 d16, #8
+ vshr.u16 d17, #16
+ vshr.u32 d6, #32
+ vshr.u64 d10, #64
+ vshr.s8 q1, #8
+ vshr.s16 q2, #16
+ vshr.s32 q3, #32
+ vshr.s64 q4, #64
+ vshr.u8 q5, #8
+ vshr.u16 q6, #16
+ vshr.u32 q7, #32
+ vshr.u64 q8, #64
+
+@ CHECK: vshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf0,0x88,0xf2]
+@ CHECK: vshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc0,0x90,0xf2]
+@ CHECK: vshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd0,0xa0,0xf2]
+@ CHECK: vshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe0,0x80,0xf2]
+@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3]
+@ CHECK: vshr.u16 d17, d17, #16 @ encoding: [0x31,0x10,0xd0,0xf3]
+@ CHECK: vshr.u32 d6, d6, #32 @ encoding: [0x16,0x60,0xa0,0xf3]
+@ CHECK: vshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa0,0x80,0xf3]
+@ CHECK: vshr.s8 q1, q1, #8 @ encoding: [0x52,0x20,0x88,0xf2]
+@ CHECK: vshr.s16 q2, q2, #16 @ encoding: [0x54,0x40,0x90,0xf2]
+@ CHECK: vshr.s32 q3, q3, #32 @ encoding: [0x56,0x60,0xa0,0xf2]
+@ CHECK: vshr.s64 q4, q4, #64 @ encoding: [0xd8,0x80,0x80,0xf2]
+@ CHECK: vshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa0,0x88,0xf3]
+@ CHECK: vshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc0,0x90,0xf3]
+@ CHECK: vshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe0,0xa0,0xf3]
+@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3]
+
+ vrshr.s8 d15, #8
+ vrshr.s16 d12, #16
+ vrshr.s32 d13, #32
+ vrshr.s64 d14, #64
+ vrshr.u8 d16, #8
+ vrshr.u16 d17, #16
+ vrshr.u32 d6, #32
+ vrshr.u64 d10, #64
+ vrshr.s8 q1, #8
+ vrshr.s16 q2, #16
+ vrshr.s32 q3, #32
+ vrshr.s64 q4, #64
+ vrshr.u8 q5, #8
+ vrshr.u16 q6, #16
+ vrshr.u32 q7, #32
+ vrshr.u64 q8, #64
+
+@ CHECK: vrshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf2,0x88,0xf2]
+@ CHECK: vrshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc2,0x90,0xf2]
+@ CHECK: vrshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd2,0xa0,0xf2]
+@ CHECK: vrshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe2,0x80,0xf2]
+@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3]
+@ CHECK: vrshr.u16 d17, d17, #16 @ encoding: [0x31,0x12,0xd0,0xf3]
+@ CHECK: vrshr.u32 d6, d6, #32 @ encoding: [0x16,0x62,0xa0,0xf3]
+@ CHECK: vrshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa2,0x80,0xf3]
+@ CHECK: vrshr.s8 q1, q1, #8 @ encoding: [0x52,0x22,0x88,0xf2]
+@ CHECK: vrshr.s16 q2, q2, #16 @ encoding: [0x54,0x42,0x90,0xf2]
+@ CHECK: vrshr.s32 q3, q3, #32 @ encoding: [0x56,0x62,0xa0,0xf2]
+@ CHECK: vrshr.s64 q4, q4, #64 @ encoding: [0xd8,0x82,0x80,0xf2]
+@ CHECK: vrshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa2,0x88,0xf3]
+@ CHECK: vrshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc2,0x90,0xf3]
+@ CHECK: vrshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe2,0xa0,0xf3]
+@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3]
diff --git a/test/MC/ARM/neon-shuffle-encoding.s b/test/MC/ARM/neon-shuffle-encoding.s
index 26734c1..0f07d9f 100644
--- a/test/MC/ARM/neon-shuffle-encoding.s
+++ b/test/MC/ARM/neon-shuffle-encoding.s
@@ -59,6 +59,8 @@
vzip.8 q9, q8
vzip.16 q9, q8
vzip.32 q9, q8
+ vzip.32 d2, d3
+ vuzp.32 d2, d3
@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3]
@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3]
@@ -70,6 +72,8 @@
@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3]
@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3]
@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3]
+@ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3]
+@ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3]
@ VTRN alternate size suffices
diff --git a/test/MC/ARM/neon-sub-encoding.s b/test/MC/ARM/neon-sub-encoding.s
index 0622e19..8eb38a5 100644
--- a/test/MC/ARM/neon-sub-encoding.s
+++ b/test/MC/ARM/neon-sub-encoding.s
@@ -132,3 +132,29 @@
vrsubhn.i32 d16, q8, q9
@ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
vrsubhn.i64 d16, q8, q9
+
+ vhsub.s8 d11, d24
+ vhsub.s16 d12, d23
+ vhsub.s32 d13, d22
+ vhsub.u8 d14, d21
+ vhsub.u16 d15, d20
+ vhsub.u32 d16, d19
+ vhsub.s8 q1, q12
+ vhsub.s16 q2, q11
+ vhsub.s32 q3, q10
+ vhsub.u8 q4, q9
+ vhsub.u16 q5, q8
+ vhsub.u32 q6, q7
+
+@ CHECK: vhsub.s8 d11, d11, d24 @ encoding: [0x28,0xb2,0x0b,0xf2]
+@ CHECK: vhsub.s16 d12, d12, d23 @ encoding: [0x27,0xc2,0x1c,0xf2]
+@ CHECK: vhsub.s32 d13, d13, d22 @ encoding: [0x26,0xd2,0x2d,0xf2]
+@ CHECK: vhsub.u8 d14, d14, d21 @ encoding: [0x25,0xe2,0x0e,0xf3]
+@ CHECK: vhsub.u16 d15, d15, d20 @ encoding: [0x24,0xf2,0x1f,0xf3]
+@ CHECK: vhsub.u32 d16, d16, d19 @ encoding: [0xa3,0x02,0x60,0xf3]
+@ CHECK: vhsub.s8 q1, q1, q12 @ encoding: [0x68,0x22,0x02,0xf2]
+@ CHECK: vhsub.s16 q2, q2, q11 @ encoding: [0x66,0x42,0x14,0xf2]
+@ CHECK: vhsub.s32 q3, q3, q10 @ encoding: [0x64,0x62,0x26,0xf2]
+@ CHECK: vhsub.u8 q4, q4, q9 @ encoding: [0x62,0x82,0x08,0xf3]
+@ CHECK: vhsub.u16 q5, q5, q8 @ encoding: [0x60,0xa2,0x1a,0xf3]
+@ CHECK: vhsub.u32 q6, q6, q7 @ encoding: [0x4e,0xc2,0x2c,0xf3]
diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s
index 1f07461..f5feca4 100644
--- a/test/MC/ARM/neon-vst-encoding.s
+++ b/test/MC/ARM/neon-vst-encoding.s
@@ -268,3 +268,11 @@
@ rdar://11082188
vst2.8 {d8, d10}, [r4]
@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4]
+
+ vst1.32 {d9[1]}, [r3, :32]
+ vst1.32 {d27[1]}, [r9, :32]!
+ vst1.32 {d27[1]}, [r3, :32], r5
+@ CHECK: vst1.32 {d9[1]}, [r3, :32] @ encoding: [0xbf,0x98,0x83,0xf4]
+@ CHECK: vst1.32 {d27[1]}, [r9, :32]! @ encoding: [0xbd,0xb8,0xc9,0xf4]
+@ CHECK: vst1.32 {d27[1]}, [r3, :32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4]
+
diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s
new file mode 100644
index 0000000..2138eed
--- /dev/null
+++ b/test/MC/ARM/neon-vswp.s
@@ -0,0 +1,7 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
+
+vswp d1, d2
+vswp q1, q2
+
+@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
+@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s
new file mode 100644
index 0000000..cc87a38
--- /dev/null
+++ b/test/MC/ARM/vfp4.s
@@ -0,0 +1,50 @@
+@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM
+@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB
+
+@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
+@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
+vfma.f64 d16, d18, d17
+
+@ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
+@ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
+vfma.f32 s2, s4, s0
+
+@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
+@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
+vfma.f32 d16, d18, d17
+
+@ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
+@ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c]
+vfma.f32 q2, q4, q0
+
+@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
+@ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b]
+vfnma.f64 d16, d18, d17
+
+@ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee]
+@ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a]
+vfnma.f32 s2, s4, s0
+
+@ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee]
+@ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b]
+vfms.f64 d16, d18, d17
+
+@ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee]
+@ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a]
+vfms.f32 s2, s4, s0
+
+@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2]
+@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c]
+vfms.f32 d16, d18, d17
+
+@ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2]
+@ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c]
+vfms.f32 q2, q4, q0
+
+@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
+@ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b]
+vfnms.f64 d16, d18, d17
+
+@ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee]
+@ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
+vfnms.f32 s2, s4, s0
generated by cgit v1.1 at 2025-08-15 12:38:15 +0000