diff options
Diffstat (limited to 'test/MC')
61 files changed, 4121 insertions, 189 deletions
diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s index 2f34748..74dfb99 100644 --- a/test/MC/ARM/arm_fixups.s +++ b/test/MC/ARM/arm_fixups.s @@ -3,7 +3,7 @@ bl _printf @ CHECK: bl _printf @ encoding: [A,A,A,0xeb] -@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_bl +@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbl mov r9, :lower16:(_foo) movw r9, :lower16:(_foo) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 4ae1ac7..4788ac7 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -382,13 +382,16 @@ Lforward: @------------------------------------------------------------------------------ bl _bar + bleq _bar blx _bar blls #28634268 blx #32424576 blx #16212288 @ CHECK: bl _bar @ encoding: [A,A,A,0xeb] -@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_bl +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbl +@ CHECK: bleq _bar @ encoding: [A,A,A,0x0b] +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_condbl @ CHECK: blx _bar @ encoding: [A,A,A,0xfa] @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx @ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b] @@ -494,6 +497,7 @@ Lforward: cmp r7, r8, ror r2 cmp r1, r6, rrx cmp r0, #-2 + cmp lr, #0 @ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] @ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1] @@ -508,6 +512,7 @@ Lforward: @ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1] @ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1] @ CHECK: cmn r0, #2 @ encoding: [0x02,0x00,0x70,0xe3] +@ CHECK: cmp lr, #0 @ encoding: [0x00,0x00,0x5e,0xe3] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s index 6e830cd..bc2605c 100644 --- a/test/MC/ARM/basic-thumb-instructions.s +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -59,12 +59,16 @@ _func: add sp, sp, #4 add r2, sp, #8 add r2, sp, #1020 + add sp, sp, #-8 + add sp, #-8 @ CHECK: add sp, #4 @ encoding: [0x01,0xb0] @ CHECK: add sp, #508 @ encoding: [0x7f,0xb0] @ CHECK: add sp, #4 @ encoding: [0x01,0xb0] @ CHECK: add r2, sp, #8 @ encoding: [0x02,0xaa] @ CHECK: add r2, sp, #1020 @ encoding: [0xff,0xaa] +@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0] +@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0] @------------------------------------------------------------------------------ @@ -93,10 +97,16 @@ _func: asrs r2, r3, #32 asrs r2, r3, #5 asrs r2, r3, #1 + asrs r5, #21 + asrs r5, r5, #21 + asrs r3, r5, #21 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10] @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11] @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10] +@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15] +@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15] +@ CHECK: asrs r3, r5, #21 @ encoding: [0x6b,0x15] @------------------------------------------------------------------------------ @@ -315,9 +325,15 @@ _func: @------------------------------------------------------------------------------ lsls r4, r5, #0 lsls r4, r5, #4 + lsls r3, #12 + lsls r3, r3, #12 + lsls r1, r3, #12 @ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00] @ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01] +@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03] +@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03] +@ CHECK: lsls r1, r3, #12 @ encoding: [0x19,0x03] @------------------------------------------------------------------------------ @@ -333,9 +349,15 @@ _func: @------------------------------------------------------------------------------ lsrs r1, r3, #1 lsrs r1, r3, #32 + lsrs r4, #20 + lsrs r4, r4, #20 + lsrs r2, r4, #20 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08] @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08] +@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d] +@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d] +@ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index ce97ca6..d2e208b 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -75,6 +75,8 @@ _func: adds r1, r2, #0x1f0 add r2, #1 add r0, r0, #32 + adds r2, r2, #56 + adds r2, #56 @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] @@ -89,6 +91,8 @@ _func: @ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71] @ CHECK: add.w r2, r2, #1 @ encoding: [0x02,0xf1,0x01,0x02] @ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00] +@ CHECK: adds r2, #56 @ encoding: [0x38,0x32] +@ CHECK: adds r2, #56 @ encoding: [0x38,0x32] @------------------------------------------------------------------------------ @@ -368,7 +372,8 @@ _func: cmp sp, r6, lsr #1 cmp r2, r5, asr #24 cmp r1, r4, ror #15 - cmp r0, #-2 + cmp r2, #-2 + cmp r9, #1 @ CHECK: cmp.w r5, #65280 @ encoding: [0xb5,0xf5,0x7f,0x4f] @ CHECK: cmp.w r4, r12 @ encoding: [0xb4,0xeb,0x0c,0x0f] @@ -377,7 +382,9 @@ _func: @ CHECK: cmp.w sp, r6, lsr #1 @ encoding: [0xbd,0xeb,0x56,0x0f] @ CHECK: cmp.w r2, r5, asr #24 @ encoding: [0xb2,0xeb,0x25,0x6f] @ CHECK: cmp.w r1, r4, ror #15 @ encoding: [0xb1,0xeb,0xf4,0x3f] -@ CHECK: cmn.w r0, #2 @ encoding: [0x10,0xf1,0x02,0x0f] +@ CHECK: cmn.w r2, #2 @ encoding: [0x12,0xf1,0x02,0x0f] +@ CHECK: cmp.w r9, #1 @ encoding: [0xb9,0xf1,0x01,0x0f] + @------------------------------------------------------------------------------ @ DBG @@ -1130,6 +1137,8 @@ _func: moveq r1, #12 movne.w r1, #12 mov.w r6, #450 + it lo + movlo r1, #-1 @ alias for mvn mov r3, #-3 @@ -1149,7 +1158,8 @@ _func: @ CHECK: moveq r1, #12 @ encoding: [0x0c,0x21] @ CHECK: movne.w r1, #12 @ encoding: [0x4f,0xf0,0x0c,0x01] @ CHECK: mov.w r6, #450 @ encoding: [0x4f,0xf4,0xe1,0x76] - +@ CHECK: it lo @ encoding: [0x38,0xbf] +@ CHECK: movlo.w r1, #-1 @ encoding: [0x4f,0xf0,0xff,0x31] @ CHECK: mvn r3, #2 @ encoding: [0x6f,0xf0,0x02,0x03] @------------------------------------------------------------------------------ @@ -1258,6 +1268,7 @@ _func: msr spsr_fc, r0 msr SPSR_fsxc, r5 msr cpsr_fsxc, r8 + msr cpsr, r3 @ CHECK: msr APSR_nzcvq, r1 @ encoding: [0x81,0xf3,0x00,0x88] @ CHECK: msr APSR_g, r2 @ encoding: [0x82,0xf3,0x00,0x84] @@ -1273,6 +1284,7 @@ _func: @ CHECK: msr SPSR_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89] @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f] @ CHECK: msr CPSR_fsxc, r8 @ encoding: [0x88,0xf3,0x00,0x8f] +@ CHECK: msr CPSR_fc, r3 @ encoding: [0x83,0xf3,0x00,0x89] @------------------------------------------------------------------------------ @@ -2644,6 +2656,8 @@ _func: subs r1, r2, #0x1f0 sub r2, #1 sub r0, r0, #32 + subs r2, r2, #56 + subs r2, #56 @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f] @@ -2658,6 +2672,8 @@ _func: @ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71] @ CHECK: sub.w r2, r2, #1 @ encoding: [0xa2,0xf1,0x01,0x02] @ CHECK: sub.w r0, r0, #32 @ encoding: [0xa0,0xf1,0x20,0x00] +@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a] +@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a] @------------------------------------------------------------------------------ @@ -2670,6 +2686,12 @@ _func: sub r4, r5, r6, asr #5 sub r4, r5, r6, ror #5 sub.w r5, r2, r12, rrx + sub r2, sp, ip + sub sp, sp, ip + sub sp, ip + sub.w r2, sp, ip + sub.w sp, sp, ip + sub.w sp, ip @ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04] @ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14] @@ -2678,6 +2700,12 @@ _func: @ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14] @ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14] @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05] +@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s new file mode 100644 index 0000000..dcc62d3 --- /dev/null +++ b/test/MC/ARM/elf-reloc-condcall.s @@ -0,0 +1,23 @@ +// RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj %s -o - | \ +// RUN: elf-dump | FileCheck -check-prefix=OBJ %s + + bleq some_label + bl some_label + blx some_label +// OBJ: .rel.text + +// OBJ: 'r_offset', 0x00000000 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1d + +// OBJ: 'r_offset', 0x00000004 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1c + +// OBJ: 'r_offset', 0x00000008 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1c + +// OBJ: .symtab +// OBJ: Symbol 4 +// OBJ-NEXT: some_label
\ No newline at end of file diff --git a/test/MC/ARM/lit.local.cfg b/test/MC/ARM/lit.local.cfg index 92d3ff3..5700913 100644 --- a/test/MC/ARM/lit.local.cfg +++ b/test/MC/ARM/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.ll', '.c', '.cpp', '.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: config.unsupported = True diff --git a/test/MC/ARM/neon-add-encoding.s b/test/MC/ARM/neon-add-encoding.s index 1fdfa4c..50c8f85 100644 --- a/test/MC/ARM/neon-add-encoding.s +++ b/test/MC/ARM/neon-add-encoding.s @@ -64,31 +64,86 @@ vhadd.u16 q8, q8, q9 @ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3] vhadd.u32 q8, q8, q9 - -@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2] + + + vhadd.s8 d11, d24 + vhadd.s16 d12, d23 + vhadd.s32 d13, d22 + vhadd.u8 d14, d21 + vhadd.u16 d15, d20 + vhadd.u32 d16, d19 + vhadd.s8 q1, q12 + vhadd.s16 q2, q11 + vhadd.s32 q3, q10 + vhadd.u8 q4, q9 + vhadd.u16 q5, q8 + vhadd.u32 q6, q7 + +@ CHECK: vhadd.s8 d11, d11, d24 @ encoding: [0x28,0xb0,0x0b,0xf2] +@ CHECK: vhadd.s16 d12, d12, d23 @ encoding: [0x27,0xc0,0x1c,0xf2] +@ CHECK: vhadd.s32 d13, d13, d22 @ encoding: [0x26,0xd0,0x2d,0xf2] +@ CHECK: vhadd.u8 d14, d14, d21 @ encoding: [0x25,0xe0,0x0e,0xf3] +@ CHECK: vhadd.u16 d15, d15, d20 @ encoding: [0x24,0xf0,0x1f,0xf3] +@ CHECK: vhadd.u32 d16, d16, d19 @ encoding: [0xa3,0x00,0x60,0xf3] +@ CHECK: vhadd.s8 q1, q1, q12 @ encoding: [0x68,0x20,0x02,0xf2] +@ CHECK: vhadd.s16 q2, q2, q11 @ encoding: [0x66,0x40,0x14,0xf2] +@ CHECK: vhadd.s32 q3, q3, q10 @ encoding: [0x64,0x60,0x26,0xf2] +@ CHECK: vhadd.u8 q4, q4, q9 @ encoding: [0x62,0x80,0x08,0xf3] +@ CHECK: vhadd.u16 q5, q5, q8 @ encoding: [0x60,0xa0,0x1a,0xf3] +@ CHECK: vhadd.u32 q6, q6, q7 @ encoding: [0x4e,0xc0,0x2c,0xf3] + vrhadd.s8 d16, d16, d17 -@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2] vrhadd.s16 d16, d16, d17 -@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2] vrhadd.s32 d16, d16, d17 -@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3] vrhadd.u8 d16, d16, d17 -@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3] vrhadd.u16 d16, d16, d17 -@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3] vrhadd.u32 d16, d16, d17 -@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2] vrhadd.s8 q8, q8, q9 -@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2] vrhadd.s16 q8, q8, q9 -@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2] vrhadd.s32 q8, q8, q9 -@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3] vrhadd.u8 q8, q8, q9 -@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3] vrhadd.u16 q8, q8, q9 -@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] vrhadd.u32 q8, q8, q9 + @ Two-operand forms. + vrhadd.s8 d16, d17 + vrhadd.s16 d16, d17 + vrhadd.s32 d16, d17 + vrhadd.u8 d16, d17 + vrhadd.u16 d16, d17 + vrhadd.u32 d16, d17 + vrhadd.s8 q8, q9 + vrhadd.s16 q8, q9 + vrhadd.s32 q8, q9 + vrhadd.u8 q8, q9 + vrhadd.u16 q8, q9 + vrhadd.u32 q8, q9 + +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2] +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2] +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2] +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3] +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3] +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3] +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2] +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2] +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2] +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3] +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3] +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] + +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2] +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2] +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2] +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3] +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3] +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3] +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2] +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2] +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2] +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3] +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3] +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] + vqadd.s8 d16, d16, d17 vqadd.s16 d16, d16, d17 diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s index cd450a8..3c97f8b 100644 --- a/test/MC/ARM/neon-shift-encoding.s +++ b/test/MC/ARM/neon-shift-encoding.s @@ -250,113 +250,124 @@ _foo: @ CHECK: vsli.64 q7, q7, #63 @ encoding: [0xde,0xe5,0xbf,0xf3] -@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] vshll.s8 q8, d16, #7 -@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] vshll.s16 q8, d16, #15 -@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] vshll.s32 q8, d16, #31 -@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] vshll.u8 q8, d16, #7 -@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] vshll.u16 q8, d16, #15 -@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] vshll.u32 q8, d16, #31 -@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] vshll.i8 q8, d16, #8 -@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] vshll.i16 q8, d16, #16 -@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] vshll.i32 q8, d16, #32 -@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] + +@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] +@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] +@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] +@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] +@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] +@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] +@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] +@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] +@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] + vshrn.i16 d16, q8, #8 -@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] vshrn.i32 d16, q8, #16 -@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] vshrn.i64 d16, q8, #32 -@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] + +@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] +@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] +@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] + vrshl.s8 d16, d17, d16 -@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] vrshl.s16 d16, d17, d16 -@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] vrshl.s32 d16, d17, d16 -@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf2] vrshl.s64 d16, d17, d16 -@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] vrshl.u8 d16, d17, d16 -@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] vrshl.u16 d16, d17, d16 -@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] vrshl.u32 d16, d17, d16 -@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] vrshl.u64 d16, d17, d16 -@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] vrshl.s8 q8, q9, q8 -@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] vrshl.s16 q8, q9, q8 -@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] vrshl.s32 q8, q9, q8 -@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] vrshl.s64 q8, q9, q8 -@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] vrshl.u8 q8, q9, q8 -@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] vrshl.u16 q8, q9, q8 -@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] vrshl.u32 q8, q9, q8 -@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] vrshl.u64 q8, q9, q8 -@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] + +@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] +@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] +@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] +@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf2] +@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] +@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] +@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] +@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] +@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] +@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] +@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] +@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] +@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] +@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] +@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] +@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] + vrshr.s8 d16, d16, #8 -@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] vrshr.s16 d16, d16, #16 -@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] vrshr.s32 d16, d16, #32 -@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] vrshr.s64 d16, d16, #64 -@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] vrshr.u8 d16, d16, #8 -@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] vrshr.u16 d16, d16, #16 -@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] vrshr.u32 d16, d16, #32 -@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] vrshr.u64 d16, d16, #64 -@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] vrshr.s8 q8, q8, #8 -@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] vrshr.s16 q8, q8, #16 -@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] vrshr.s32 q8, q8, #32 -@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] vrshr.s64 q8, q8, #64 -@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] vrshr.u8 q8, q8, #8 -@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] vrshr.u16 q8, q8, #16 -@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] vrshr.u32 q8, q8, #32 -@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] vrshr.u64 q8, q8, #64 -@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] + +@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] +@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] +@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] +@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] +@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] +@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] +@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] +@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] +@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] +@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] +@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] +@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] +@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] +@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] + + vrshrn.i16 d16, q8, #8 -@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] vrshrn.i32 d16, q8, #16 -@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] vrshrn.i64 d16, q8, #32 -@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2] vqrshrn.s16 d16, q8, #4 -@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2] vqrshrn.s32 d16, q8, #13 -@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2] vqrshrn.s64 d16, q8, #13 -@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3] vqrshrn.u16 d16, q8, #4 -@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3] vqrshrn.u32 d16, q8, #13 -@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3] vqrshrn.u64 d16, q8, #13 +@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] +@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] +@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] +@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2] +@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2] +@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2] +@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3] +@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3] +@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3] + + @ Optional destination operand variants. vshl.s8 q4, q5 vshl.s16 q4, q5 @@ -417,3 +428,108 @@ _foo: @ CHECK: vshl.i16 d4, d4, #10 @ encoding: [0x14,0x45,0x9a,0xf2] @ CHECK: vshl.i32 d4, d4, #17 @ encoding: [0x14,0x45,0xb1,0xf2] @ CHECK: vshl.i64 d4, d4, #43 @ encoding: [0x94,0x45,0xab,0xf2] + + @ Two-operand VRSHL forms. + vrshl.s8 d11, d4 + vrshl.s16 d12, d5 + vrshl.s32 d13, d6 + vrshl.s64 d14, d7 + vrshl.u8 d15, d8 + vrshl.u16 d16, d9 + vrshl.u32 d17, d10 + vrshl.u64 d18, d11 + vrshl.s8 q1, q8 + vrshl.s16 q2, q15 + vrshl.s32 q3, q14 + vrshl.s64 q4, q13 + vrshl.u8 q5, q12 + vrshl.u16 q6, q11 + vrshl.u32 q7, q10 + vrshl.u64 q8, q9 + +@ CHECK: vrshl.s8 d11, d11, d4 @ encoding: [0x0b,0xb5,0x04,0xf2] +@ CHECK: vrshl.s16 d12, d12, d5 @ encoding: [0x0c,0xc5,0x15,0xf2] +@ CHECK: vrshl.s32 d13, d13, d6 @ encoding: [0x0d,0xd5,0x26,0xf2] +@ CHECK: vrshl.s64 d14, d14, d7 @ encoding: [0x0e,0xe5,0x37,0xf2] +@ CHECK: vrshl.u8 d15, d15, d8 @ encoding: [0x0f,0xf5,0x08,0xf3] +@ CHECK: vrshl.u16 d16, d16, d9 @ encoding: [0x20,0x05,0x59,0xf3] +@ CHECK: vrshl.u32 d17, d17, d10 @ encoding: [0x21,0x15,0x6a,0xf3] +@ CHECK: vrshl.u64 d18, d18, d11 @ encoding: [0x22,0x25,0x7b,0xf3] +@ CHECK: vrshl.s8 q1, q1, q8 @ encoding: [0xc2,0x25,0x00,0xf2] +@ CHECK: vrshl.s16 q2, q2, q15 @ encoding: [0xc4,0x45,0x1e,0xf2] +@ CHECK: vrshl.s32 q3, q3, q14 @ encoding: [0xc6,0x65,0x2c,0xf2] +@ CHECK: vrshl.s64 q4, q4, q13 @ encoding: [0xc8,0x85,0x3a,0xf2] +@ CHECK: vrshl.u8 q5, q5, q12 @ encoding: [0xca,0xa5,0x08,0xf3] +@ CHECK: vrshl.u16 q6, q6, q11 @ encoding: [0xcc,0xc5,0x16,0xf3] +@ CHECK: vrshl.u32 q7, q7, q10 @ encoding: [0xce,0xe5,0x24,0xf3] +@ CHECK: vrshl.u64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf3] + + +@ Two-operand forms. + vshr.s8 d15, #8 + vshr.s16 d12, #16 + vshr.s32 d13, #32 + vshr.s64 d14, #64 + vshr.u8 d16, #8 + vshr.u16 d17, #16 + vshr.u32 d6, #32 + vshr.u64 d10, #64 + vshr.s8 q1, #8 + vshr.s16 q2, #16 + vshr.s32 q3, #32 + vshr.s64 q4, #64 + vshr.u8 q5, #8 + vshr.u16 q6, #16 + vshr.u32 q7, #32 + vshr.u64 q8, #64 + +@ CHECK: vshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf0,0x88,0xf2] +@ CHECK: vshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc0,0x90,0xf2] +@ CHECK: vshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd0,0xa0,0xf2] +@ CHECK: vshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe0,0x80,0xf2] +@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] +@ CHECK: vshr.u16 d17, d17, #16 @ encoding: [0x31,0x10,0xd0,0xf3] +@ CHECK: vshr.u32 d6, d6, #32 @ encoding: [0x16,0x60,0xa0,0xf3] +@ CHECK: vshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa0,0x80,0xf3] +@ CHECK: vshr.s8 q1, q1, #8 @ encoding: [0x52,0x20,0x88,0xf2] +@ CHECK: vshr.s16 q2, q2, #16 @ encoding: [0x54,0x40,0x90,0xf2] +@ CHECK: vshr.s32 q3, q3, #32 @ encoding: [0x56,0x60,0xa0,0xf2] +@ CHECK: vshr.s64 q4, q4, #64 @ encoding: [0xd8,0x80,0x80,0xf2] +@ CHECK: vshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa0,0x88,0xf3] +@ CHECK: vshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc0,0x90,0xf3] +@ CHECK: vshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe0,0xa0,0xf3] +@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] + + vrshr.s8 d15, #8 + vrshr.s16 d12, #16 + vrshr.s32 d13, #32 + vrshr.s64 d14, #64 + vrshr.u8 d16, #8 + vrshr.u16 d17, #16 + vrshr.u32 d6, #32 + vrshr.u64 d10, #64 + vrshr.s8 q1, #8 + vrshr.s16 q2, #16 + vrshr.s32 q3, #32 + vrshr.s64 q4, #64 + vrshr.u8 q5, #8 + vrshr.u16 q6, #16 + vrshr.u32 q7, #32 + vrshr.u64 q8, #64 + +@ CHECK: vrshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf2,0x88,0xf2] +@ CHECK: vrshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc2,0x90,0xf2] +@ CHECK: vrshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd2,0xa0,0xf2] +@ CHECK: vrshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe2,0x80,0xf2] +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] +@ CHECK: vrshr.u16 d17, d17, #16 @ encoding: [0x31,0x12,0xd0,0xf3] +@ CHECK: vrshr.u32 d6, d6, #32 @ encoding: [0x16,0x62,0xa0,0xf3] +@ CHECK: vrshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa2,0x80,0xf3] +@ CHECK: vrshr.s8 q1, q1, #8 @ encoding: [0x52,0x22,0x88,0xf2] +@ CHECK: vrshr.s16 q2, q2, #16 @ encoding: [0x54,0x42,0x90,0xf2] +@ CHECK: vrshr.s32 q3, q3, #32 @ encoding: [0x56,0x62,0xa0,0xf2] +@ CHECK: vrshr.s64 q4, q4, #64 @ encoding: [0xd8,0x82,0x80,0xf2] +@ CHECK: vrshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa2,0x88,0xf3] +@ CHECK: vrshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc2,0x90,0xf3] +@ CHECK: vrshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe2,0xa0,0xf3] +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] diff --git a/test/MC/ARM/neon-shuffle-encoding.s b/test/MC/ARM/neon-shuffle-encoding.s index 26734c1..0f07d9f 100644 --- a/test/MC/ARM/neon-shuffle-encoding.s +++ b/test/MC/ARM/neon-shuffle-encoding.s @@ -59,6 +59,8 @@ vzip.8 q9, q8 vzip.16 q9, q8 vzip.32 q9, q8 + vzip.32 d2, d3 + vuzp.32 d2, d3 @ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3] @ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3] @@ -70,6 +72,8 @@ @ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3] @ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3] @ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] +@ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3] +@ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3] @ VTRN alternate size suffices diff --git a/test/MC/ARM/neon-sub-encoding.s b/test/MC/ARM/neon-sub-encoding.s index 0622e19..8eb38a5 100644 --- a/test/MC/ARM/neon-sub-encoding.s +++ b/test/MC/ARM/neon-sub-encoding.s @@ -132,3 +132,29 @@ vrsubhn.i32 d16, q8, q9 @ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3] vrsubhn.i64 d16, q8, q9 + + vhsub.s8 d11, d24 + vhsub.s16 d12, d23 + vhsub.s32 d13, d22 + vhsub.u8 d14, d21 + vhsub.u16 d15, d20 + vhsub.u32 d16, d19 + vhsub.s8 q1, q12 + vhsub.s16 q2, q11 + vhsub.s32 q3, q10 + vhsub.u8 q4, q9 + vhsub.u16 q5, q8 + vhsub.u32 q6, q7 + +@ CHECK: vhsub.s8 d11, d11, d24 @ encoding: [0x28,0xb2,0x0b,0xf2] +@ CHECK: vhsub.s16 d12, d12, d23 @ encoding: [0x27,0xc2,0x1c,0xf2] +@ CHECK: vhsub.s32 d13, d13, d22 @ encoding: [0x26,0xd2,0x2d,0xf2] +@ CHECK: vhsub.u8 d14, d14, d21 @ encoding: [0x25,0xe2,0x0e,0xf3] +@ CHECK: vhsub.u16 d15, d15, d20 @ encoding: [0x24,0xf2,0x1f,0xf3] +@ CHECK: vhsub.u32 d16, d16, d19 @ encoding: [0xa3,0x02,0x60,0xf3] +@ CHECK: vhsub.s8 q1, q1, q12 @ encoding: [0x68,0x22,0x02,0xf2] +@ CHECK: vhsub.s16 q2, q2, q11 @ encoding: [0x66,0x42,0x14,0xf2] +@ CHECK: vhsub.s32 q3, q3, q10 @ encoding: [0x64,0x62,0x26,0xf2] +@ CHECK: vhsub.u8 q4, q4, q9 @ encoding: [0x62,0x82,0x08,0xf3] +@ CHECK: vhsub.u16 q5, q5, q8 @ encoding: [0x60,0xa2,0x1a,0xf3] +@ CHECK: vhsub.u32 q6, q6, q7 @ encoding: [0x4e,0xc2,0x2c,0xf3] diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s index 1f07461..f5feca4 100644 --- a/test/MC/ARM/neon-vst-encoding.s +++ b/test/MC/ARM/neon-vst-encoding.s @@ -268,3 +268,11 @@ @ rdar://11082188 vst2.8 {d8, d10}, [r4] @ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4] + + vst1.32 {d9[1]}, [r3, :32] + vst1.32 {d27[1]}, [r9, :32]! + vst1.32 {d27[1]}, [r3, :32], r5 +@ CHECK: vst1.32 {d9[1]}, [r3, :32] @ encoding: [0xbf,0x98,0x83,0xf4] +@ CHECK: vst1.32 {d27[1]}, [r9, :32]! @ encoding: [0xbd,0xb8,0xc9,0xf4] +@ CHECK: vst1.32 {d27[1]}, [r3, :32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4] + diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s new file mode 100644 index 0000000..2138eed --- /dev/null +++ b/test/MC/ARM/neon-vswp.s @@ -0,0 +1,7 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + +vswp d1, d2 +vswp q1, q2 + +@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3] +@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3] diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s new file mode 100644 index 0000000..cc87a38 --- /dev/null +++ b/test/MC/ARM/vfp4.s @@ -0,0 +1,50 @@ +@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM +@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB + +@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] +@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] +vfma.f64 d16, d18, d17 + +@ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee] +@ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a] +vfma.f32 s2, s4, s0 + +@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] +@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] +vfma.f32 d16, d18, d17 + +@ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2] +@ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c] +vfma.f32 q2, q4, q0 + +@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] +@ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] +vfnma.f64 d16, d18, d17 + +@ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee] +@ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a] +vfnma.f32 s2, s4, s0 + +@ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] +@ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] +vfms.f64 d16, d18, d17 + +@ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee] +@ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a] +vfms.f32 s2, s4, s0 + +@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] +@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] +vfms.f32 d16, d18, d17 + +@ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2] +@ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c] +vfms.f32 q2, q4, q0 + +@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] +@ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] +vfnms.f64 d16, d18, d17 + +@ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee] +@ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a] +vfnms.f32 s2, s4, s0 diff --git a/test/MC/AsmParser/lit.local.cfg b/test/MC/AsmParser/lit.local.cfg index 1f53769..6c49f08 100644 --- a/test/MC/AsmParser/lit.local.cfg +++ b/test/MC/AsmParser/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/AsmParser/macro-args.s b/test/MC/AsmParser/macro-args.s index 4b87899..13b197a 100644 --- a/test/MC/AsmParser/macro-args.s +++ b/test/MC/AsmParser/macro-args.s @@ -18,3 +18,27 @@ bar // CHECK: .long 3 // CHECK: .long 0 + + +.macro top + middle _$0, $1 +.endm +.macro middle + $0: + .if $n > 1 + bottom $1 + .endif +.endm +.macro bottom + .set fred, $0 +.endm + +.text + +top foo +top bar, 42 + +// CHECK: _foo: +// CHECK-NOT: fred +// CHECK: _bar +// CHECK-NEXT: fred = 42 diff --git a/test/MC/COFF/lit.local.cfg b/test/MC/COFF/lit.local.cfg index ec8d4d3..41a8434 100644 --- a/test/MC/COFF/lit.local.cfg +++ b/test/MC/COFF/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.s', '.ll'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 264a78a..471076a 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -201,7 +201,7 @@ 0x20 0x51 0x17 0xe6 # CHECK: strdeq r2, r3, [r0], -r8 -0xf8 0x24 0x00 0x00 +0xf8 0x20 0x00 0x00 # CHECK: ldrdeq r2, r3, [r0], -r12 0xdc 0x24 0x00 0x00 @@ -321,3 +321,6 @@ # CHECK: ldmgt sp!, {r9} 0x00 0x02 0xbd 0xc8 +# CHECK: cdp2 p10, #0, c6, c12, c0, #7 +0xe0 0x6a 0x0c 0xfe + diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt deleted file mode 100644 index 067dcb3..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. -0x10 0x51 0x37 0xe6 - - diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt new file mode 100644 index 0000000..aaae6ce --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: invalid instruction encoding +0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt new file mode 100644 index 0000000..8ff3a2b --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt new file mode 100644 index 0000000..bb87ade --- /dev/null +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE + +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.68 LDRD (register) +# if Rt{0} = 1 then UNDEFINED; + +# V4: invalid instruction encoding +# V5TE: ldrd +0xd0 0x10 0x00 0x01 + diff --git a/test/MC/Disassembler/ARM/lit.local.cfg b/test/MC/Disassembler/ARM/lit.local.cfg index c5dd3fb..22a76e5 100644 --- a/test/MC/Disassembler/ARM/lit.local.cfg +++ b/test/MC/Disassembler/ARM/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.txt'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 998e9e8..c5dbee3 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -2061,3 +2061,222 @@ # CHECK: vst4.16 {d8, d10, d12, d14}, [r4] 0x8f 0x81 0x04 0xf4 # CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x0d 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4]! +0x4d 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4]! +0x8d 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4]! +0xcd 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4]! +0x06 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4], r6 +0x46 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4], r6 +0x86 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4], r6 +0xc6 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4], r6 +0x0d 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4]! +0x06 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x0d 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x0d 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x4d 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x8d 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x06 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x0d 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x0d 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x4f 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4] +0x8f 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4] +0xcf 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4] +0x0f 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4] +0x4f 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4] +0x8f 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4] +0x0f 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4] +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x4f 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4] +0x8f 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4] +0x0f 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4] +0x4d 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x46 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x8d 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x86 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x06 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x0f 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x0f 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x0f 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x0f 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11256967 +0x0f 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2] +0x4f 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2] +0x8f 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2] +0x0d 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2]! +0x4d 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2]! +0x8d 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2]! +0x03 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2], r3 +0x43 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2], r3 +0x83 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2], r3 +0x2f 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3] +0x6f 0x0d 0xa3 0xf4 +# CHECK: vld2.16 {d0[], d2[]}, [r3] +0xaf 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3] +0x2d 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3]! +0x6d 0x0d 0xa3 0xf4 +# CHECK: vld2.16 {d0[], d2[]}, [r3]! +0xad 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3]! +0x24 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3], r4 +0x64 0x0d 0xa3 0xf4 +0xa4 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3], r4 diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index f8e7dbe..65cd230 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1778,3 +1778,223 @@ # CHECK: vst4.16 {d8, d10, d12, d14}, [r4] 0x04 0xf9 0x8f 0x81 # CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x24 0xf9 0x0d 0x87 +# CHECK: vld1.8 {d8}, [r4]! +0x24 0xf9 0x4d 0x87 +# CHECK: vld1.16 {d8}, [r4]! +0x24 0xf9 0x8d 0x87 +# CHECK: vld1.32 {d8}, [r4]! +0x24 0xf9 0xcd 0x87 +# CHECK: vld1.64 {d8}, [r4]! +0x24 0xf9 0x06 0x87 +# CHECK: vld1.8 {d8}, [r4], r6 +0x24 0xf9 0x46 0x87 +# CHECK: vld1.16 {d8}, [r4], r6 +0x24 0xf9 0x86 0x87 +# CHECK: vld1.32 {d8}, [r4], r6 +0x24 0xf9 0xc6 0x87 +# CHECK: vld1.64 {d8}, [r4], r6 +0x24 0xf9 0x0d 0x8a +# CHECK: vld1.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x8a +# CHECK: vld1.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x8a +# CHECK: vld1.32 {d8, d9}, [r4]! +0x24 0xf9 0xcd 0x8a +# CHECK: vld1.64 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x8a +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x8a +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x8a +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0x24 0xf9 0xc6 0x8a +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0xcd 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x46 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x86 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0xc6 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x0d 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0xcd 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x46 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x86 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0xc6 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x89 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x24 0xf9 0x4d 0x89 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x24 0xf9 0x8d 0x89 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x24 0xf9 0x06 0x89 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x24 0xf9 0x46 0x89 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x24 0xf9 0x86 0x89 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x24 0xf9 0x0d 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x46 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x86 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x0d 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x46 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x86 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x4f 0x8a +# CHECK: vld1.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x8a +# CHECK: vld1.32 {d8, d9}, [r4] +0x24 0xf9 0xcf 0x8a +# CHECK: vld1.64 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x8a +# CHECK: vld1.8 {d8, d9}, [r4] +0x24 0xf9 0x4f 0x88 +# CHECK: vld2.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x88 +# CHECK: vld2.32 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x88 +# CHECK: vld2.8 {d8, d9}, [r4] +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x4f 0x89 +# CHECK: vld2.16 {d8, d10}, [r4] +0x24 0xf9 0x8f 0x89 +# CHECK: vld2.32 {d8, d10}, [r4] +0x24 0xf9 0x0f 0x89 +# CHECK: vld2.8 {d8, d10}, [r4] +0x24 0xf9 0x4d 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x46 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x8d 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x86 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0f 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x24 0xf9 0x4f 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x24 0xf9 0x8f 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x24 0xf9 0x0f 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x4f 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x8f 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x0f 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x24 0xf9 0x4f 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x24 0xf9 0x8f 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x24 0xf9 0x0f 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x4f 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x8f 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11256967 +0xa2 0xf9 0x0f 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2] +0xa2 0xf9 0x4f 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2] +0xa2 0xf9 0x8f 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2] +0xa2 0xf9 0x0d 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x4d 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x8d 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x03 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2], r3 +0xa2 0xf9 0x43 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2], r3 +0xa2 0xf9 0x83 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2], r3 +0xa3 0xf9 0x2f 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3] +0xa3 0xf9 0x6f 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3] +0xa3 0xf9 0xaf 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3] +0xa3 0xf9 0x2d 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3]! +0xa3 0xf9 0x6d 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3]! +0xa3 0xf9 0xad 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3]! +0xa3 0xf9 0x24 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3], r4 +0xa3 0xf9 0x64 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3], r4 +0xa3 0xf9 0xa4 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3], r4 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 0000000..275bae2 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt new file mode 100644 index 0000000..635b66e --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xd1 0xf1 0x5f 0x01 +0xd1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xd1 0xe1 0x4f 0x01 +0xd1 0xe1 0x4f 0x01 + + diff --git a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt new file mode 100644 index 0000000..dac4390 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x01 0x10 0x50 0x03 +0x01 0x10 0x50 0x03 + +# CHECK: potentially undefined +# CHECK: 0x82 0x10 0x50 0x01 +0x82 0x10 0x50 0x01 + +# CHECK: potentially undefined +# CHECK: 0x02 0x10 0x50 0x01 +0x02 0x10 0x50 0x01 + +# CHECK: potentially undefined +# CHECK: 0x1f 0x01 0x52 0x01 +0x1f 0x01 0x52 0x01 + +# CHECK: potentially undefined +# CHECK: 0x10 0x11 0x52 0x01 +0x10 0x11 0x52 0x01 + +# CHECK: potentially undefined +# CHECK: 0x10 0x0f 0x51 0x01 +0x10 0x0f 0x51 0x01 + +# CHECK: potentially undefined +# CHECK: 0x10 0x01 0x5f 0x01 +0x10 0x01 0x5f 0x01 + diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt new file mode 100644 index 0000000..ed5e350 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -0,0 +1,22 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xff 0x00 0xb9 0x00 +0xff 0x00 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0xf0 0xb9 0x00 +0xfb 0xf0 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x01 0xb9 0x00 +0xfb 0x01 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x00 0xbf 0x00 +0xfb 0x00 0xbf 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x90 0xb9 0x00 +0xfb 0x90 0xb9 0x00 + diff --git a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index f8f23ed..a8f54f7 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- @@ -7,4 +7,7 @@ # # A8.6.68 LDRD (register) # if Rt{0} = 1 then UNDEFINED; + +# CHECK: potentially undefined +# CHECK: 0xd0 0x10 0x00 0x00 0xd0 0x10 0x00 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt new file mode 100644 index 0000000..26b286d --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x00 0x10 0x51 0xfc +0x00 0x10 0x51 0xfc + +# CHECK: potentially undefined +# CHECK: 0x00 0xf0 0x41 0x0c +0x00 0xf0 0x41 0x0c + +# CHECK: potentially undefined +# CHECK: 0x00 0x00 0x4f 0x0c +0x00 0x00 0x4f 0x0c diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt new file mode 100644 index 0000000..3e472cd --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x0f 0x01 +0x00 0xf0 0x0f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x4f 0x01 +0x00 0xf0 0x4f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x01 0x01 +0x0f 0x0d 0x01 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x40 0x01 +0x0f 0x0d 0x40 0x01 + diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt new file mode 100644 index 0000000..3db86cc --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x93 0x12 0x01 0x00 +0x93 0x12 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x0f 0x01 0x00 +0x92 0x0f 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x9f 0x02 0x01 0x00 +0x9f 0x02 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x01 0x0f 0x00 +0x92 0x01 0x0f 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt new file mode 100644 index 0000000..8ec49ca --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: shadd16 r5, r7, r0 +0x10 0x51 0x37 0xe6 + + diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt new file mode 100644 index 0000000..64bb171 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt @@ -0,0 +1,26 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x9f 0x10 0x03 0x01 +0x9f 0x10 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0xf0 0x03 0x01 +0x90 0xf0 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x1f 0x03 0x01 +0x90 0x1f 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x0f 0x01 +0x90 0x10 0x0f 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x01 0x01 +0x90 0x10 0x01 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x00 0x01 +0x90 0x10 0x00 0x01 + diff --git a/test/MC/Disassembler/ARM/vfp4.txt b/test/MC/Disassembler/ARM/vfp4.txt new file mode 100644 index 0000000..4f2c732 --- /dev/null +++ b/test/MC/Disassembler/ARM/vfp4.txt @@ -0,0 +1,37 @@ +# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown --disassemble -mattr=+neon,+vfp4 | FileCheck %s + +# CHECK: vfma.f64 d16, d18, d17 +0xe2 0xee 0xa1 0x0b + +# CHECK: vfma.f32 s2, s4, s0 +0xa2 0xee 0x00 0x1a + +# CHECK: vfma.f32 d16, d18, d17 +0x42 0xef 0xb1 0x0c + +# CHECK: vfma.f32 q2, q4, q0 +0x08 0xef 0x50 0x4c + +# CHECK: vfnms.f64 d16, d18, d17 +0xd2 0xee 0xa1 0x0b + +# CHECK: vfnms.f32 s2, s4, s0 +0x92 0xee 0x00 0x1a + +# CHECK: vfms.f64 d16, d18, d17 +0xe2 0xee 0xe1 0x0b + +# CHECK: vfms.f32 s2, s4, s0 +0xa2 0xee 0x40 0x1a + +# CHECK: vfms.f32 d16, d18, d17 +0x62 0xef 0xb1 0x0c + +# CHECK: vfms.f32 q2, q4, q0 +0x28 0xef 0x50 0x4c + +# CHECK: vfnma.f64 d16, d18, d17 +0xd2 0xee 0xe1 0x0b + +# CHECK: vfnma.f32 s2, s4, s0 +0x92 0xee 0x40 0x1a diff --git a/test/MC/Disassembler/MBlaze/lit.local.cfg b/test/MC/Disassembler/MBlaze/lit.local.cfg index 766b980..3955b4e 100644 --- a/test/MC/Disassembler/MBlaze/lit.local.cfg +++ b/test/MC/Disassembler/MBlaze/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.txt'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'MBlaze' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt new file mode 100644 index 0000000..591d8c4 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -0,0 +1,421 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux + +# CHECK: abs.d $f12,$f14 +0x46 0x20 0x39 0x85 + +# CHECK: abs.s $f6,$f7 +0x46 0x00 0x39 0x85 + +# CHECK: add t1,a2,a3 +0x00 0xc7 0x48 0x20 + +# CHECK: add.d $f18,$f12,$f14 +0x46 0x27 0x32 0x40 + +# CHECK: add.s $f9,$f6,$f7 +0x46 0x07 0x32 0x40 + +# CHECK: addi t1,a2,17767 +0x20 0xc9 0x45 0x67 + +# CHECK: addiu t1,a2,-15001 +0x24 0xc9 0xc5 0x67 + +# CHECK: addu t1,a2,a3 +0x00 0xc7 0x48 0x21 + +# CHECK: and t1,a2,a3 +0x00 0xc7 0x48 0x24 + +# CHECK: andi t1,a2,0x4567 +0x30 0xc9 0x45 0x67 + +# CHECK: b 00000534 +0x10 0x00 0x01 0x4c + +# CHECK: bal 00000534 +0x04 0x11 0x01 0x4c + +# CHECK: bc1f 00000534 +0x45 0x00 0x01 0x4c + +# CHECK: bc1t 00000534 +0x45 0x01 0x01 0x4c + +# CHECK: beq t1,a2,00000534 +0x11 0x26 0x01 0x4c + +# CHECK: bgez a2,00000534 +0x04 0xc1 0x01 0x4c + +# CHECK: bgezal a2,00000534 +0x04 0xd1 0x01 0x4c + +# CHECK: bgtz a2,00000534 +0x1c 0xc0 0x01 0x4c + +# CHECK: blez a2,00000534 +0x18 0xc0 0x01 0x4c + +# CHECK: bne t1,a2,00000534 +0x15 0x26 0x01 0x4c + +# CHECK: c.eq.d $f12,$f14 +0x46 0x27 0x30 0x32 + +# CHECK: c.eq.s $f6,$f7 +0x46 0x07 0x30 0x32 + +# CHECK: c.f.d $f12,$f14 +0x46 0x27 0x30 0x30 + +# CHECK: c.f.s $f6,$f7 +0x46 0x07 0x30 0x30 + +# CHECK: c.le.d $f12,$f14 +0x46 0x27 0x30 0x3e + +# CHECK: c.le.s $f6,$f7 +0x46 0x07 0x30 0x3e + +# CHECK: c.lt.d $f12,$f14 +0x46 0x27 0x30 0x3c + +# CHECK: c.lt.s $f6,$f7 +0x46 0x07 0x30 0x3c + +# CHECK: c.nge.d $f12,$f14 +0x46 0x27 0x30 0x3d + +# CHECK: c.nge.s $f6,$f7 +0x46 0x07 0x30 0x3d + +# CHECK: c.ngl.d $f12,$f14 +0x46 0x27 0x30 0x3b + +# CHECK: c.ngl.s $f6,$f7 +0x46 0x07 0x30 0x3b + +# CHECK: c.ngle.d $f12,$f14 +0x46 0x27 0x30 0x39 + +# CHECK: c.ngle.s $f6,$f7 +0x46 0x07 0x30 0x39 + +# CHECK: c.ngt.d $f12,$f14 +0x46 0x27 0x30 0x3f + +# CHECK: c.ngt.s $f6,$f7 +0x46 0x07 0x30 0x3f + +# CHECK: c.ole.d $f12,$f14 +0x46 0x27 0x30 0x36 + +# CHECK: c.ole.s $f6,$f7 +0x46 0x07 0x30 0x36 + +# CHECK: c.olt.d $f12,$f14 +0x46 0x27 0x30 0x34 + +# CHECK: c.olt.s $f6,$f7 +0x46 0x07 0x30 0x34 + +# CHECK: c.seq.d $f12,$f14 +0x46 0x27 0x30 0x3a + +# CHECK: c.seq.s $f6,$f7 +0x46 0x07 0x30 0x3a + +# CHECK: c.sf.d $f12,$f14 +0x46 0x27 0x30 0x38 + +# CHECK: c.sf.s $f6,$f7 +0x46 0x07 0x30 0x38 + +# CHECK: c.ueq.d $f12,$f14 +0x46 0x27 0x30 0x33 + +# CHECK: c.ueq.s $f28,$f18 +0x46 0x12 0xe0 0x33 + +# CHECK: c.ule.d $f12,$f14 +0x46 0x27 0x30 0x37 + +# CHECK: c.ule.s $f6,$f7 +0x46 0x07 0x30 0x37 + +# CHECK: c.ult.d $f12,$f14 +0x46 0x27 0x30 0x35 + +# CHECK: c.ult.s $f6,$f7 +0x46 0x07 0x30 0x35 + +# CHECK: c.un.d $f12,$f14 +0x46 0x27 0x30 0x31 + +# CHECK: c.un.s $f6,$f7 +0x46 0x07 0x30 0x31 + +# CHECK: ceil.w.d $f12,$f14 +0x46 0x20 0x39 0x8e + +# CHECK: ceil.w.s $f6,$f7 +0x46 0x00 0x39 0x8e + +# CHECK: cfc1 a2,$7 +0x44 0x46 0x38 0x00 + +# CHECK: clo a2,a3 +0x70 0xe6 0x30 0x21 + +# CHECK: clz a2,a3 +0x70 0xe6 0x30 0x20 + +# CHECK: ctc1 a2,$7 +0x44 0xc6 0x38 0x00 + +# CHECK: cvt.d.s $f6,$f7 +0x46 0x00 0x38 0xa1 + +# CHECK: cvt.d.w $f12,$f14 +0x46 0x80 0x38 0xa1 + +# CHECK: cvt.l.d $f12,$f14 +0x46 0x20 0x39 0xa5 + +# CHECK: cvt.l.s $f6,$f7 +0x46 0x00 0x39 0xa5 + +# CHECK: cvt.s.d $f12,$f14 +0x46 0x20 0x39 0xa0 + +# CHECK: cvt.s.w $f6,$f7 +0x46 0x80 0x39 0xa0 + +# CHECK: cvt.w.d $f12,$f14 +0x46 0x20 0x39 0xa4 + +# CHECK: cvt.w.s $f6,$f7 +0x46 0x00 0x39 0xa4 + +# CHECK: floor.w.d $f12,$f14 +0x46 0x20 0x39 0x8f + +# CHECK: floor.w.s $f6,$f7 +0x46 0x00 0x39 0x8f + +# CHECK: j 00000530 +0x08 0x00 0x01 0x4c + +# CHECK: jal 00000530 +0x0c 0x00 0x01 0x4c + +# CHECK: jalr a2,a3 +0x00 0xe0 0xf8 0x09 + +# CHECK: jr a3 +0x00 0xe0 0x00 0x08 + +# CHECK: lb a0,9158(a1) +0x80 0xa4 0x23 0xc6 + +# CHECK: lbu a0,6(a1) +0x90 0xa4 0x00 0x06 + +# CHECK: ldc1 $f9,9158(a3) +0xd4 0xe9 0x23 0xc6 + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: li v1,17767 +0x24 0x03 0x45 0x67 + +# CHECK: ll t1,9158(a3) +0xc0 0xe9 0x23 0xc6 + +# CHECK: lui a2,0x4567 +0x3c 0x06 0x45 0x67 + +# CHECK: lw a0,24(a1) +0x8c 0xa4 0x00 0x18 + +# CHECK: lwc1 $f9,9158(a3) +0xc4 0xe9 0x23 0xc6 + +# CHECK: madd a2,a3 +0x70 0xc7 0x00 0x00 + +# CHECK: maddu a2,a3 +0x70 0xc7 0x00 0x01 + +# CHECK: mfc1 a2,$f7 +0x44 0x06 0x38 0x00 + +# CHECK: mfhi a1 +0x00 0x00 0x28 0x10 + +# CHECK: mflo a1 +0x00 0x00 0x28 0x12 + +# CHECK: mov.d $f6,$f7 +0x46 0x20 0x39 0x86 + +# CHECK: mov.s $f6,$f7 +0x46 0x00 0x39 0x86 + +# CHECK: move a2,a1 +0x00 0xa0 0x30 0x21 + +# CHECK: msub a2,a3 +0x70 0xc7 0x00 0x04 + +# CHECK: msubu a2,a3 +0x70 0xc7 0x00 0x05 + +# CHECK: mtc1 a2,$f7 +0x44 0x86 0x38 0x00 + +# CHECK: mthi a3 +0x00 0xe0 0x00 0x11 + +# CHECK: mtlo a3 +0x00 0xe0 0x00 0x13 + +# CHECK: mul.d $f9,$f12,$f14 +0x46 0x27 0x32 0x42 + +# CHECK: mul.s $f9,$f6,$f7 +0x46 0x07 0x32 0x42 + +# CHECK: mul t1,a2,a3 +0x70 0xc7 0x48 0x02 + +# CHECK: mult v1,a1 +0x00 0x65 0x00 0x18 + +# CHECK: multu v1,a1 +0x00 0x65 0x00 0x19 + +# CHECK: neg.d $f12,$f14 +0x46 0x20 0x39 0x87 + +# CHECK: neg.s $f6,$f7 +0x46 0x00 0x39 0x87 + +# CHECK: neg v1,a1 +0x00 0x05 0x18 0x22 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x00 0xc7 0x48 0x27 + +# CHECK: not v1,a1 +0x00 0xa0 0x18 0x27 + +# CHECK: or v1,v1,a1 +0x00 0x65 0x18 0x25 + +# CHECK: ori t1,a2,0x4567 +0x34 0xc9 0x45 0x67 + +# CHECK: rdhwr a2,$29 +0x7c 0x06 0xe8 0x3b + +# CHECK: round.w.d $f12,$f14 +0x46 0x20 0x39 0x8c + +# CHECK: round.w.s $f6,$f7 +0x46 0x00 0x39 0x8c + +# CHECK: sb a0,9158(a1) +0xa0 0xa4 0x23 0xc6 + +# CHECK: sb a0,6(a1) +0xa0 0xa4 0x00 0x06 + +# CHECK: sc t1,9158(a3) +0xe0 0xe9 0x23 0xc6 + +# CHECK: sdc1 $f9,9158(a3) +0xf4 0xe9 0x23 0xc6 + +# CHECK: sh a0,9158(a1) +0xa4 0xa4 0x23 0xc6 + +# CHECK: sll a0,v1,0x7 +0x00 0x03 0x21 0xc0 + +# CHECK: sllv v0,v1,a1 +0x00 0xa3 0x10 0x04 + +# CHECK: slt v1,v1,a1 +0x00 0x65 0x18 0x2a + +# CHECK: slti v1,v1,103 +0x28 0x63 0x00 0x67 + +# CHECK: sltiu v1,v1,103 +0x2c 0x63 0x00 0x67 + +# CHECK: sltu v1,v1,a1 +0x00 0x65 0x18 0x2b + +# CHECK: sqrt.d $f12,$f14 +0x46 0x20 0x39 0x84 + +# CHECK: sqrt.s $f6,$f7 +0x46 0x00 0x39 0x84 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: srav v0,v1,a1 +0x00 0xa3 0x10 0x07 + +# CHECK: srl a0,v1,0x7 +0x00 0x03 0x21 0xc2 + +# CHECK: srlv v0,v1,a1 +0x00 0xa3 0x10 0x06 + +# CHECK: sub.d $f9,$f12,$f14 +0x46 0x27 0x32 0x41 + +# CHECK: sub.s $f9,$f6,$f7 +0x46 0x07 0x32 0x41 + +# CHECK: sub t1,a2,a3 +0x00 0xc7 0x48 0x22 + +# CHECK: subu a0,v1,a1 +0x00 0x65 0x20 0x23 + +# CHECK: sw a0,24(a1) +0xac 0xa4 0x00 0x18 + +# CHECK: swc1 $f9,9158(a3) +0xe4 0xe9 0x23 0xc6 + +# CHECK: sync 0x7 +0x00 0x00 0x01 0xcf + +# CHECK: trunc.w.d $f12,$f14 +0x46 0x20 0x39 0x8d + +# CHECK: trunc.w.s $f6,$f7 +0x46 0x00 0x39 0x8d + +# CHECK: xor v1,v1,a1 +0x00 0x65 0x18 0x26 + +# CHECK: xori t1,a2,0x4567 +0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt new file mode 100644 index 0000000..a5a3cfd --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -0,0 +1,424 @@ +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux + +# CHECK: abs.d $f12,$f14 +0x85 0x39 0x20 0x46 + +# CHECK: abs.s $f6,$f7 +0x85 0x39 0x00 0x46 + +# CHECK: add t1,a2,a3 +0x20 0x48 0xc7 0x00 + +# CHECK: add.d $f18,$f12,$f14 +0x40 0x32 0x27 0x46 + +# CHECK: add.s $f9,$f6,$f7 +0x40 0x32 0x07 0x46 + +# CHECK: addi t1,a2,17767 +0x67 0x45 0xc9 0x20 + +# CHECK: addiu t1,a2,-15001 +0x67 0xc5 0xc9 0x24 + +# CHECK: addu t1,a2,a3 +0x21 0x48 0xc7 0x00 + +# CHECK: and t1,a2,a3 +0x24 0x48 0xc7 0x00 + +# CHECK: andi t1,a2,0x4567 +0x67 0x45 0xc9 0x30 + +# CHECK: b 00000534 +0x4c 0x01 0x00 0x10 + +# CHECK: bal 00000534 +0x4c 0x01 0x11 0x04 + +# CHECK: bc1f 00000534 +0x4c 0x01 0x00 0x45 + +# CHECK: bc1t 00000534 +0x4c 0x01 0x01 0x45 + +# CHECK: beq t1,a2,00000534 +0x4c 0x01 0x26 0x11 + +# CHECK: bgez a2,00000534 +0x4c 0x01 0xc1 0x04 + +# CHECK: bgezal a2,00000534 +0x4c 0x01 0xd1 0x04 + +# CHECK: bgtz a2,00000534 +0x4c 0x01 0xc0 0x1c + +# CHECK: blez a2,00000534 +0x4c 0x01 0xc0 0x18 + +# CHECK: bne t1,a2,00000534 +0x4c 0x01 0x26 0x15 + +# CHECK: c.eq.d $f12,$f14 +0x32 0x30 0x27 0x46 + +# CHECK: c.eq.s $f6,$f7 +0x32 0x30 0x07 0x46 + +# CHECK: c.f.d $f12,$f14 +0x30 0x30 0x27 0x46 + +# CHECK: c.f.s $f6,$f7 +0x30 0x30 0x07 0x46 + +# CHECK: c.le.d $f12,$f14 +0x3e 0x30 0x27 0x46 + +# CHECK: c.le.s $f6,$f7 +0x3e 0x30 0x07 0x46 + +# CHECK: c.lt.d $f12,$f14 +0x3c 0x30 0x27 0x46 + +# CHECK: c.lt.s $f6,$f7 +0x3c 0x30 0x07 0x46 + +# CHECK: c.nge.d $f12,$f14 +0x3d 0x30 0x27 0x46 + +# CHECK: c.nge.s $f6,$f7 +0x3d 0x30 0x07 0x46 + +# CHECK: c.ngl.d $f12,$f14 +0x3b 0x30 0x27 0x46 + +# CHECK: c.ngl.s $f6,$f7 +0x3b 0x30 0x07 0x46 + +# CHECK: c.ngle.d $f12,$f14 +0x39 0x30 0x27 0x46 + +# CHECK: c.ngle.s $f6,$f7 +0x39 0x30 0x07 0x46 + +# CHECK: c.ngt.d $f12,$f14 +0x3f 0x30 0x27 0x46 + +# CHECK: c.ngt.s $f6,$f7 +0x3f 0x30 0x07 0x46 + +# CHECK: c.ole.d $f12,$f14 +0x36 0x30 0x27 0x46 + +# CHECK: c.ole.s $f6,$f7 +0x36 0x30 0x07 0x46 + +# CHECK: c.olt.d $f12,$f14 +0x34 0x30 0x27 0x46 + +# CHECK: c.olt.s $f6,$f7 +0x34 0x30 0x07 0x46 + +# CHECK: c.seq.d $f12,$f14 +0x3a 0x30 0x27 0x46 + +# CHECK: c.seq.s $f6,$f7 +0x3a 0x30 0x07 0x46 + +# CHECK: c.sf.d $f12,$f14 +0x38 0x30 0x27 0x46 + +# CHECK: c.sf.s $f6,$f7 +0x38 0x30 0x07 0x46 + +# CHECK: c.ueq.d $f12,$f14 +0x33 0x30 0x27 0x46 + +# CHECK: c.ueq.s $f28,$f18 +0x33 0xe0 0x12 0x46 + +# CHECK: c.ule.d $f12,$f14 +0x37 0x30 0x27 0x46 + +# CHECK: c.ule.s $f6,$f7 +0x37 0x30 0x07 0x46 + +# CHECK: c.ult.d $f12,$f14 +0x35 0x30 0x27 0x46 + +# CHECK: c.ult.s $f6,$f7 +0x35 0x30 0x07 0x46 + +# CHECK: c.un.d $f12,$f14 +0x31 0x30 0x27 0x46 + +# CHECK: c.un.s $f6,$f7 +0x31 0x30 0x07 0x46 + +# CHECK: ceil.w.d $f12,$f14 +0x8e 0x38 0x20 0x46 + +# CHECK: ceil.w.s $f6,$f7 +0x8e 0x38 0x00 0x46 + +# CHECK: cfc1 a2,$7 +0x00 0x38 0x46 0x44 + +# CHECK: clo a2,a3 +0x21 0x30 0xe6 0x70 + +# CHECK: clz a2,a3 +0x20 0x30 0xe6 0x70 + +# CHECK: ctc1 a2,$7 +0x00 0x38 0xc6 0x44 + +# CHECK: cvt.d.s $f6,$f7 +0xa1 0x39 0x00 0x46 + +# CHECK: cvt.d.w $f12,$f14 +0xa1 0x39 0x80 0x46 + +# CHECK: cvt.l.d $f12,$f14 +0xa5 0x39 0x20 0x46 + +# CHECK: cvt.l.s $f6,$f7 +0xa5 0x39 0x00 0x46 + +# CHECK: cvt.s.d $f12,$f14 +0xa0 0x39 0x20 0x46 + +# CHECK: cvt.s.w $f6,$f7 +0xa0 0x39 0x80 0x46 + +# CHECK: cvt.w.d $f12,$f14 +0xa4 0x39 0x20 0x46 + +# CHECK: cvt.w.s $f6,$f7 +0xa4 0x39 0x00 0x46 + +# CHECK: floor.w.d $f12,$f14 +0x8f 0x39 0x20 0x46 + +# CHECK: floor.w.s $f6,$f7 +0x8f 0x39 0x00 0x46 + +# CHECK: j 00000530 +0x4c 0x01 0x00 0x08 + +# CHECK: jal 00000530 +0x4c 0x01 0x00 0x0c + +# CHECK: jalr a2,a3 +0x09 0xf8 0xe0 0x00 + +# CHECK: jr a3 +0x08 0x00 0xe0 0x00 + +# CHECK: lb a0,9158(a1) +0xc6 0x23 0xa4 0x80 + +# CHECK: lbu a0,6(a1) +0x06 0x00 0xa4 0x90 + +# CHECK: ldc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xd4 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: li v1,17767 +0x67 0x45 0x03 0x24 + +# CHECK: ll t1,9158(a3) +0xc6 0x23 0xe9 0xc0 + +# CHECK: lui a2,0x4567 +0x67 0x45 0x06 0x3c + +# CHECK: lw a0,24(a1) +0x18 0x00 0xa4 0x8c + +# CHECK lw at,-18316(v0) +0x74 0xb8 0x41 0x8c + +# CHECK: lwc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xc4 + +# CHECK: madd a2,a3 +0x00 0x00 0xc7 0x70 + +# CHECK: maddu a2,a3 +0x01 0x00 0xc7 0x70 + +# CHECK: mfc1 a2,$f7 +0x00 0x38 0x06 0x44 + +# CHECK: mfhi a1 +0x10 0x28 0x00 0x00 + +# CHECK: mflo a1 +0x12 0x28 0x00 0x00 + +# CHECK: mov.d $f12,$f14 +0x86 0x39 0x20 0x46 + +# CHECK: mov.s $f6,$f7 +0x86 0x39 0x00 0x46 + +# CHECK: move a2,a1 +0x21 0x30 0xa0 0x00 + +# CHECK: msub a2,a3 +0x04 0x00 0xc7 0x70 + +# CHECK: msubu a2,a3 +0x05 0x00 0xc7 0x70 + +# CHECK: mtc1 a2,$f7 +0x00 0x38 0x86 0x44 + +# CHECK: mthi a3 +0x11 0x00 0xe0 0x00 + +# CHECK: mtlo a3 +0x13 0x00 0xe0 0x00 + +# CHECK: mul.d $f9,$f12,$f14 +0x42 0x32 0x27 0x46 + +# CHECK: mul.s $f9,$f6,$f7 +0x42 0x32 0x07 0x46 + +# CHECK: mul t1,a2,a3 +0x02 0x48 0xc7 0x70 + +# CHECK: mult v1,a1 +0x18 0x00 0x65 0x00 + +# CHECK: multu v1,a1 +0x19 0x00 0x65 0x00 + +# CHECK: neg.d $f12,$f14 +0x87 0x39 0x20 0x46 + +# CHECK: neg.s $f6,$f7 +0x87 0x39 0x00 0x46 + +# CHECK: neg v1,a1 +0x22 0x18 0x05 0x00 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x27 0x48 0xc7 0x00 + +# CHECK: not v1,a1 +0x27 0x18 0xa0 0x00 + +# CHECK: or v1,v1,a1 +0x25 0x18 0x65 0x00 + +# CHECK: ori t1,a2,0x4567 +0x67 0x45 0xc9 0x34 + +# CHECK: rdhwr a2,$29 +0x3b 0xe8 0x06 0x7c + +# CHECK: round.w.d $f12,$f14 +0x8c 0x39 0x20 0x46 + +# CHECK: round.w.s $f6,$f7 +0x8c 0x39 0x00 0x46 + +# CHECK: sb a0,9158(a1) +0xc6 0x23 0xa4 0xa0 + +# CHECK: sb a0,6(a1) +0x06 0x00 0xa4 0xa0 + +# CHECK: sc t1,9158(a3) +0xc6 0x23 0xe9 0xe0 + +# CHECK: sdc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xf4 + +# CHECK: sh a0,9158(a1) +0xc6 0x23 0xa4 0xa4 + +# CHECK: sll a0,v1,0x7 +0xc0 0x21 0x03 0x00 + +# CHECK: sllv v0,v1,a1 +0x04 0x10 0xa3 0x00 + +# CHECK: slt v1,v1,a1 +0x2a 0x18 0x65 0x00 + +# CHECK: slti v1,v1,103 +0x67 0x00 0x63 0x28 + +# CHECK: sltiu v1,v1,103 +0x67 0x00 0x63 0x2c + +# CHECK: sltu v1,v1,a1 +0x2b 0x18 0x65 0x00 + +# CHECK: sqrt.d $f12,$f14 +0x84 0x39 0x20 0x46 + +# CHECK: sqrt.s $f6,$f7 +0x84 0x39 0x00 0x46 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: srav v0,v1,a1 +0x07 0x10 0xa3 0x00 + +# CHECK: srl a0,v1,0x7 +0xc2 0x21 0x03 0x00 + +# CHECK: srlv v0,v1,a1 +0x06 0x10 0xa3 0x00 + +# CHECK: sub.d $f9,$f12,$f14 +0x41 0x32 0x27 0x46 + +# CHECK: sub.s $f9,$f6,$f7 +0x41 0x32 0x07 0x46 + +# CHECK: sub t1,a2,a3 +0x22 0x48 0xc7 0x00 + +# CHECK: subu a0,v1,a1 +0x23 0x20 0x65 0x00 + +# CHECK: sw a0,24(a1) +0x18 0x00 0xa4 0xac + +# CHECK: swc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xe4 + +# CHECK: sync 0x7 +0xcf 0x01 0x00 0x00 + +# CHECK: trunc.w.d $f12,$f14 +0x8d 0x39 0x20 0x46 + +# CHECK: trunc.w.s $f6,$f7 +0x8d 0x39 0x00 0x46 + +# CHECK: xor v1,v1,a1 +0x26 0x18 0x65 0x00 + +# CHECK: xori t1,a2,0x4567 +0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt new file mode 100644 index 0000000..295ffd0 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -0,0 +1,439 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 + +# CHECK: abs.d $f12,$f14 +0x46 0x20 0x39 0x85 + +# CHECK: abs.s $f6,$f7 +0x46 0x00 0x39 0x85 + +# CHECK: add t1,a2,a3 +0x00 0xc7 0x48 0x20 + +# CHECK: add.d $f18,$f12,$f14 +0x46 0x27 0x32 0x40 + +# CHECK: add.s $f9,$f6,$f7 +0x46 0x07 0x32 0x40 + +# CHECK: addi t1,a2,17767 +0x20 0xc9 0x45 0x67 + +# CHECK: addiu t1,a2,-15001 +0x24 0xc9 0xc5 0x67 + +# CHECK: addu t1,a2,a3 +0x00 0xc7 0x48 0x21 + +# CHECK: and t1,a2,a3 +0x00 0xc7 0x48 0x24 + +# CHECK: andi t1,a2,0x4567 +0x30 0xc9 0x45 0x67 + +# CHECK: b 00000534 +0x10 0x00 0x01 0x4c + +# CHECK: bal 00000534 +0x04 0x11 0x01 0x4c + +# CHECK: bc1f 00000534 +0x45 0x00 0x01 0x4c + +# CHECK: bc1t 00000534 +0x45 0x01 0x01 0x4c + +# CHECK: beq t1,a2,00000534 +0x11 0x26 0x01 0x4c + +# CHECK: bgez a2,00000534 +0x04 0xc1 0x01 0x4c + +# CHECK: bgezal a2,00000534 +0x04 0xd1 0x01 0x4c + +# CHECK: bgtz a2,00000534 +0x1c 0xc0 0x01 0x4c + +# CHECK: blez a2,00000534 +0x18 0xc0 0x01 0x4c + +# CHECK: bne t1,a2,00000534 +0x15 0x26 0x01 0x4c + +# CHECK: c.eq.d $f12,$f14 +0x46 0x27 0x30 0x32 + +# CHECK: c.eq.s $f6,$f7 +0x46 0x07 0x30 0x32 + +# CHECK: c.f.d $f12,$f14 +0x46 0x27 0x30 0x30 + +# CHECK: c.f.s $f6,$f7 +0x46 0x07 0x30 0x30 + +# CHECK: c.le.d $f12,$f14 +0x46 0x27 0x30 0x3e + +# CHECK: c.le.s $f6,$f7 +0x46 0x07 0x30 0x3e + +# CHECK: c.lt.d $f12,$f14 +0x46 0x27 0x30 0x3c + +# CHECK: c.lt.s $f6,$f7 +0x46 0x07 0x30 0x3c + +# CHECK: c.nge.d $f12,$f14 +0x46 0x27 0x30 0x3d + +# CHECK: c.nge.s $f6,$f7 +0x46 0x07 0x30 0x3d + +# CHECK: c.ngl.d $f12,$f14 +0x46 0x27 0x30 0x3b + +# CHECK: c.ngl.s $f6,$f7 +0x46 0x07 0x30 0x3b + +# CHECK: c.ngle.d $f12,$f14 +0x46 0x27 0x30 0x39 + +# CHECK: c.ngle.s $f6,$f7 +0x46 0x07 0x30 0x39 + +# CHECK: c.ngt.d $f12,$f14 +0x46 0x27 0x30 0x3f + +# CHECK: c.ngt.s $f6,$f7 +0x46 0x07 0x30 0x3f + +# CHECK: c.ole.d $f12,$f14 +0x46 0x27 0x30 0x36 + +# CHECK: c.ole.s $f6,$f7 +0x46 0x07 0x30 0x36 + +# CHECK: c.olt.d $f12,$f14 +0x46 0x27 0x30 0x34 + +# CHECK: c.olt.s $f6,$f7 +0x46 0x07 0x30 0x34 + +# CHECK: c.seq.d $f12,$f14 +0x46 0x27 0x30 0x3a + +# CHECK: c.seq.s $f6,$f7 +0x46 0x07 0x30 0x3a + +# CHECK: c.sf.d $f12,$f14 +0x46 0x27 0x30 0x38 + +# CHECK: c.sf.s $f6,$f7 +0x46 0x07 0x30 0x38 + +# CHECK: c.ueq.d $f12,$f14 +0x46 0x27 0x30 0x33 + +# CHECK: c.ueq.s $f28,$f18 +0x46 0x12 0xe0 0x33 + +# CHECK: c.ule.d $f12,$f14 +0x46 0x27 0x30 0x37 + +# CHECK: c.ule.s $f6,$f7 +0x46 0x07 0x30 0x37 + +# CHECK: c.ult.d $f12,$f14 +0x46 0x27 0x30 0x35 + +# CHECK: c.ult.s $f6,$f7 +0x46 0x07 0x30 0x35 + +# CHECK: c.un.d $f12,$f14 +0x46 0x27 0x30 0x31 + +# CHECK: c.un.s $f6,$f7 +0x46 0x07 0x30 0x31 + +# CHECK: ceil.w.d $f12,$f14 +0x46 0x20 0x39 0x8e + +# CHECK: ceil.w.s $f6,$f7 +0x46 0x00 0x39 0x8e + +# CHECK: cfc1 a2,$7 +0x44 0x46 0x38 0x00 + +# CHECK: clo a2,a3 +0x70 0xe6 0x30 0x21 + +# CHECK: clz a2,a3 +0x70 0xe6 0x30 0x20 + +# CHECK: ctc1 a2,$7 +0x44 0xc6 0x38 0x00 + +# CHECK: cvt.d.s $f6,$f7 +0x46 0x00 0x38 0xa1 + +# CHECK: cvt.d.w $f12,$f14 +0x46 0x80 0x38 0xa1 + +# CHECK: cvt.l.d $f12,$f14 +0x46 0x20 0x39 0xa5 + +# CHECK: cvt.l.s $f6,$f7 +0x46 0x00 0x39 0xa5 + +# CHECK: cvt.s.d $f12,$f14 +0x46 0x20 0x39 0xa0 + +# CHECK: cvt.s.w $f6,$f7 +0x46 0x80 0x39 0xa0 + +# CHECK: cvt.w.d $f12,$f14 +0x46 0x20 0x39 0xa4 + +# CHECK: cvt.w.s $f6,$f7 +0x46 0x00 0x39 0xa4 + +# CHECK: floor.w.d $f12,$f14 +0x46 0x20 0x39 0x8f + +# CHECK: floor.w.s $f6,$f7 +0x46 0x00 0x39 0x8f + +# CHECK: ins s3,t1,0x6,0x7 +0x7d 0x33 0x61 0x84 + +# CHECK: j 00000530 +0x08 0x00 0x01 0x4c + +# CHECK: jal 00000530 +0x0c 0x00 0x01 0x4c + +# CHECK: jalr a2,a3 +0x00 0xe0 0xf8 0x09 + +# CHECK: jr a3 +0x00 0xe0 0x00 0x08 + +# CHECK: lb a0,9158(a1) +0x80 0xa4 0x23 0xc6 + +# CHECK: lbu a0,6(a1) +0x90 0xa4 0x00 0x06 + +# CHECK: ldc1 $f9,9158(a3) +0xd4 0xe9 0x23 0xc6 + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: li v1,17767 +0x24 0x03 0x45 0x67 + +# CHECK: ll t1,9158(a3) +0xc0 0xe9 0x23 0xc6 + +# CHECK: lui a2,0x4567 +0x3c 0x06 0x45 0x67 + +# CHECK: lw a0,24(a1) +0x8c 0xa4 0x00 0x18 + +# CHECK: lwc1 $f9,9158(a3) +0xc4 0xe9 0x23 0xc6 + +# CHECK: madd a2,a3 +0x70 0xc7 0x00 0x00 + +# CHECK: maddu a2,a3 +0x70 0xc7 0x00 0x01 + +# CHECK: mfc1 a2,$f7 +0x44 0x06 0x38 0x00 + +# CHECK: mfhi a1 +0x00 0x00 0x28 0x10 + +# CHECK: mflo a1 +0x00 0x00 0x28 0x12 + +# CHECK: mov.d $f6,$f7 +0x46 0x20 0x39 0x86 + +# CHECK: mov.s $f6,$f7 +0x46 0x00 0x39 0x86 + +# CHECK: move a2,a1 +0x00 0xa0 0x30 0x21 + +# CHECK: msub a2,a3 +0x70 0xc7 0x00 0x04 + +# CHECK: msubu a2,a3 +0x70 0xc7 0x00 0x05 + +# CHECK: mtc1 a2,$f7 +0x44 0x86 0x38 0x00 + +# CHECK: mthi a3 +0x00 0xe0 0x00 0x11 + +# CHECK: mtlo a3 +0x00 0xe0 0x00 0x13 + +# CHECK: mul.d $f9,$f12,$f14 +0x46 0x27 0x32 0x42 + +# CHECK: mul.s $f9,$f6,$f7 +0x46 0x07 0x32 0x42 + +# CHECK: mul t1,a2,a3 +0x70 0xc7 0x48 0x02 + +# CHECK: mult v1,a1 +0x00 0x65 0x00 0x18 + +# CHECK: multu v1,a1 +0x00 0x65 0x00 0x19 + +# CHECK: neg.d $f12,$f14 +0x46 0x20 0x39 0x87 + +# CHECK: neg.s $f6,$f7 +0x46 0x00 0x39 0x87 + +# CHECK: neg v1,a1 +0x00 0x05 0x18 0x22 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x00 0xc7 0x48 0x27 + +# CHECK: not v1,a1 +0x00 0xa0 0x18 0x27 + +# CHECK: or v1,v1,a1 +0x00 0x65 0x18 0x25 + +# CHECK: ori t1,a2,0x4567 +0x34 0xc9 0x45 0x67 + +# CHECK: rdhwr a2,$29 +0x7c 0x06 0xe8 0x3b + +# CHECK: ror t1,a2,0x7 +0x00 0x26 0x49 0xc2 + +# CHECK: rorv t1,a2,a3 +0x00 0xe6 0x48 0x46 + +# CHECK: round.w.d $f12,$f14 +0x46 0x20 0x39 0x8c + +# CHECK: round.w.s $f6,$f7 +0x46 0x00 0x39 0x8c + +# CHECK: sb a0,9158(a1) +0xa0 0xa4 0x23 0xc6 + +# CHECK: sb a0,6(a1) +0xa0 0xa4 0x00 0x06 + +# CHECK: sc t1,9158(a3) +0xe0 0xe9 0x23 0xc6 + +# CHECK: sdc1 $f9,9158(a3) +0xf4 0xe9 0x23 0xc6 + +# CHECK: seb a2,a3 +0x7c 0x07 0x34 0x20 + +# CHECK: seh a2,a3 +0x7c 0x07 0x36 0x20 + +# CHECK: sh a0,9158(a1) +0xa4 0xa4 0x23 0xc6 + +# CHECK: sll a0,v1,0x7 +0x00 0x03 0x21 0xc0 + +# CHECK: sllv v0,v1,a1 +0x00 0xa3 0x10 0x04 + +# CHECK: slt v1,v1,a1 +0x00 0x65 0x18 0x2a + +# CHECK: slti v1,v1,103 +0x28 0x63 0x00 0x67 + +# CHECK: sltiu v1,v1,103 +0x2c 0x63 0x00 0x67 + +# CHECK: sltu v1,v1,a1 +0x00 0x65 0x18 0x2b + +# CHECK: sqrt.d $f12,$f14 +0x46 0x20 0x39 0x84 + +# CHECK: sqrt.s $f6,$f7 +0x46 0x00 0x39 0x84 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: srav v0,v1,a1 +0x00 0xa3 0x10 0x07 + +# CHECK: srl a0,v1,0x7 +0x00 0x03 0x21 0xc2 + +# CHECK: srlv v0,v1,a1 +0x00 0xa3 0x10 0x06 + +# CHECK: sub.d $f9,$f12,$f14 +0x46 0x27 0x32 0x41 + +# CHECK: sub.s $f9,$f6,$f7 +0x46 0x07 0x32 0x41 + +# CHECK: sub t1,a2,a3 +0x00 0xc7 0x48 0x22 + +# CHECK: subu a0,v1,a1 +0x00 0x65 0x20 0x23 + +# CHECK: sw a0,24(a1) +0xac 0xa4 0x00 0x18 + +# CHECK: swc1 $f9,9158(a3) +0xe4 0xe9 0x23 0xc6 + +# CHECK: sync 0x7 +0x00 0x00 0x01 0xcf + +# CHECK: trunc.w.d $f12,$f14 +0x46 0x20 0x39 0x8d + +# CHECK: trunc.w.s $f6,$f7 +0x46 0x00 0x39 0x8d + +# CHECK: wsbh a2,a3 +0x7c 0x07 0x30 0xa0 + +# CHECK: xor v1,v1,a1 +0x00 0x65 0x18 0x26 + +# CHECK: xori t1,a2,0x4567 +0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt new file mode 100644 index 0000000..6d8be79 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -0,0 +1,442 @@ +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 + +# CHECK: abs.d $f12,$f14 +0x85 0x39 0x20 0x46 + +# CHECK: abs.s $f6,$f7 +0x85 0x39 0x00 0x46 + +# CHECK: add t1,a2,a3 +0x20 0x48 0xc7 0x00 + +# CHECK: add.d $f18,$f12,$f14 +0x40 0x32 0x27 0x46 + +# CHECK: add.s $f9,$f6,$f7 +0x40 0x32 0x07 0x46 + +# CHECK: addi t1,a2,17767 +0x67 0x45 0xc9 0x20 + +# CHECK: addiu t1,a2,-15001 +0x67 0xc5 0xc9 0x24 + +# CHECK: addu t1,a2,a3 +0x21 0x48 0xc7 0x00 + +# CHECK: and t1,a2,a3 +0x24 0x48 0xc7 0x00 + +# CHECK: andi t1,a2,0x4567 +0x67 0x45 0xc9 0x30 + +# CHECK: b 00000534 +0x4c 0x01 0x00 0x10 + +# CHECK: bal 00000534 +0x4c 0x01 0x11 0x04 + +# CHECK: bc1f 00000534 +0x4c 0x01 0x00 0x45 + +# CHECK: bc1t 00000534 +0x4c 0x01 0x01 0x45 + +# CHECK: beq t1,a2,00000534 +0x4c 0x01 0x26 0x11 + +# CHECK: bgez a2,00000534 +0x4c 0x01 0xc1 0x04 + +# CHECK: bgezal a2,00000534 +0x4c 0x01 0xd1 0x04 + +# CHECK: bgtz a2,00000534 +0x4c 0x01 0xc0 0x1c + +# CHECK: blez a2,00000534 +0x4c 0x01 0xc0 0x18 + +# CHECK: bne t1,a2,00000534 +0x4c 0x01 0x26 0x15 + +# CHECK: c.eq.d $f12,$f14 +0x32 0x30 0x27 0x46 + +# CHECK: c.eq.s $f6,$f7 +0x32 0x30 0x07 0x46 + +# CHECK: c.f.d $f12,$f14 +0x30 0x30 0x27 0x46 + +# CHECK: c.f.s $f6,$f7 +0x30 0x30 0x07 0x46 + +# CHECK: c.le.d $f12,$f14 +0x3e 0x30 0x27 0x46 + +# CHECK: c.le.s $f6,$f7 +0x3e 0x30 0x07 0x46 + +# CHECK: c.lt.d $f12,$f14 +0x3c 0x30 0x27 0x46 + +# CHECK: c.lt.s $f6,$f7 +0x3c 0x30 0x07 0x46 + +# CHECK: c.nge.d $f12,$f14 +0x3d 0x30 0x27 0x46 + +# CHECK: c.nge.s $f6,$f7 +0x3d 0x30 0x07 0x46 + +# CHECK: c.ngl.d $f12,$f14 +0x3b 0x30 0x27 0x46 + +# CHECK: c.ngl.s $f6,$f7 +0x3b 0x30 0x07 0x46 + +# CHECK: c.ngle.d $f12,$f14 +0x39 0x30 0x27 0x46 + +# CHECK: c.ngle.s $f6,$f7 +0x39 0x30 0x07 0x46 + +# CHECK: c.ngt.d $f12,$f14 +0x3f 0x30 0x27 0x46 + +# CHECK: c.ngt.s $f6,$f7 +0x3f 0x30 0x07 0x46 + +# CHECK: c.ole.d $f12,$f14 +0x36 0x30 0x27 0x46 + +# CHECK: c.ole.s $f6,$f7 +0x36 0x30 0x07 0x46 + +# CHECK: c.olt.d $f12,$f14 +0x34 0x30 0x27 0x46 + +# CHECK: c.olt.s $f6,$f7 +0x34 0x30 0x07 0x46 + +# CHECK: c.seq.d $f12,$f14 +0x3a 0x30 0x27 0x46 + +# CHECK: c.seq.s $f6,$f7 +0x3a 0x30 0x07 0x46 + +# CHECK: c.sf.d $f12,$f14 +0x38 0x30 0x27 0x46 + +# CHECK: c.sf.s $f6,$f7 +0x38 0x30 0x07 0x46 + +# CHECK: c.ueq.d $f12,$f14 +0x33 0x30 0x27 0x46 + +# CHECK: c.ueq.s $f28,$f18 +0x33 0xe0 0x12 0x46 + +# CHECK: c.ule.d $f12,$f14 +0x37 0x30 0x27 0x46 + +# CHECK: c.ule.s $f6,$f7 +0x37 0x30 0x07 0x46 + +# CHECK: c.ult.d $f12,$f14 +0x35 0x30 0x27 0x46 + +# CHECK: c.ult.s $f6,$f7 +0x35 0x30 0x07 0x46 + +# CHECK: c.un.d $f12,$f14 +0x31 0x30 0x27 0x46 + +# CHECK: c.un.s $f6,$f7 +0x31 0x30 0x07 0x46 + +# CHECK: ceil.w.d $f12,$f14 +0x8e 0x38 0x20 0x46 + +# CHECK: ceil.w.s $f6,$f7 +0x8e 0x38 0x00 0x46 + +# CHECK: cfc1 a2,$7 +0x00 0x38 0x46 0x44 + +# CHECK: clo a2,a3 +0x21 0x30 0xe6 0x70 + +# CHECK: clz a2,a3 +0x20 0x30 0xe6 0x70 + +# CHECK: ctc1 a2,$7 +0x00 0x38 0xc6 0x44 + +# CHECK: cvt.d.s $f6,$f7 +0xa1 0x39 0x00 0x46 + +# CHECK: cvt.d.w $f12,$f14 +0xa1 0x39 0x80 0x46 + +# CHECK: cvt.l.d $f12,$f14 +0xa5 0x39 0x20 0x46 + +# CHECK: cvt.l.s $f6,$f7 +0xa5 0x39 0x00 0x46 + +# CHECK: cvt.s.d $f12,$f14 +0xa0 0x39 0x20 0x46 + +# CHECK: cvt.s.w $f6,$f7 +0xa0 0x39 0x80 0x46 + +# CHECK: cvt.w.d $f12,$f14 +0xa4 0x39 0x20 0x46 + +# CHECK: cvt.w.s $f6,$f7 +0xa4 0x39 0x00 0x46 + +# CHECK: floor.w.d $f12,$f14 +0x8f 0x39 0x20 0x46 + +# CHECK: floor.w.s $f6,$f7 +0x8f 0x39 0x00 0x46 + +# CHECK: ins s3,t1,0x6,0x7 +0x84 0x61 0x33 0x7d + +# CHECK: j 00000530 +0x4c 0x01 0x00 0x08 + +# CHECK: jal 00000530 +0x4c 0x01 0x00 0x0c + +# CHECK: jalr a2,a3 +0x09 0xf8 0xe0 0x00 + +# CHECK: jr a3 +0x08 0x00 0xe0 0x00 + +# CHECK: lb a0,9158(a1) +0xc6 0x23 0xa4 0x80 + +# CHECK: lbu a0,6(a1) +0x06 0x00 0xa4 0x90 + +# CHECK: ldc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xd4 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: li v1,17767 +0x67 0x45 0x03 0x24 + +# CHECK: ll t1,9158(a3) +0xc6 0x23 0xe9 0xc0 + +# CHECK: lui a2,0x4567 +0x67 0x45 0x06 0x3c + +# CHECK: lw a0,24(a1) +0x18 0x00 0xa4 0x8c + +# CHECK lw at,-18316(v0) +0x74 0xb8 0x41 0x8c + +# CHECK: lwc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xc4 + +# CHECK: madd a2,a3 +0x00 0x00 0xc7 0x70 + +# CHECK: maddu a2,a3 +0x01 0x00 0xc7 0x70 + +# CHECK: mfc1 a2,$f7 +0x00 0x38 0x06 0x44 + +# CHECK: mfhi a1 +0x10 0x28 0x00 0x00 + +# CHECK: mflo a1 +0x12 0x28 0x00 0x00 + +# CHECK: mov.d $f12,$f14 +0x86 0x39 0x20 0x46 + +# CHECK: mov.s $f6,$f7 +0x86 0x39 0x00 0x46 + +# CHECK: move a2,a1 +0x21 0x30 0xa0 0x00 + +# CHECK: msub a2,a3 +0x04 0x00 0xc7 0x70 + +# CHECK: msubu a2,a3 +0x05 0x00 0xc7 0x70 + +# CHECK: mtc1 a2,$f7 +0x00 0x38 0x86 0x44 + +# CHECK: mthi a3 +0x11 0x00 0xe0 0x00 + +# CHECK: mtlo a3 +0x13 0x00 0xe0 0x00 + +# CHECK: mul.d $f9,$f12,$f14 +0x42 0x32 0x27 0x46 + +# CHECK: mul.s $f9,$f6,$f7 +0x42 0x32 0x07 0x46 + +# CHECK: mul t1,a2,a3 +0x02 0x48 0xc7 0x70 + +# CHECK: mult v1,a1 +0x18 0x00 0x65 0x00 + +# CHECK: multu v1,a1 +0x19 0x00 0x65 0x00 + +# CHECK: neg.d $f12,$f14 +0x87 0x39 0x20 0x46 + +# CHECK: neg.s $f6,$f7 +0x87 0x39 0x00 0x46 + +# CHECK: neg v1,a1 +0x22 0x18 0x05 0x00 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x27 0x48 0xc7 0x00 + +# CHECK: not v1,a1 +0x27 0x18 0xa0 0x00 + +# CHECK: or v1,v1,a1 +0x25 0x18 0x65 0x00 + +# CHECK: ori t1,a2,0x4567 +0x67 0x45 0xc9 0x34 + +# CHECK: rdhwr a2,$29 +0x3b 0xe8 0x06 0x7c + +# CHECK: ror t1,a2,0x7 +0xc2 0x49 0x26 0x00 + +# CHECK: rorv t1,a2,a3 +0x46 0x48 0xe6 0x00 + +# CHECK: round.w.d $f12,$f14 +0x8c 0x39 0x20 0x46 + +# CHECK: round.w.s $f6,$f7 +0x8c 0x39 0x00 0x46 + +# CHECK: sb a0,9158(a1) +0xc6 0x23 0xa4 0xa0 + +# CHECK: sb a0,6(a1) +0x06 0x00 0xa4 0xa0 + +# CHECK: sc t1,9158(a3) +0xc6 0x23 0xe9 0xe0 + +# CHECK: sdc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xf4 + +# CHECK: seb a2,a3 +0x20 0x34 0x07 0x7c + +# CHECK: seh a2,a3 +0x20 0x36 0x07 0x7c + +# CHECK: sh a0,9158(a1) +0xc6 0x23 0xa4 0xa4 + +# CHECK: sll a0,v1,0x7 +0xc0 0x21 0x03 0x00 + +# CHECK: sllv v0,v1,a1 +0x04 0x10 0xa3 0x00 + +# CHECK: slt v1,v1,a1 +0x2a 0x18 0x65 0x00 + +# CHECK: slti v1,v1,103 +0x67 0x00 0x63 0x28 + +# CHECK: sltiu v1,v1,103 +0x67 0x00 0x63 0x2c + +# CHECK: sltu v1,v1,a1 +0x2b 0x18 0x65 0x00 + +# CHECK: sqrt.d $f12,$f14 +0x84 0x39 0x20 0x46 + +# CHECK: sqrt.s $f6,$f7 +0x84 0x39 0x00 0x46 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: srav v0,v1,a1 +0x07 0x10 0xa3 0x00 + +# CHECK: srl a0,v1,0x7 +0xc2 0x21 0x03 0x00 + +# CHECK: srlv v0,v1,a1 +0x06 0x10 0xa3 0x00 + +# CHECK: sub.d $f9,$f12,$f14 +0x41 0x32 0x27 0x46 + +# CHECK: sub.s $f9,$f6,$f7 +0x41 0x32 0x07 0x46 + +# CHECK: sub t1,a2,a3 +0x22 0x48 0xc7 0x00 + +# CHECK: subu a0,v1,a1 +0x23 0x20 0x65 0x00 + +# CHECK: sw a0,24(a1) +0x18 0x00 0xa4 0xac + +# CHECK: swc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xe4 + +# CHECK: sync 0x7 +0xcf 0x01 0x00 0x00 + +# CHECK: trunc.w.d $f12,$f14 +0x8d 0x39 0x20 0x46 + +# CHECK: trunc.w.s $f6,$f7 +0x8d 0x39 0x00 0x46 + +# CHECK: wsbh a2,a3 +0xa0 0x30 0x07 0x7c + +# CHECK: xor v1,v1,a1 +0x26 0x18 0x65 0x00 + +# CHECK: xori t1,a2,0x4567 +0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt new file mode 100644 index 0000000..1c7447a --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -0,0 +1,67 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux
+
+# CHECK: daddiu t3,k0,31949
+0x67 0x4b 0x7c 0xcd
+
+# CHECK: daddu k0,at,t3
+0x00 0x2b 0xd0 0x2d
+
+# CHECK: ddiv zero,k0,s6
+0x03 0x56 0x00 0x1e
+
+# CHECK: ddivu zero,t1,t8
+0x01 0x38 0x00 0x1f
+
+# CHECK: dmfc1 v0,$f14
+0x44 0x22 0x70 0x00
+
+# CHECK: dmtc1 s7,$f5
+0x44 0xb7 0x28 0x00
+
+# CHECK: dmult t3,k0
+0x01 0x7a 0x00 0x1c
+
+# CHECK: dmultu s7,t5
+0x02 0xed 0x00 0x1d
+
+# CHECK: dsll v1,t8,0x11
+0x00 0x18 0x1c 0x78
+
+# CHECK: dsllv gp,k1,t8
+0x03 0x1b 0xe0 0x14
+
+# CHECK: dsra at,at,0x1e
+0x00 0x01 0x0f 0xbb
+
+# CHECK: dsrav at,at,s8
+0x03 0xc1 0x08 0x17
+
+# CHECK: dsrl t2,gp,0x18
+0x00 0x1c 0x56 0x3a
+
+# CHECK: dsrlv gp,t2,s7
+0x02 0xea 0xe0 0x16
+
+# CHECK: dsubu gp,k1,t8
+0x03 0x78 0xe0 0x2f
+
+# CHECK: lw k1,-15155(at)
+0x8c 0x3b 0xc4 0xcd
+
+# CHECK: lui at,0x1
+0x3c 0x01 0x00 0x01
+
+# CHECK: lwu v1,-1746(v1)
+0x9c 0x63 0xf9 0x2e
+
+# CHECK: lui ra,0x1
+0x3c 0x1f 0x00 0x01
+
+# CHECK: sw k0,-15159(at)
+0xac 0x3a 0xc4 0xc9
+
+# CHECK: ld k0,3958(zero)
+0xdc 0x1a 0x0f 0x76
+
+# CHECK: sd a2,17767(zero)
+0xfc 0x06 0x45 0x67
diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt new file mode 100644 index 0000000..dd87522 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -0,0 +1,67 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux
+
+# CHECK: daddiu t3,k0,31949
+0xcd 0x7c 0x4b 0x67
+
+# CHECK: daddu k0,at,t3
+0x2d 0xd0 0x2b 0x00
+
+# CHECK: ddiv zero,k0,s6
+0x1e 0x00 0x56 0x03
+
+# CHECK: ddivu zero,t1,t8
+0x1f 0x00 0x38 0x01
+
+# CHECK: dmfc1 v0,$f14
+0x00 0x70 0x22 0x44
+
+# CHECK: dmtc1 s7,$f5
+0x00 0x28 0xb7 0x44
+
+# CHECK: dmult t3,k0
+0x1c 0x00 0x7a 0x01
+
+# CHECK: dmultu s7,t5
+0x1d 0x00 0xed 0x02
+
+# CHECK: dsll v1,t8,0x11
+0x78 0x1c 0x18 0x00
+
+# CHECK: dsllv gp,k1,t8
+0x14 0xe0 0x1b 0x03
+
+# CHECK: dsra at,at,0x1e
+0xbb 0x0f 0x01 0x00
+
+# CHECK: dsrav at,at,s8
+0x17 0x08 0xc1 0x03
+
+# CHECK: dsrl t2,gp,0x18
+0x3a 0x56 0x1c 0x00
+
+# CHECK: dsrlv gp,t2,s7
+0x16 0xe0 0xea 0x02
+
+# CHECK: dsubu gp,k1,t8
+0x2f 0xe0 0x78 0x03
+
+# CHECK: lw k1,-15155(at)
+0xcd 0xc4 0x3b 0x8c
+
+# CHECK: lui at,0x1
+0x01 0x00 0x01 0x3c
+
+# CHECK: lwu v1,-1746(v1)
+0x2e 0xf9 0x63 0x9c
+
+# CHECK: lui ra,0x1
+0x01 0x00 0x1f 0x3c
+
+# CHECK: sw k0,-15159(at)
+0xc9 0xc4 0x3a 0xac
+
+# CHECK: ld k0,3958(zero)
+0x76 0x0f 0x1a 0xdc
+
+# CHECK: sd a2,17767(zero)
+0x67 0x45 0x06 0xfc
diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt new file mode 100644 index 0000000..26bc94d --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -0,0 +1,91 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2
+
+# CHECK: daddiu t3,k0,31949
+0x67 0x4b 0x7c 0xcd
+
+# CHECK: daddu k0,at,t3
+0x00 0x2b 0xd0 0x2d
+
+# CHECK: ddiv zero,k0,s6
+0x03 0x56 0x00 0x1e
+
+# CHECK: ddivu zero,t1,t8
+0x01 0x38 0x00 0x1f
+
+# CHECK: dmfc1 v0,$f14
+0x44 0x22 0x70 0x00
+
+# CHECK: dmtc1 s7,$f5
+0x44 0xb7 0x28 0x00
+
+# CHECK: dmult t3,k0
+0x01 0x7a 0x00 0x1c
+
+# CHECK: dmultu s7,t5
+0x02 0xed 0x00 0x1d
+
+# CHECK: dsll v1,t8,0x11
+0x00 0x18 0x1c 0x78
+
+# CHECK: dsllv gp,k1,t8
+0x03 0x1b 0xe0 0x14
+
+# CHECK: dsra at,at,0x1e
+0x00 0x01 0x0f 0xbb
+
+# CHECK: dsrav at,at,s8
+0x03 0xc1 0x08 0x17
+
+# CHECK: dsrl t2,gp,0x18
+0x00 0x1c 0x56 0x3a
+
+# CHECK: dsrlv gp,t2,s7
+0x02 0xea 0xe0 0x16
+
+# CHECK: dsubu gp,k1,t8
+0x03 0x78 0xe0 0x2f
+
+# CHECK: lw k1,-15155(at)
+0x8c 0x3b 0xc4 0xcd
+
+# CHECK: lui at,0x1
+0x3c 0x01 0x00 0x01
+
+# CHECK: lwu v1,-1746(v1)
+0x9c 0x63 0xf9 0x2e
+
+# CHECK: lui ra,0x1
+0x3c 0x1f 0x00 0x01
+
+# CHECK: sw k0,-15159(at)
+0xac 0x3a 0xc4 0xc9
+
+# CHECK: ld k0,3958(zero)
+0xdc 0x1a 0x0f 0x76
+
+# CHECK: sd a2,17767(zero)
+0xfc 0x06 0x45 0x67
+
+# CHECK: dclo t1,t8
+0x73 0x09 0x48 0x25
+
+# CHECK: dclz k0,t1
+0x71 0x3a 0xd0 0x24
+
+# CHECK: dext a3,gp,0x1d,0x1f
+0x7f 0x87 0xf7 0x43
+
+# CHECK: dins s4,gp,0xf,0x1
+0x7f 0x94 0x7b 0xc7
+
+# CHECK: dsbh a3,gp
+0x7c 0x1c 0x38 0xa4
+
+# CHECK: dshd v1,t6
+0x7c 0x0e 0x19 0x64
+
+# CHECK: drotr s4,k1,0x6
+0x00 0x3b 0xa1 0xba
+
+# CHECK: drotrv t8,s7,a1
+0x00 0xb7 0xc0 0x56
diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt new file mode 100644 index 0000000..81a7c66 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -0,0 +1,91 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2
+
+# CHECK: daddiu t3,k0,31949
+0xcd 0x7c 0x4b 0x67
+
+# CHECK: daddu k0,at,t3
+0x2d 0xd0 0x2b 0x00
+
+# CHECK: ddiv zero,k0,s6
+0x1e 0x00 0x56 0x03
+
+# CHECK: ddivu zero,t1,t8
+0x1f 0x00 0x38 0x01
+
+# CHECK: dmfc1 v0,$f14
+0x00 0x70 0x22 0x44
+
+# CHECK: dmtc1 s7,$f5
+0x00 0x28 0xb7 0x44
+
+# CHECK: dmult t3,k0
+0x1c 0x00 0x7a 0x01
+
+# CHECK: dmultu s7,t5
+0x1d 0x00 0xed 0x02
+
+# CHECK: dsll v1,t8,0x11
+0x78 0x1c 0x18 0x00
+
+# CHECK: dsllv gp,k1,t8
+0x14 0xe0 0x1b 0x03
+
+# CHECK: dsra at,at,0x1e
+0xbb 0x0f 0x01 0x00
+
+# CHECK: dsrav at,at,s8
+0x17 0x08 0xc1 0x03
+
+# CHECK: dsrl t2,gp,0x18
+0x3a 0x56 0x1c 0x00
+
+# CHECK: dsrlv gp,t2,s7
+0x16 0xe0 0xea 0x02
+
+# CHECK: dsubu gp,k1,t8
+0x2f 0xe0 0x78 0x03
+
+# CHECK: lw k1,-15155(at)
+0xcd 0xc4 0x3b 0x8c
+
+# CHECK: lui at,0x1
+0x01 0x00 0x01 0x3c
+
+# CHECK: lwu v1,-1746(v1)
+0x2e 0xf9 0x63 0x9c
+
+# CHECK: lui ra,0x1
+0x01 0x00 0x1f 0x3c
+
+# CHECK: sw k0,-15159(at)
+0xc9 0xc4 0x3a 0xac
+
+# CHECK: ld k0,3958(zero)
+0x76 0x0f 0x1a 0xdc
+
+# CHECK: sd a2,17767(zero)
+0x67 0x45 0x06 0xfc
+
+# CHECK: dclo t1,t8
+0x25 0x48 0x09 0x73
+
+# CHECK: dclz k0,t1
+0x24 0xd0 0x3a 0x71
+
+# CHECK: dext a3,gp,0x1d,0x1f
+0x43 0xf7 0x87 0x7f
+
+# CHECK: dins s4,gp,0xf,0x1
+0xc7 0x7b 0x94 0x7f
+
+# CHECK: dsbh a3,gp
+0xa4 0x38 0x1c 0x7c
+
+# CHECK: dshd v1,t6
+0x64 0x19 0x0e 0x7c
+
+# CHECK: drotr s4,k1,0x6
+0xba 0xa1 0x3b 0x00
+
+# CHECK: drotrv t8,s7,a1
+0x56 0xc0 0xb7 0x00
diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index e2883c7..a5dbcf2 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 -x86-asm-syntax=intel | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 --output-asm-variant=1 | FileCheck %s # CHECK: movsb 0xa4 @@ -99,3 +99,9 @@ # CHECK: iretq 0x48 0xcf +# CHECK: ret +0x66 0xc3 + +# CHECK: retf +0x66 0xcb + diff --git a/test/MC/Disassembler/X86/invalid-cmp-imm.txt b/test/MC/Disassembler/X86/invalid-cmp-imm.txt new file mode 100644 index 0000000..bf8699b --- /dev/null +++ b/test/MC/Disassembler/X86/invalid-cmp-imm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} + +# This instruction would decode as cmpordps if the immediate byte was less than 8. +0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordpd if the immediate byte was less than 8. +0x66 0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordss if the immediate byte was less than 8. +0xf3 0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordsd if the immediate byte was less than 8. +0xf2 0x0f 0xc2 0xc7 0x08 diff --git a/test/MC/Disassembler/X86/lit.local.cfg b/test/MC/Disassembler/X86/lit.local.cfg index 5f3ae7d..6211b3e 100644 --- a/test/MC/Disassembler/X86/lit.local.cfg +++ b/test/MC/Disassembler/X86/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.txt'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 5f2f608..739fa6a 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -421,6 +421,18 @@ # CHECK: movl %eax, 0 0xa3 0x00 0x00 0x00 0x00 +# CHECK: cmpordpd %xmm7, %xmm0 +0x66 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordps %xmm7, %xmm0 +0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordsd %xmm7, %xmm0 +0xf2 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordss %xmm7, %xmm0 +0xf3 0x0f 0xc2 0xc7 0x07 + # CHECK: vaddps %xmm3, %xmm7, %xmm0 0xc4 0xe1 0x00 0x58 0xc3 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt new file mode 100644 index 0000000..f4b8f46 --- /dev/null +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -0,0 +1,63 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s + +# Coverage + +# CHECK: vcmptrue_usps +0xc5 0x04 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_uspd +0xc5 0x05 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_usss +0xc5 0x06 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_ussd +0xc5 0x07 0xc2 0xc7 0x1f + +# CHECK: vcmpeq_uqps +0xc5 0x04 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqpd +0xc5 0x05 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqss +0xc5 0x06 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqsd +0xc5 0x07 0xc2 0xc7 0x08 + +# CHECK: vcmpeqps +0xc5 0x04 0xc2 0xc7 0x00 + +# CHECK: vcmpeqpd +0xc5 0x05 0xc2 0xc7 0x00 + +# CHECK: vcmpeqss +0xc5 0x06 0xc2 0xc7 0x00 + +# CHECK: vcmpeqsd +0xc5 0x07 0xc2 0xc7 0x00 + +# CHECK: cmpeqps +0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqpd +0x66 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqss +0xf3 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqsd +0xf2 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpordps +0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordpd +0x66 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordss +0xf3 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordsd +0xf2 0x0f 0xc2 0xc7 0x07 diff --git a/test/MC/ELF/lit.local.cfg b/test/MC/ELF/lit.local.cfg index 461c6f4..56bf008 100644 --- a/test/MC/ELF/lit.local.cfg +++ b/test/MC/ELF/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.ll', '.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/MBlaze/lit.local.cfg b/test/MC/MBlaze/lit.local.cfg index 6f92d87..b0e1d85 100644 --- a/test/MC/MBlaze/lit.local.cfg +++ b/test/MC/MBlaze/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.ll', '.c', '.cpp', '.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'MBlaze' in targets: config.unsupported = True diff --git a/test/MC/MachO/ARM/lit.local.cfg b/test/MC/MachO/ARM/lit.local.cfg index 871e2b5..8976463 100644 --- a/test/MC/MachO/ARM/lit.local.cfg +++ b/test/MC/MachO/ARM/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: config.unsupported = True diff --git a/test/MC/MachO/lit.local.cfg b/test/MC/MachO/lit.local.cfg index 1f53769..6c49f08 100644 --- a/test/MC/MachO/lit.local.cfg +++ b/test/MC/MachO/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll index 875ba3b..71c69bb 100644 --- a/test/MC/Mips/elf-bigendian.ll +++ b/test/MC/Mips/elf-bigendian.ll @@ -5,18 +5,18 @@ ; Make sure that a section table (text) entry is correct. ; CHECK: (('sh_name', 0x{{[0]*}}5) # '.text' -; CHECKNEXT: ('sh_type', 0x{{[0]*}}1) -; CHECKNEXT: ('sh_flags', 0x{{[0]*}}6) -; CHECKNEXT: ('sh_addr', 0x{{{[0-9,a-f]+}}) -; CHECKNEXT: ('sh_offset', 0x{{{[0-9,a-f]+}}) -; CHECKNEXT: ('sh_size', 0x{{{[0-9,a-f]+}}) -; CHECKNEXT: ('sh_link', 0x{{[0]+}}) -; CHECKNEXT: ('sh_info', 0x{{[0]+}}) -; CHECKNEXT: ('sh_addralign', 0x{{[0]*}}4) -; CHECKNEXT: ('sh_entsize', 0x{{[0]+}}) +; CHECK-NEXT: ('sh_type', 0x{{[0]*}}1) +; CHECK-NEXT: ('sh_flags', 0x{{[0]*}}6) +; CHECK-NEXT: ('sh_addr', 0x{{[0-9,a-f]+}}) +; CHECK-NEXT: ('sh_offset', 0x{{[0-9,a-f]+}}) +; CHECK-NEXT: ('sh_size', 0x{{[0-9,a-f]+}}) +; CHECK-NEXT: ('sh_link', 0x{{[0]+}}) +; CHECK-NEXT: ('sh_info', 0x{{[0]+}}) +; CHECK-NEXT: ('sh_addralign', 0x{{[0]*}}4) +; CHECK-NEXT: ('sh_entsize', 0x{{[0]+}}) ; See that at least first 3 instructions are correct: GP prologue -; CHECKNEXT: ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f]*}}') +; CHECK-NEXT: ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f, ]*}}') ; ModuleID = '../br1.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32" diff --git a/test/MC/Mips/elf_basic.s b/test/MC/Mips/elf_basic.s index f7ed348..7a79fa0 100644 --- a/test/MC/Mips/elf_basic.s +++ b/test/MC/Mips/elf_basic.s @@ -1,7 +1,32 @@ -// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE %s -// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE %s +// 32 bit big endian +// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32 %s +// 32 bit little endian +// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE32 %s +// 64 bit big endian +// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64 %s +// 64 bit little endian +// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE64 %s -// Check that we produce the correct endian. +// Check that we produce 32 bit with each endian. -// CHECK-BE: ('e_indent[EI_DATA]', 0x02) -// CHECK-LE: ('e_indent[EI_DATA]', 0x01) +// This is 32 bit. +// CHECK-BE32: ('e_indent[EI_CLASS]', 0x01) +// This is big endian. +// CHECK-BE32: ('e_indent[EI_DATA]', 0x02) + +// This is 32 bit. +// CHECK-LE32: ('e_indent[EI_CLASS]', 0x01) +// This is little endian. +// CHECK-LE32: ('e_indent[EI_DATA]', 0x01) + +// Check that we produce 64 bit with each endian. + +// This is 64 bit. +// CHECK-BE64: ('e_indent[EI_CLASS]', 0x02) +// This is big endian. +// CHECK-BE64: ('e_indent[EI_DATA]', 0x02) + +// This is 64 bit. +// CHECK-LE64: ('e_indent[EI_CLASS]', 0x02) +// This is little endian. +// CHECK-LE64: ('e_indent[EI_DATA]', 0x01) diff --git a/test/MC/Mips/lit.local.cfg b/test/MC/Mips/lit.local.cfg index ecc61ea..d2e3b28 100644 --- a/test/MC/Mips/lit.local.cfg +++ b/test/MC/Mips/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.ll', '.c', '.cpp', '.s'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'Mips' in targets: config.unsupported = True diff --git a/test/MC/Mips/sym-offset.ll b/test/MC/Mips/sym-offset.ll new file mode 100644 index 0000000..5939935 --- /dev/null +++ b/test/MC/Mips/sym-offset.ll @@ -0,0 +1,22 @@ +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s + +; FIXME: use assembler instead of llc when it becomes available. + +@string1 = internal global [11 x i8] c"aaaaaaaaaa\00", align 1 +@string2 = internal global [10 x i8] c"aaaa\00bbbb\00", align 1 + +define i32 @foo1(i32 %n) nounwind readonly { +entry: +; check that the immediate fields of lwl and lwr are three apart. +; 8841000e lwl at,14(v0) +; 9841000b lwr at,11(v0) + +; CHECK: ('_section_data', '00001c3c 00009c27 21e09903 0000828f 0e004188 0b004198 + + %call = tail call i32 @memcmp(i8* getelementptr inbounds ([11 x i8]* @string1, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @string2, i32 0, i32 0), i32 4) nounwind readonly + %cmp = icmp eq i32 %call, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +declare i32 @memcmp(i8* nocapture, i8* nocapture, i32) nounwind readonly diff --git a/test/MC/X86/intel-syntax-encoding.s b/test/MC/X86/intel-syntax-encoding.s index 8891126..03b0551 100644 --- a/test/MC/X86/intel-syntax-encoding.s +++ b/test/MC/X86/intel-syntax-encoding.s @@ -42,3 +42,16 @@ LBB0_3: // CHECK: encoding: [0x0f,0xc2,0xd1,0x01] cmpltps XMM2, XMM1 + +// CHECK: encoding: [0xc3] + ret + +// CHECK: encoding: [0xcb] + retf + +// CHECK: encoding: [0xc2,0x08,0x00] + ret 8 + +// CHECK: encoding: [0xca,0x08,0x00] + retf 8 + diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s index 8e11aec..57a0037 100644 --- a/test/MC/X86/x86-32.s +++ b/test/MC/X86/x86-32.s @@ -990,3 +990,11 @@ xchgl %ecx, %eax // CHECK: xchgl %ecx, %eax // CHECK: encoding: [0x91] xchgl %eax, %ecx + +// CHECK: retw +// CHECK: encoding: [0x66,0xc3] +retw + +// CHECK: lretw +// CHECK: encoding: [0x66,0xcb] +lretw diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index f53b672..6a2d5bb 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -50,6 +50,9 @@ // CHECK: ret ret +// CHECK: retw + retw + // FIXME: Check that this matches SUB32ri8 // CHECK: subl $1, %eax subl $1, %eax @@ -841,6 +844,7 @@ iretq lretq // CHECK: lretq # encoding: [0x48,0xcb] lretl // CHECK: lretl # encoding: [0xcb] lret // CHECK: lretl # encoding: [0xcb] +lretw // CHECK: lretw # encoding: [0x66,0xcb] // rdar://8403907 sysret diff --git a/test/MC/X86/x86_64-avx-encoding.s b/test/MC/X86/x86_64-avx-encoding.s index 990ba40..bd5559a 100644 --- a/test/MC/X86/x86_64-avx-encoding.s +++ b/test/MC/X86/x86_64-avx-encoding.s @@ -600,6 +600,774 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03] vcmpunordsd -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: vcmpps $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x08] + vcmpeq_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x09] + vcmpngeps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0a] + vcmpngtps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0b] + vcmpfalseps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0c] + vcmpneq_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0d] + vcmpgeps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0e] + vcmpgtps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0f] + vcmptrueps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x10] + vcmpeq_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x11] + vcmplt_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x12] + vcmple_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x13] + vcmpunord_sps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x14] + vcmpneq_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x15] + vcmpnlt_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x16] + vcmpnle_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x17] + vcmpord_sps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x18] + vcmpeq_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x19] + vcmpnge_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1a] + vcmpngt_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1b] + vcmpfalse_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1c] + vcmpneq_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1d] + vcmpge_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1e] + vcmpgt_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f] + vcmptrue_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngeps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalseps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgeps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptrueps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_osps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_sps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_usps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_sps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_usps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_osps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_osps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_usps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x08] + vcmpeq_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x09] + vcmpngepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0a] + vcmpngtpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0b] + vcmpfalsepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0c] + vcmpneq_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0d] + vcmpgepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0e] + vcmpgtpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0f] + vcmptruepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x10] + vcmpeq_ospd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x11] + vcmplt_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x12] + vcmple_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x13] + vcmpunord_spd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x14] + vcmpneq_uspd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x15] + vcmpnlt_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x16] + vcmpnle_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x17] + vcmpord_spd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x18] + vcmpeq_uspd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x19] + vcmpnge_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1a] + vcmpngt_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1b] + vcmpfalse_ospd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1c] + vcmpneq_ospd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1d] + vcmpge_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1e] + vcmpgt_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1f] + vcmptrue_uspd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalsepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptruepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_ospd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_spd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_uspd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_spd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_uspd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_ospd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_ospd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_uspd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x08] + vcmpeq_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x09] + vcmpngess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0a] + vcmpngtss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0b] + vcmpfalsess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0c] + vcmpneq_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0d] + vcmpgess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0e] + vcmpgtss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0f] + vcmptruess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x10] + vcmpeq_osss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x11] + vcmplt_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x12] + vcmple_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x13] + vcmpunord_sss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x14] + vcmpneq_usss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x15] + vcmpnlt_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x16] + vcmpnle_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x17] + vcmpord_sss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x18] + vcmpeq_usss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x19] + vcmpnge_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1a] + vcmpngt_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1b] + vcmpfalse_osss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1c] + vcmpneq_osss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1d] + vcmpge_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1e] + vcmpgt_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1f] + vcmptrue_usss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalsess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptruess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_osss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_sss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_usss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_sss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_usss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_osss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_osss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_usss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x08] + vcmpeq_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x09] + vcmpngesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0a] + vcmpngtsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0b] + vcmpfalsesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0c] + vcmpneq_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0d] + vcmpgesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0e] + vcmpgtsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0f] + vcmptruesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x10] + vcmpeq_ossd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x11] + vcmplt_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x12] + vcmple_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x13] + vcmpunord_ssd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x14] + vcmpneq_ussd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x15] + vcmpnlt_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x16] + vcmpnle_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x17] + vcmpord_ssd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x18] + vcmpeq_ussd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x19] + vcmpnge_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1a] + vcmpngt_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1b] + vcmpfalse_ossd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1c] + vcmpneq_ossd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1d] + vcmpge_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1e] + vcmpgt_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1f] + vcmptrue_ussd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalsesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptruesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_ossd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_ssd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_ussd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_ssd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_ussd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_ossd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_ossd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_ussd -4(%rbx,%rcx,8), %xmm12, %xmm13 + // CHECK: vucomiss %xmm11, %xmm12 // CHECK: encoding: [0xc4,0x41,0x78,0x2e,0xe3] vucomiss %xmm11, %xmm12 |