diff options
Diffstat (limited to 'test/MC/Disassembler/ARM/move-banked-regs-thumb.txt')
| -rw-r--r-- | test/MC/Disassembler/ARM/move-banked-regs-thumb.txt | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt b/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt new file mode 100644 index 0000000..29e91ab --- /dev/null +++ b/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt @@ -0,0 +1,153 @@ +@ RUN: llvm-mc -disassemble -triple thumb -mcpu=cyclone %s | FileCheck %s + +[0xe0,0xf3,0x20,0x82] +[0xe1,0xf3,0x20,0x83] +[0xe2,0xf3,0x20,0x85] +[0xe3,0xf3,0x20,0x87] +[0xe4,0xf3,0x20,0x8b] +[0xe5,0xf3,0x20,0x81] +[0xe6,0xf3,0x20,0x82] +@ CHECK: mrs r2, r8_usr +@ CHECK: mrs r3, r9_usr +@ CHECK: mrs r5, r10_usr +@ CHECK: mrs r7, r11_usr +@ CHECK: mrs r11, r12_usr +@ CHECK: mrs r1, sp_usr +@ CHECK: mrs r2, lr_usr + +[0xe8,0xf3,0x20,0x82] +[0xe9,0xf3,0x20,0x83] +[0xea,0xf3,0x20,0x85] +[0xeb,0xf3,0x20,0x87] +[0xec,0xf3,0x20,0x8b] +[0xed,0xf3,0x20,0x81] +[0xee,0xf3,0x20,0x82] +[0xfe,0xf3,0x20,0x83] +@ CHECK: mrs r2, r8_fiq +@ CHECK: mrs r3, r9_fiq +@ CHECK: mrs r5, r10_fiq +@ CHECK: mrs r7, r11_fiq +@ CHECK: mrs r11, r12_fiq +@ CHECK: mrs r1, sp_fiq +@ CHECK: mrs r2, lr_fiq +@ CHECK: mrs r3, SPSR_fiq + +[0xe0,0xf3,0x30,0x84] +[0xe1,0xf3,0x30,0x89] +[0xf0,0xf3,0x30,0x81] +@ CHECK: mrs r4, lr_irq +@ CHECK: mrs r9, sp_irq +@ CHECK: mrs r1, SPSR_irq + +[0xe2,0xf3,0x30,0x81] +[0xe3,0xf3,0x30,0x83] +[0xf2,0xf3,0x30,0x85] +@ CHECK: mrs r1, lr_svc +@ CHECK: mrs r3, sp_svc +@ CHECK: mrs r5, SPSR_svc + +[0xe4,0xf3,0x30,0x85] +[0xe5,0xf3,0x30,0x87] +[0xf4,0xf3,0x30,0x89] +@ CHECK: mrs r5, lr_abt +@ CHECK: mrs r7, sp_abt +@ CHECK: mrs r9, SPSR_abt + +[0xe6,0xf3,0x30,0x89] +[0xe7,0xf3,0x30,0x8b] +[0xf6,0xf3,0x30,0x8c] +@ CHECK: mrs r9, lr_und +@ CHECK: mrs r11, sp_und +@ CHECK: mrs r12, SPSR_und + + +[0xec,0xf3,0x30,0x82] +[0xed,0xf3,0x30,0x84] +[0xfc,0xf3,0x30,0x86] +@ CHECK: mrs r2, lr_mon +@ CHECK: mrs r4, sp_mon +@ CHECK: mrs r6, SPSR_mon + + +[0xee,0xf3,0x30,0x86] +[0xef,0xf3,0x30,0x88] +[0xfe,0xf3,0x30,0x8a] +@ CHECK: mrs r6, elr_hyp +@ CHECK: mrs r8, sp_hyp +@ CHECK: mrs r10, SPSR_hyp + + +[0x82,0xf3,0x20,0x80] +[0x83,0xf3,0x20,0x81] +[0x85,0xf3,0x20,0x82] +[0x87,0xf3,0x20,0x83] +[0x8b,0xf3,0x20,0x84] +[0x81,0xf3,0x20,0x85] +[0x82,0xf3,0x20,0x86] +@ CHECK: msr r8_usr, r2 +@ CHECK: msr r9_usr, r3 +@ CHECK: msr r10_usr, r5 +@ CHECK: msr r11_usr, r7 +@ CHECK: msr r12_usr, r11 +@ CHECK: msr sp_usr, r1 +@ CHECK: msr lr_usr, r2 + +[0x82,0xf3,0x20,0x88] +[0x83,0xf3,0x20,0x89] +[0x85,0xf3,0x20,0x8a] +[0x87,0xf3,0x20,0x8b] +[0x8b,0xf3,0x20,0x8c] +[0x81,0xf3,0x20,0x8d] +[0x82,0xf3,0x20,0x8e] +[0x93,0xf3,0x20,0x8e] +@ CHECK: msr r8_fiq, r2 +@ CHECK: msr r9_fiq, r3 +@ CHECK: msr r10_fiq, r5 +@ CHECK: msr r11_fiq, r7 +@ CHECK: msr r12_fiq, r11 +@ CHECK: msr sp_fiq, r1 +@ CHECK: msr lr_fiq, r2 +@ CHECK: msr SPSR_fiq, r3 + +[0x84,0xf3,0x30,0x80] +[0x89,0xf3,0x30,0x81] +[0x9b,0xf3,0x30,0x80] +@ CHECK: msr lr_irq, r4 +@ CHECK: msr sp_irq, r9 +@ CHECK: msr SPSR_irq, r11 + +[0x81,0xf3,0x30,0x82] +[0x83,0xf3,0x30,0x83] +[0x95,0xf3,0x30,0x82] +@ CHECK: msr lr_svc, r1 +@ CHECK: msr sp_svc, r3 +@ CHECK: msr SPSR_svc, r5 + +[0x85,0xf3,0x30,0x84] +[0x87,0xf3,0x30,0x85] +[0x99,0xf3,0x30,0x84] +@ CHECK: msr lr_abt, r5 +@ CHECK: msr sp_abt, r7 +@ CHECK: msr SPSR_abt, r9 + +[0x89,0xf3,0x30,0x86] +[0x8b,0xf3,0x30,0x87] +[0x9c,0xf3,0x30,0x86] +@ CHECK: msr lr_und, r9 +@ CHECK: msr sp_und, r11 +@ CHECK: msr SPSR_und, r12 + + +[0x82,0xf3,0x30,0x8c] +[0x84,0xf3,0x30,0x8d] +[0x96,0xf3,0x30,0x8c] +@ CHECK: msr lr_mon, r2 +@ CHECK: msr sp_mon, r4 +@ CHECK: msr SPSR_mon, r6 + +[0x86,0xf3,0x30,0x8e] +[0x88,0xf3,0x30,0x8f] +[0x9a,0xf3,0x30,0x8e] +@ CHECK: msr elr_hyp, r6 +@ CHECK: msr sp_hyp, r8 +@ CHECK: msr SPSR_hyp, r10 |