aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC/Disassembler/ARM
diff options
context:
space:
mode:
Diffstat (limited to 'test/MC/Disassembler/ARM')
-rw-r--r--test/MC/Disassembler/ARM/arm-tests.txt2
-rw-r--r--test/MC/Disassembler/ARM/d16.txt23
-rw-r--r--test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt35
-rw-r--r--test/MC/Disassembler/ARM/move-banked-regs-arm.txt150
-rw-r--r--test/MC/Disassembler/ARM/move-banked-regs-thumb.txt153
-rw-r--r--test/MC/Disassembler/ARM/thumb-MSR-MClass.txt95
-rw-r--r--test/MC/Disassembler/ARM/thumb-tests.txt2
-rw-r--r--test/MC/Disassembler/ARM/thumb2-preloads.txt69
8 files changed, 523 insertions, 6 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index acc2d9f..e82f75a 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
# CHECK: addpl r4, pc, #318767104
0x4c 0x45 0x8f 0x52
diff --git a/test/MC/Disassembler/ARM/d16.txt b/test/MC/Disassembler/ARM/d16.txt
new file mode 100644
index 0000000..735af81
--- /dev/null
+++ b/test/MC/Disassembler/ARM/d16.txt
@@ -0,0 +1,23 @@
+# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
+# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
+
+
+# D32: vadd.f64 d1, d2, d16
+# D16: warning: invalid instruction encoding
+[0x32,0xee,0x20,0x1b]
+
+# D32: vadd.f64 d1, d17, d6
+# D16: warning: invalid instruction encoding
+[0x31,0xee,0x86,0x1b]
+
+# D32: vadd.f64 d19, d7, d6
+# D16: warning: invalid instruction encoding
+[0x77,0xee,0x06,0x3b]
+
+# D32: vcvt.f64.f32 d22, s4
+# D16: warning: invalid instruction encoding
+[0xf7,0xee,0xc2,0x6a]
+
+# D32: vcvt.f32.f64 s26, d30
+# D16: warning: invalid instruction encoding
+[0xb7,0xee,0xee,0xdb]
diff --git a/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt b/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
new file mode 100644
index 0000000..26fa907
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
@@ -0,0 +1,35 @@
+# RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck --check-prefix=CHECK %s
+# RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mrs
+#------------------------------------------------------------------------------
+
+# invalid SYSm
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xef 0xf3 0x80 0x80]
+[0xef 0xf3 0x80 0x80]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for msr
+#------------------------------------------------------------------------------
+
+# invalid mask = '00'
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0x80 0xf3 0x00 0x80]
+[0x80 0xf3 0x00 0x80]
+
+# invalid mask = '11' with SYSm not in {0..3}
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0x80 0xf3 0x05 0x8c]
+[0x80 0xf3 0x05 0x8c]
+
+# invalid mask = '01' (ThumbV7M does not have the DSP extension)
+# CHECK-V7M: warning: potentially undefined instruction encoding
+# CHECK-V7M-NEXT: [0x80 0xf3 0x00 0x84]
+[0x80 0xf3 0x00 0x84]
+
+# invalid SYSm
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x80 0xf3 0x80 0x88]
+[0x80 0xf3 0x80 0x88]
diff --git a/test/MC/Disassembler/ARM/move-banked-regs-arm.txt b/test/MC/Disassembler/ARM/move-banked-regs-arm.txt
new file mode 100644
index 0000000..dd1d463
--- /dev/null
+++ b/test/MC/Disassembler/ARM/move-banked-regs-arm.txt
@@ -0,0 +1,150 @@
+@ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s
+
+
+[0x00,0x22,0x20,0xe1]
+[0x00,0x32,0x21,0xe1]
+[0x00,0x52,0x22,0xe1]
+[0x00,0x72,0x23,0xe1]
+[0x00,0xb2,0x24,0xe1]
+[0x00,0x12,0x25,0xe1]
+[0x00,0x22,0x26,0xe1]
+@ CHECK: mrs r2, r8_usr
+@ CHECK: mrs r3, r9_usr
+@ CHECK: mrs r5, r10_usr
+@ CHECK: mrs r7, r11_usr
+@ CHECK: mrs r11, r12_usr
+@ CHECK: mrs r1, sp_usr
+@ CHECK: mrs r2, lr_usr
+
+[0x00,0x22,0x28,0xe1]
+[0x00,0x32,0x29,0xe1]
+[0x00,0x52,0x2a,0xe1]
+[0x00,0x72,0x2b,0xe1]
+[0x00,0xb2,0x2c,0xe1]
+[0x00,0x12,0x2d,0xe1]
+[0x00,0x22,0x2e,0xe1]
+[0x00,0x32,0x6e,0xe1]
+@ CHECK: mrs r2, r8_fiq
+@ CHECK: mrs r3, r9_fiq
+@ CHECK: mrs r5, r10_fiq
+@ CHECK: mrs r7, r11_fiq
+@ CHECK: mrs r11, r12_fiq
+@ CHECK: mrs r1, sp_fiq
+@ CHECK: mrs r2, lr_fiq
+@ CHECK: mrs r3, SPSR_fiq
+
+[0x00,0x43,0x20,0xe1]
+[0x00,0x93,0x21,0xe1]
+[0x00,0x13,0x60,0xe1]
+@ CHECK: mrs r4, lr_irq
+@ CHECK: mrs r9, sp_irq
+@ CHECK: mrs r1, SPSR_irq
+
+[0x00,0x13,0x22,0xe1]
+[0x00,0x33,0x23,0xe1]
+[0x00,0x53,0x62,0xe1]
+@ CHECK: mrs r1, lr_svc
+@ CHECK: mrs r3, sp_svc
+@ CHECK: mrs r5, SPSR_svc
+
+[0x00,0x53,0x24,0xe1]
+[0x00,0x73,0x25,0xe1]
+[0x00,0x93,0x64,0xe1]
+@ CHECK: mrs r5, lr_abt
+@ CHECK: mrs r7, sp_abt
+@ CHECK: mrs r9, SPSR_abt
+
+[0x00,0x93,0x26,0xe1]
+[0x00,0xb3,0x27,0xe1]
+[0x00,0xc3,0x66,0xe1]
+@ CHECK: mrs r9, lr_und
+@ CHECK: mrs r11, sp_und
+@ CHECK: mrs r12, SPSR_und
+
+[0x00,0x23,0x2c,0xe1]
+[0x00,0x43,0x2d,0xe1]
+[0x00,0x63,0x6c,0xe1]
+@ CHECK: mrs r2, lr_mon
+@ CHECK: mrs r4, sp_mon
+@ CHECK: mrs r6, SPSR_mon
+
+[0x00,0x63,0x2e,0xe1]
+[0x00,0x83,0x2f,0xe1]
+[0x00,0xa3,0x6e,0xe1]
+@ CHECK: mrs r6, elr_hyp
+@ CHECK: mrs r8, sp_hyp
+@ CHECK: mrs r10, SPSR_hyp
+
+[0x02,0xf2,0x20,0xe1]
+[0x03,0xf2,0x21,0xe1]
+[0x05,0xf2,0x22,0xe1]
+[0x07,0xf2,0x23,0xe1]
+[0x0b,0xf2,0x24,0xe1]
+[0x01,0xf2,0x25,0xe1]
+[0x02,0xf2,0x26,0xe1]
+@ CHECK: msr r8_usr, r2
+@ CHECK: msr r9_usr, r3
+@ CHECK: msr r10_usr, r5
+@ CHECK: msr r11_usr, r7
+@ CHECK: msr r12_usr, r11
+@ CHECK: msr sp_usr, r1
+@ CHECK: msr lr_usr, r2
+
+[0x02,0xf2,0x28,0xe1]
+[0x03,0xf2,0x29,0xe1]
+[0x05,0xf2,0x2a,0xe1]
+[0x07,0xf2,0x2b,0xe1]
+[0x0b,0xf2,0x2c,0xe1]
+[0x01,0xf2,0x2d,0xe1]
+[0x02,0xf2,0x2e,0xe1]
+[0x03,0xf2,0x6e,0xe1]
+@ CHECK: msr r8_fiq, r2
+@ CHECK: msr r9_fiq, r3
+@ CHECK: msr r10_fiq, r5
+@ CHECK: msr r11_fiq, r7
+@ CHECK: msr r12_fiq, r11
+@ CHECK: msr sp_fiq, r1
+@ CHECK: msr lr_fiq, r2
+@ CHECK: msr SPSR_fiq, r3
+
+[0x04,0xf3,0x20,0xe1]
+[0x09,0xf3,0x21,0xe1]
+[0x0b,0xf3,0x60,0xe1]
+@ CHECK: msr lr_irq, r4
+@ CHECK: msr sp_irq, r9
+@ CHECK: msr SPSR_irq, r11
+
+[0x01,0xf3,0x22,0xe1]
+[0x03,0xf3,0x23,0xe1]
+[0x05,0xf3,0x62,0xe1]
+@ CHECK: msr lr_svc, r1
+@ CHECK: msr sp_svc, r3
+@ CHECK: msr SPSR_svc, r5
+
+[0x05,0xf3,0x24,0xe1]
+[0x07,0xf3,0x25,0xe1]
+[0x09,0xf3,0x64,0xe1]
+@ CHECK: msr lr_abt, r5
+@ CHECK: msr sp_abt, r7
+@ CHECK: msr SPSR_abt, r9
+
+[0x09,0xf3,0x26,0xe1]
+[0x0b,0xf3,0x27,0xe1]
+[0x0c,0xf3,0x66,0xe1]
+@ CHECK: msr lr_und, r9
+@ CHECK: msr sp_und, r11
+@ CHECK: msr SPSR_und, r12
+
+[0x02,0xf3,0x2c,0xe1]
+[0x04,0xf3,0x2d,0xe1]
+[0x06,0xf3,0x6c,0xe1]
+@ CHECK: msr lr_mon, r2
+@ CHECK: msr sp_mon, r4
+@ CHECK: msr SPSR_mon, r6
+
+[0x06,0xf3,0x2e,0xe1]
+[0x08,0xf3,0x2f,0xe1]
+[0x0a,0xf3,0x6e,0xe1]
+@ CHECK: msr elr_hyp, r6
+@ CHECK: msr sp_hyp, r8
+@ CHECK: msr SPSR_hyp, r10
diff --git a/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt b/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt
new file mode 100644
index 0000000..29e91ab
--- /dev/null
+++ b/test/MC/Disassembler/ARM/move-banked-regs-thumb.txt
@@ -0,0 +1,153 @@
+@ RUN: llvm-mc -disassemble -triple thumb -mcpu=cyclone %s | FileCheck %s
+
+[0xe0,0xf3,0x20,0x82]
+[0xe1,0xf3,0x20,0x83]
+[0xe2,0xf3,0x20,0x85]
+[0xe3,0xf3,0x20,0x87]
+[0xe4,0xf3,0x20,0x8b]
+[0xe5,0xf3,0x20,0x81]
+[0xe6,0xf3,0x20,0x82]
+@ CHECK: mrs r2, r8_usr
+@ CHECK: mrs r3, r9_usr
+@ CHECK: mrs r5, r10_usr
+@ CHECK: mrs r7, r11_usr
+@ CHECK: mrs r11, r12_usr
+@ CHECK: mrs r1, sp_usr
+@ CHECK: mrs r2, lr_usr
+
+[0xe8,0xf3,0x20,0x82]
+[0xe9,0xf3,0x20,0x83]
+[0xea,0xf3,0x20,0x85]
+[0xeb,0xf3,0x20,0x87]
+[0xec,0xf3,0x20,0x8b]
+[0xed,0xf3,0x20,0x81]
+[0xee,0xf3,0x20,0x82]
+[0xfe,0xf3,0x20,0x83]
+@ CHECK: mrs r2, r8_fiq
+@ CHECK: mrs r3, r9_fiq
+@ CHECK: mrs r5, r10_fiq
+@ CHECK: mrs r7, r11_fiq
+@ CHECK: mrs r11, r12_fiq
+@ CHECK: mrs r1, sp_fiq
+@ CHECK: mrs r2, lr_fiq
+@ CHECK: mrs r3, SPSR_fiq
+
+[0xe0,0xf3,0x30,0x84]
+[0xe1,0xf3,0x30,0x89]
+[0xf0,0xf3,0x30,0x81]
+@ CHECK: mrs r4, lr_irq
+@ CHECK: mrs r9, sp_irq
+@ CHECK: mrs r1, SPSR_irq
+
+[0xe2,0xf3,0x30,0x81]
+[0xe3,0xf3,0x30,0x83]
+[0xf2,0xf3,0x30,0x85]
+@ CHECK: mrs r1, lr_svc
+@ CHECK: mrs r3, sp_svc
+@ CHECK: mrs r5, SPSR_svc
+
+[0xe4,0xf3,0x30,0x85]
+[0xe5,0xf3,0x30,0x87]
+[0xf4,0xf3,0x30,0x89]
+@ CHECK: mrs r5, lr_abt
+@ CHECK: mrs r7, sp_abt
+@ CHECK: mrs r9, SPSR_abt
+
+[0xe6,0xf3,0x30,0x89]
+[0xe7,0xf3,0x30,0x8b]
+[0xf6,0xf3,0x30,0x8c]
+@ CHECK: mrs r9, lr_und
+@ CHECK: mrs r11, sp_und
+@ CHECK: mrs r12, SPSR_und
+
+
+[0xec,0xf3,0x30,0x82]
+[0xed,0xf3,0x30,0x84]
+[0xfc,0xf3,0x30,0x86]
+@ CHECK: mrs r2, lr_mon
+@ CHECK: mrs r4, sp_mon
+@ CHECK: mrs r6, SPSR_mon
+
+
+[0xee,0xf3,0x30,0x86]
+[0xef,0xf3,0x30,0x88]
+[0xfe,0xf3,0x30,0x8a]
+@ CHECK: mrs r6, elr_hyp
+@ CHECK: mrs r8, sp_hyp
+@ CHECK: mrs r10, SPSR_hyp
+
+
+[0x82,0xf3,0x20,0x80]
+[0x83,0xf3,0x20,0x81]
+[0x85,0xf3,0x20,0x82]
+[0x87,0xf3,0x20,0x83]
+[0x8b,0xf3,0x20,0x84]
+[0x81,0xf3,0x20,0x85]
+[0x82,0xf3,0x20,0x86]
+@ CHECK: msr r8_usr, r2
+@ CHECK: msr r9_usr, r3
+@ CHECK: msr r10_usr, r5
+@ CHECK: msr r11_usr, r7
+@ CHECK: msr r12_usr, r11
+@ CHECK: msr sp_usr, r1
+@ CHECK: msr lr_usr, r2
+
+[0x82,0xf3,0x20,0x88]
+[0x83,0xf3,0x20,0x89]
+[0x85,0xf3,0x20,0x8a]
+[0x87,0xf3,0x20,0x8b]
+[0x8b,0xf3,0x20,0x8c]
+[0x81,0xf3,0x20,0x8d]
+[0x82,0xf3,0x20,0x8e]
+[0x93,0xf3,0x20,0x8e]
+@ CHECK: msr r8_fiq, r2
+@ CHECK: msr r9_fiq, r3
+@ CHECK: msr r10_fiq, r5
+@ CHECK: msr r11_fiq, r7
+@ CHECK: msr r12_fiq, r11
+@ CHECK: msr sp_fiq, r1
+@ CHECK: msr lr_fiq, r2
+@ CHECK: msr SPSR_fiq, r3
+
+[0x84,0xf3,0x30,0x80]
+[0x89,0xf3,0x30,0x81]
+[0x9b,0xf3,0x30,0x80]
+@ CHECK: msr lr_irq, r4
+@ CHECK: msr sp_irq, r9
+@ CHECK: msr SPSR_irq, r11
+
+[0x81,0xf3,0x30,0x82]
+[0x83,0xf3,0x30,0x83]
+[0x95,0xf3,0x30,0x82]
+@ CHECK: msr lr_svc, r1
+@ CHECK: msr sp_svc, r3
+@ CHECK: msr SPSR_svc, r5
+
+[0x85,0xf3,0x30,0x84]
+[0x87,0xf3,0x30,0x85]
+[0x99,0xf3,0x30,0x84]
+@ CHECK: msr lr_abt, r5
+@ CHECK: msr sp_abt, r7
+@ CHECK: msr SPSR_abt, r9
+
+[0x89,0xf3,0x30,0x86]
+[0x8b,0xf3,0x30,0x87]
+[0x9c,0xf3,0x30,0x86]
+@ CHECK: msr lr_und, r9
+@ CHECK: msr sp_und, r11
+@ CHECK: msr SPSR_und, r12
+
+
+[0x82,0xf3,0x30,0x8c]
+[0x84,0xf3,0x30,0x8d]
+[0x96,0xf3,0x30,0x8c]
+@ CHECK: msr lr_mon, r2
+@ CHECK: msr sp_mon, r4
+@ CHECK: msr SPSR_mon, r6
+
+[0x86,0xf3,0x30,0x8e]
+[0x88,0xf3,0x30,0x8f]
+[0x9a,0xf3,0x30,0x8e]
+@ CHECK: msr elr_hyp, r6
+@ CHECK: msr sp_hyp, r8
+@ CHECK: msr SPSR_hyp, r10
diff --git a/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt b/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt
index 497cb9a..c1a2790 100644
--- a/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt
+++ b/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt
@@ -1,7 +1,94 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=thumbv7em | FileCheck %s
-# CHECK: msr primask, r0
-0x80 0xf3 0x10 0x80
+#------------------------------------------------------------------------------
+# MRS
+#------------------------------------------------------------------------------
-# CHECK: mrs r0, primask
+# CHECK: mrs r0, apsr
+# CHECK: mrs r0, iapsr
+# CHECK: mrs r0, eapsr
+# CHECK: mrs r0, xpsr
+# CHECK: mrs r0, ipsr
+# CHECK: mrs r0, epsr
+# CHECK: mrs r0, iepsr
+# CHECK: mrs r0, msp
+# CHECK: mrs r0, psp
+# CHECK: mrs r0, primask
+# CHECK: mrs r0, basepri
+# CHECK: mrs r0, basepri_max
+# CHECK: mrs r0, faultmask
+# CHECK: mrs r0, control
+
+0xef 0xf3 0x00 0x80
+0xef 0xf3 0x01 0x80
+0xef 0xf3 0x02 0x80
+0xef 0xf3 0x03 0x80
+0xef 0xf3 0x05 0x80
+0xef 0xf3 0x06 0x80
+0xef 0xf3 0x07 0x80
+0xef 0xf3 0x08 0x80
+0xef 0xf3 0x09 0x80
0xef 0xf3 0x10 0x80
+0xef 0xf3 0x11 0x80
+0xef 0xf3 0x12 0x80
+0xef 0xf3 0x13 0x80
+0xef 0xf3 0x14 0x80
+
+
+#------------------------------------------------------------------------------
+# MSR
+#------------------------------------------------------------------------------
+
+# CHECK: msr apsr_nzcvq, r0
+# CHECK: msr apsr_g, r0
+# CHECK: msr apsr_nzcvqg, r0
+
+0x80 0xf3 0x00 0x88
+0x80 0xf3 0x00 0x84
+0x80 0xf3 0x00 0x8c
+
+# CHECK: msr iapsr_nzcvq, r0
+# CHECK: msr iapsr_g, r0
+# CHECK: msr iapsr_nzcvqg, r0
+
+0x80 0xf3 0x01 0x88
+0x80 0xf3 0x01 0x84
+0x80 0xf3 0x01 0x8c
+
+# CHECK: msr eapsr_nzcvq, r0
+# CHECK: msr eapsr_g, r0
+# CHECK: msr eapsr_nzcvqg, r0
+
+0x80 0xf3 0x02 0x88
+0x80 0xf3 0x02 0x84
+0x80 0xf3 0x02 0x8c
+
+# CHECK: msr xpsr_nzcvq, r0
+# CHECK: msr xpsr_g, r0
+# CHECK: msr xpsr_nzcvqg, r0
+
+0x80 0xf3 0x03 0x88
+0x80 0xf3 0x03 0x84
+0x80 0xf3 0x03 0x8c
+
+# CHECK: msr ipsr, r0
+# CHECK: msr epsr, r0
+# CHECK: msr iepsr, r0
+# CHECK: msr msp, r0
+# CHECK: msr psp, r0
+# CHECK: msr primask, r0
+# CHECK: msr basepri, r0
+# CHECK: msr basepri_max, r0
+# CHECK: msr faultmask, r0
+# CHECK: msr control, r0
+
+0x80 0xf3 0x05 0x88
+0x80 0xf3 0x06 0x88
+0x80 0xf3 0x07 0x88
+0x80 0xf3 0x08 0x88
+0x80 0xf3 0x09 0x88
+0x80 0xf3 0x10 0x88
+0x80 0xf3 0x11 0x88
+0x80 0xf3 0x12 0x88
+0x80 0xf3 0x13 0x88
+0x80 0xf3 0x14 0x88
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index df2bac1..dcb6e3f 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
# CHECK: add r5, sp, #68
0x11 0xad
diff --git a/test/MC/Disassembler/ARM/thumb2-preloads.txt b/test/MC/Disassembler/ARM/thumb2-preloads.txt
new file mode 100644
index 0000000..dec4d64
--- /dev/null
+++ b/test/MC/Disassembler/ARM/thumb2-preloads.txt
@@ -0,0 +1,69 @@
+# RUN: not llvm-mc -triple=thumbv6t2-none-eabi -disassemble < %s 2>/dev/null | FileCheck %s --check-prefix=V6T2
+# RUN: not llvm-mc -triple=thumbv7a-none-eabi -disassemble -mattr=-mp < %s 2>/dev/null | FileCheck %s --check-prefix=V6T2 --check-prefix=V7
+# RUN: llvm-mc -triple=thumbv7a-none-eabi -disassemble -mattr=+mp < %s 2>/dev/null | FileCheck %s --check-prefix=V6T2 --check-prefix=V7 --check-prefix=MP
+# RUN: not llvm-mc -triple=thumbv7m-none-eabi -disassemble < %s 2>/dev/null | FileCheck %s --check-prefix=V6T2 --check-prefix=V7
+
+# RUN: not llvm-mc -triple=thumbv6t2-none-eabi -disassemble < %s 2>&1 >/dev/null | FileCheck %s --check-prefix=MP-ERR --check-prefix=V7-ERR
+# RUN: not llvm-mc -triple=thumbv7a-none-eabi -disassemble -mattr=-mp < %s 2>&1 >/dev/null | FileCheck %s --check-prefix=MP-ERR
+# RUN: llvm-mc -triple=thumbv7a-none-eabi -disassemble -mattr=+mp < %s 2>&1 >/dev/null
+# RUN: not llvm-mc -triple=thumbv7m-none-eabi -disassemble < %s 2>&1 >/dev/null | FileCheck %s --check-prefix=MP-ERR
+
+# V6T2: pld [r1, #3]
+[0x91,0xf8,0x03,0xf0]
+
+# V6T2: pld [r2, #-5]
+[0x12,0xf8,0x05,0xfc]
+
+# MP: pldw [r3, #4]
+# MP-ERR: invalid instruction encoding
+# MP-ERR-NEXT: [0xb3,0xf8,0x04,0xf0]
+[0xb3,0xf8,0x04,0xf0]
+
+# MP: pldw [r4, #-6]
+# MP-ERR: invalid instruction encoding
+# MP-ERR-NEXT: [0x34,0xf8,0x06,0xfc]
+[0x34,0xf8,0x06,0xfc]
+
+# V6T2: pld [pc, #8]
+[0x9f,0xf8,0x08,0xf0]
+
+# V6T2: pld [pc, #-5]
+[0x1f,0xf8,0x05,0xf0]
+
+# V6T2: pld [r5, r6]
+[0x15,0xf8,0x06,0xf0]
+
+# V6T2: pld [r7, r8, lsl #1]
+[0x17,0xf8,0x18,0xf0]
+
+# MP: pldw [r9, r10]
+# MP-ERR: invalid instruction encoding
+# MP-ERR-NEXT: [0x39,0xf8,0x0a,0xf0]
+[0x39,0xf8,0x0a,0xf0]
+
+# MP: pldw [r11, r12, lsl #2]
+# MP-ERR: invalid instruction encoding
+# MP-ERR-NEXT: [0x3b,0xf8,0x2c,0xf0]
+[0x3b,0xf8,0x2c,0xf0]
+
+# V7: pli [r1, #10]
+# V7-ERR: invalid instruction encoding
+# V7-ERR-NEXT: [0x91,0xf9,0x0a,0xf0]
+[0x91,0xf9,0x0a,0xf0]
+
+# V7: pli [r2, #-3]
+# V7-ERR: invalid instruction encoding
+# V7-ERR-NEXT: [0x12,0xf9,0x03,0xfc]
+[0x12,0xf9,0x03,0xfc]
+
+# V7: pli [pc, #6]
+# V7-ERR: invalid instruction encoding
+# V7-ERR-NEXT: [0x9f,0xf9,0x06,0xf0]
+[0x9f,0xf9,0x06,0xf0]
+
+# V7: pli [pc, #-8]
+# V7-ERR: invalid instruction encoding
+# V7-ERR-NEXT: [0x1f,0xf9,0x08,0xf0]
+[0x1f,0xf9,0x08,0xf0]
+
+# NO-ERR-NOT: invalid instruction encoding
generated by cgit v1.1 at 2024-06-09 20:08:50 +0000