diff options
Diffstat (limited to 'test/MC/Disassembler')
33 files changed, 2819 insertions, 39 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 264a78a..471076a 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -201,7 +201,7 @@ 0x20 0x51 0x17 0xe6 # CHECK: strdeq r2, r3, [r0], -r8 -0xf8 0x24 0x00 0x00 +0xf8 0x20 0x00 0x00 # CHECK: ldrdeq r2, r3, [r0], -r12 0xdc 0x24 0x00 0x00 @@ -321,3 +321,6 @@ # CHECK: ldmgt sp!, {r9} 0x00 0x02 0xbd 0xc8 +# CHECK: cdp2 p10, #0, c6, c12, c0, #7 +0xe0 0x6a 0x0c 0xfe + diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt deleted file mode 100644 index 067dcb3..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. -0x10 0x51 0x37 0xe6 - - diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt new file mode 100644 index 0000000..aaae6ce --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: invalid instruction encoding +0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt new file mode 100644 index 0000000..8ff3a2b --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt new file mode 100644 index 0000000..bb87ade --- /dev/null +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE + +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.68 LDRD (register) +# if Rt{0} = 1 then UNDEFINED; + +# V4: invalid instruction encoding +# V5TE: ldrd +0xd0 0x10 0x00 0x01 + diff --git a/test/MC/Disassembler/ARM/lit.local.cfg b/test/MC/Disassembler/ARM/lit.local.cfg index c5dd3fb..22a76e5 100644 --- a/test/MC/Disassembler/ARM/lit.local.cfg +++ b/test/MC/Disassembler/ARM/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.txt'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 998e9e8..c5dbee3 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -2061,3 +2061,222 @@ # CHECK: vst4.16 {d8, d10, d12, d14}, [r4] 0x8f 0x81 0x04 0xf4 # CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x0d 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4]! +0x4d 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4]! +0x8d 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4]! +0xcd 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4]! +0x06 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4], r6 +0x46 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4], r6 +0x86 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4], r6 +0xc6 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4], r6 +0x0d 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4]! +0x06 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x0d 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x0d 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x4d 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x8d 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x06 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x0d 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x0d 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x4f 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4] +0x8f 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4] +0xcf 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4] +0x0f 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4] +0x4f 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4] +0x8f 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4] +0x0f 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4] +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x4f 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4] +0x8f 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4] +0x0f 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4] +0x4d 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x46 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x8d 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x86 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x06 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x0f 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x0f 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x0f 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x0f 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11256967 +0x0f 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2] +0x4f 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2] +0x8f 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2] +0x0d 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2]! +0x4d 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2]! +0x8d 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2]! +0x03 0x0d 0xa2 0xf4 +# CHECK: vld2.8 {d0[], d1[]}, [r2], r3 +0x43 0x0d 0xa2 0xf4 +# CHECK: vld2.16 {d0[], d1[]}, [r2], r3 +0x83 0x0d 0xa2 0xf4 +# CHECK: vld2.32 {d0[], d1[]}, [r2], r3 +0x2f 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3] +0x6f 0x0d 0xa3 0xf4 +# CHECK: vld2.16 {d0[], d2[]}, [r3] +0xaf 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3] +0x2d 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3]! +0x6d 0x0d 0xa3 0xf4 +# CHECK: vld2.16 {d0[], d2[]}, [r3]! +0xad 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3]! +0x24 0x0d 0xa3 0xf4 +# CHECK: vld2.8 {d0[], d2[]}, [r3], r4 +0x64 0x0d 0xa3 0xf4 +0xa4 0x0d 0xa3 0xf4 +# CHECK: vld2.32 {d0[], d2[]}, [r3], r4 diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index f8e7dbe..65cd230 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1778,3 +1778,223 @@ # CHECK: vst4.16 {d8, d10, d12, d14}, [r4] 0x04 0xf9 0x8f 0x81 # CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x24 0xf9 0x0d 0x87 +# CHECK: vld1.8 {d8}, [r4]! +0x24 0xf9 0x4d 0x87 +# CHECK: vld1.16 {d8}, [r4]! +0x24 0xf9 0x8d 0x87 +# CHECK: vld1.32 {d8}, [r4]! +0x24 0xf9 0xcd 0x87 +# CHECK: vld1.64 {d8}, [r4]! +0x24 0xf9 0x06 0x87 +# CHECK: vld1.8 {d8}, [r4], r6 +0x24 0xf9 0x46 0x87 +# CHECK: vld1.16 {d8}, [r4], r6 +0x24 0xf9 0x86 0x87 +# CHECK: vld1.32 {d8}, [r4], r6 +0x24 0xf9 0xc6 0x87 +# CHECK: vld1.64 {d8}, [r4], r6 +0x24 0xf9 0x0d 0x8a +# CHECK: vld1.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x8a +# CHECK: vld1.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x8a +# CHECK: vld1.32 {d8, d9}, [r4]! +0x24 0xf9 0xcd 0x8a +# CHECK: vld1.64 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x8a +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x8a +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x8a +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0x24 0xf9 0xc6 0x8a +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0xcd 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x46 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x86 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0xc6 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x0d 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0xcd 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x46 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x86 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0xc6 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x89 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x24 0xf9 0x4d 0x89 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x24 0xf9 0x8d 0x89 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x24 0xf9 0x06 0x89 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x24 0xf9 0x46 0x89 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x24 0xf9 0x86 0x89 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x24 0xf9 0x0d 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x46 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x86 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x0d 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x46 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x86 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x4f 0x8a +# CHECK: vld1.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x8a +# CHECK: vld1.32 {d8, d9}, [r4] +0x24 0xf9 0xcf 0x8a +# CHECK: vld1.64 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x8a +# CHECK: vld1.8 {d8, d9}, [r4] +0x24 0xf9 0x4f 0x88 +# CHECK: vld2.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x88 +# CHECK: vld2.32 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x88 +# CHECK: vld2.8 {d8, d9}, [r4] +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x4f 0x89 +# CHECK: vld2.16 {d8, d10}, [r4] +0x24 0xf9 0x8f 0x89 +# CHECK: vld2.32 {d8, d10}, [r4] +0x24 0xf9 0x0f 0x89 +# CHECK: vld2.8 {d8, d10}, [r4] +0x24 0xf9 0x4d 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x46 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x8d 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x86 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0f 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x24 0xf9 0x4f 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x24 0xf9 0x8f 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x24 0xf9 0x0f 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x4f 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x8f 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x0f 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x24 0xf9 0x4f 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x24 0xf9 0x8f 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x24 0xf9 0x0f 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x4f 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x8f 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11256967 +0xa2 0xf9 0x0f 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2] +0xa2 0xf9 0x4f 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2] +0xa2 0xf9 0x8f 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2] +0xa2 0xf9 0x0d 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x4d 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x8d 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2]! +0xa2 0xf9 0x03 0x0d +# CHECK: vld2.8 {d0[], d1[]}, [r2], r3 +0xa2 0xf9 0x43 0x0d +# CHECK: vld2.16 {d0[], d1[]}, [r2], r3 +0xa2 0xf9 0x83 0x0d +# CHECK: vld2.32 {d0[], d1[]}, [r2], r3 +0xa3 0xf9 0x2f 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3] +0xa3 0xf9 0x6f 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3] +0xa3 0xf9 0xaf 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3] +0xa3 0xf9 0x2d 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3]! +0xa3 0xf9 0x6d 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3]! +0xa3 0xf9 0xad 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3]! +0xa3 0xf9 0x24 0x0d +# CHECK: vld2.8 {d0[], d2[]}, [r3], r4 +0xa3 0xf9 0x64 0x0d +# CHECK: vld2.16 {d0[], d2[]}, [r3], r4 +0xa3 0xf9 0xa4 0x0d +# CHECK: vld2.32 {d0[], d2[]}, [r3], r4 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 0000000..275bae2 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt new file mode 100644 index 0000000..635b66e --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xd1 0xf1 0x5f 0x01 +0xd1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xd1 0xe1 0x4f 0x01 +0xd1 0xe1 0x4f 0x01 + + diff --git a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt new file mode 100644 index 0000000..dac4390 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt @@ -0,0 +1,30 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x01 0x10 0x50 0x03 +0x01 0x10 0x50 0x03 + +# CHECK: potentially undefined +# CHECK: 0x82 0x10 0x50 0x01 +0x82 0x10 0x50 0x01 + +# CHECK: potentially undefined +# CHECK: 0x02 0x10 0x50 0x01 +0x02 0x10 0x50 0x01 + +# CHECK: potentially undefined +# CHECK: 0x1f 0x01 0x52 0x01 +0x1f 0x01 0x52 0x01 + +# CHECK: potentially undefined +# CHECK: 0x10 0x11 0x52 0x01 +0x10 0x11 0x52 0x01 + +# CHECK: potentially undefined +# CHECK: 0x10 0x0f 0x51 0x01 +0x10 0x0f 0x51 0x01 + +# CHECK: potentially undefined +# CHECK: 0x10 0x01 0x5f 0x01 +0x10 0x01 0x5f 0x01 + diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt new file mode 100644 index 0000000..ed5e350 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -0,0 +1,22 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xff 0x00 0xb9 0x00 +0xff 0x00 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0xf0 0xb9 0x00 +0xfb 0xf0 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x01 0xb9 0x00 +0xfb 0x01 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x00 0xbf 0x00 +0xfb 0x00 0xbf 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x90 0xb9 0x00 +0xfb 0x90 0xb9 0x00 + diff --git a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index f8f23ed..a8f54f7 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- @@ -7,4 +7,7 @@ # # A8.6.68 LDRD (register) # if Rt{0} = 1 then UNDEFINED; + +# CHECK: potentially undefined +# CHECK: 0xd0 0x10 0x00 0x00 0xd0 0x10 0x00 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt new file mode 100644 index 0000000..26b286d --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x00 0x10 0x51 0xfc +0x00 0x10 0x51 0xfc + +# CHECK: potentially undefined +# CHECK: 0x00 0xf0 0x41 0x0c +0x00 0xf0 0x41 0x0c + +# CHECK: potentially undefined +# CHECK: 0x00 0x00 0x4f 0x0c +0x00 0x00 0x4f 0x0c diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt new file mode 100644 index 0000000..3e472cd --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x0f 0x01 +0x00 0xf0 0x0f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x4f 0x01 +0x00 0xf0 0x4f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x01 0x01 +0x0f 0x0d 0x01 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x40 0x01 +0x0f 0x0d 0x40 0x01 + diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt new file mode 100644 index 0000000..3db86cc --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x93 0x12 0x01 0x00 +0x93 0x12 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x0f 0x01 0x00 +0x92 0x0f 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x9f 0x02 0x01 0x00 +0x9f 0x02 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x01 0x0f 0x00 +0x92 0x01 0x0f 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt new file mode 100644 index 0000000..8ec49ca --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: shadd16 r5, r7, r0 +0x10 0x51 0x37 0xe6 + + diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt new file mode 100644 index 0000000..64bb171 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt @@ -0,0 +1,26 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x9f 0x10 0x03 0x01 +0x9f 0x10 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0xf0 0x03 0x01 +0x90 0xf0 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x1f 0x03 0x01 +0x90 0x1f 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x0f 0x01 +0x90 0x10 0x0f 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x01 0x01 +0x90 0x10 0x01 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x00 0x01 +0x90 0x10 0x00 0x01 + diff --git a/test/MC/Disassembler/ARM/vfp4.txt b/test/MC/Disassembler/ARM/vfp4.txt new file mode 100644 index 0000000..4f2c732 --- /dev/null +++ b/test/MC/Disassembler/ARM/vfp4.txt @@ -0,0 +1,37 @@ +# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown --disassemble -mattr=+neon,+vfp4 | FileCheck %s + +# CHECK: vfma.f64 d16, d18, d17 +0xe2 0xee 0xa1 0x0b + +# CHECK: vfma.f32 s2, s4, s0 +0xa2 0xee 0x00 0x1a + +# CHECK: vfma.f32 d16, d18, d17 +0x42 0xef 0xb1 0x0c + +# CHECK: vfma.f32 q2, q4, q0 +0x08 0xef 0x50 0x4c + +# CHECK: vfnms.f64 d16, d18, d17 +0xd2 0xee 0xa1 0x0b + +# CHECK: vfnms.f32 s2, s4, s0 +0x92 0xee 0x00 0x1a + +# CHECK: vfms.f64 d16, d18, d17 +0xe2 0xee 0xe1 0x0b + +# CHECK: vfms.f32 s2, s4, s0 +0xa2 0xee 0x40 0x1a + +# CHECK: vfms.f32 d16, d18, d17 +0x62 0xef 0xb1 0x0c + +# CHECK: vfms.f32 q2, q4, q0 +0x28 0xef 0x50 0x4c + +# CHECK: vfnma.f64 d16, d18, d17 +0xd2 0xee 0xe1 0x0b + +# CHECK: vfnma.f32 s2, s4, s0 +0x92 0xee 0x40 0x1a diff --git a/test/MC/Disassembler/MBlaze/lit.local.cfg b/test/MC/Disassembler/MBlaze/lit.local.cfg index 766b980..3955b4e 100644 --- a/test/MC/Disassembler/MBlaze/lit.local.cfg +++ b/test/MC/Disassembler/MBlaze/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.txt'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'MBlaze' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt new file mode 100644 index 0000000..591d8c4 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -0,0 +1,421 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux + +# CHECK: abs.d $f12,$f14 +0x46 0x20 0x39 0x85 + +# CHECK: abs.s $f6,$f7 +0x46 0x00 0x39 0x85 + +# CHECK: add t1,a2,a3 +0x00 0xc7 0x48 0x20 + +# CHECK: add.d $f18,$f12,$f14 +0x46 0x27 0x32 0x40 + +# CHECK: add.s $f9,$f6,$f7 +0x46 0x07 0x32 0x40 + +# CHECK: addi t1,a2,17767 +0x20 0xc9 0x45 0x67 + +# CHECK: addiu t1,a2,-15001 +0x24 0xc9 0xc5 0x67 + +# CHECK: addu t1,a2,a3 +0x00 0xc7 0x48 0x21 + +# CHECK: and t1,a2,a3 +0x00 0xc7 0x48 0x24 + +# CHECK: andi t1,a2,0x4567 +0x30 0xc9 0x45 0x67 + +# CHECK: b 00000534 +0x10 0x00 0x01 0x4c + +# CHECK: bal 00000534 +0x04 0x11 0x01 0x4c + +# CHECK: bc1f 00000534 +0x45 0x00 0x01 0x4c + +# CHECK: bc1t 00000534 +0x45 0x01 0x01 0x4c + +# CHECK: beq t1,a2,00000534 +0x11 0x26 0x01 0x4c + +# CHECK: bgez a2,00000534 +0x04 0xc1 0x01 0x4c + +# CHECK: bgezal a2,00000534 +0x04 0xd1 0x01 0x4c + +# CHECK: bgtz a2,00000534 +0x1c 0xc0 0x01 0x4c + +# CHECK: blez a2,00000534 +0x18 0xc0 0x01 0x4c + +# CHECK: bne t1,a2,00000534 +0x15 0x26 0x01 0x4c + +# CHECK: c.eq.d $f12,$f14 +0x46 0x27 0x30 0x32 + +# CHECK: c.eq.s $f6,$f7 +0x46 0x07 0x30 0x32 + +# CHECK: c.f.d $f12,$f14 +0x46 0x27 0x30 0x30 + +# CHECK: c.f.s $f6,$f7 +0x46 0x07 0x30 0x30 + +# CHECK: c.le.d $f12,$f14 +0x46 0x27 0x30 0x3e + +# CHECK: c.le.s $f6,$f7 +0x46 0x07 0x30 0x3e + +# CHECK: c.lt.d $f12,$f14 +0x46 0x27 0x30 0x3c + +# CHECK: c.lt.s $f6,$f7 +0x46 0x07 0x30 0x3c + +# CHECK: c.nge.d $f12,$f14 +0x46 0x27 0x30 0x3d + +# CHECK: c.nge.s $f6,$f7 +0x46 0x07 0x30 0x3d + +# CHECK: c.ngl.d $f12,$f14 +0x46 0x27 0x30 0x3b + +# CHECK: c.ngl.s $f6,$f7 +0x46 0x07 0x30 0x3b + +# CHECK: c.ngle.d $f12,$f14 +0x46 0x27 0x30 0x39 + +# CHECK: c.ngle.s $f6,$f7 +0x46 0x07 0x30 0x39 + +# CHECK: c.ngt.d $f12,$f14 +0x46 0x27 0x30 0x3f + +# CHECK: c.ngt.s $f6,$f7 +0x46 0x07 0x30 0x3f + +# CHECK: c.ole.d $f12,$f14 +0x46 0x27 0x30 0x36 + +# CHECK: c.ole.s $f6,$f7 +0x46 0x07 0x30 0x36 + +# CHECK: c.olt.d $f12,$f14 +0x46 0x27 0x30 0x34 + +# CHECK: c.olt.s $f6,$f7 +0x46 0x07 0x30 0x34 + +# CHECK: c.seq.d $f12,$f14 +0x46 0x27 0x30 0x3a + +# CHECK: c.seq.s $f6,$f7 +0x46 0x07 0x30 0x3a + +# CHECK: c.sf.d $f12,$f14 +0x46 0x27 0x30 0x38 + +# CHECK: c.sf.s $f6,$f7 +0x46 0x07 0x30 0x38 + +# CHECK: c.ueq.d $f12,$f14 +0x46 0x27 0x30 0x33 + +# CHECK: c.ueq.s $f28,$f18 +0x46 0x12 0xe0 0x33 + +# CHECK: c.ule.d $f12,$f14 +0x46 0x27 0x30 0x37 + +# CHECK: c.ule.s $f6,$f7 +0x46 0x07 0x30 0x37 + +# CHECK: c.ult.d $f12,$f14 +0x46 0x27 0x30 0x35 + +# CHECK: c.ult.s $f6,$f7 +0x46 0x07 0x30 0x35 + +# CHECK: c.un.d $f12,$f14 +0x46 0x27 0x30 0x31 + +# CHECK: c.un.s $f6,$f7 +0x46 0x07 0x30 0x31 + +# CHECK: ceil.w.d $f12,$f14 +0x46 0x20 0x39 0x8e + +# CHECK: ceil.w.s $f6,$f7 +0x46 0x00 0x39 0x8e + +# CHECK: cfc1 a2,$7 +0x44 0x46 0x38 0x00 + +# CHECK: clo a2,a3 +0x70 0xe6 0x30 0x21 + +# CHECK: clz a2,a3 +0x70 0xe6 0x30 0x20 + +# CHECK: ctc1 a2,$7 +0x44 0xc6 0x38 0x00 + +# CHECK: cvt.d.s $f6,$f7 +0x46 0x00 0x38 0xa1 + +# CHECK: cvt.d.w $f12,$f14 +0x46 0x80 0x38 0xa1 + +# CHECK: cvt.l.d $f12,$f14 +0x46 0x20 0x39 0xa5 + +# CHECK: cvt.l.s $f6,$f7 +0x46 0x00 0x39 0xa5 + +# CHECK: cvt.s.d $f12,$f14 +0x46 0x20 0x39 0xa0 + +# CHECK: cvt.s.w $f6,$f7 +0x46 0x80 0x39 0xa0 + +# CHECK: cvt.w.d $f12,$f14 +0x46 0x20 0x39 0xa4 + +# CHECK: cvt.w.s $f6,$f7 +0x46 0x00 0x39 0xa4 + +# CHECK: floor.w.d $f12,$f14 +0x46 0x20 0x39 0x8f + +# CHECK: floor.w.s $f6,$f7 +0x46 0x00 0x39 0x8f + +# CHECK: j 00000530 +0x08 0x00 0x01 0x4c + +# CHECK: jal 00000530 +0x0c 0x00 0x01 0x4c + +# CHECK: jalr a2,a3 +0x00 0xe0 0xf8 0x09 + +# CHECK: jr a3 +0x00 0xe0 0x00 0x08 + +# CHECK: lb a0,9158(a1) +0x80 0xa4 0x23 0xc6 + +# CHECK: lbu a0,6(a1) +0x90 0xa4 0x00 0x06 + +# CHECK: ldc1 $f9,9158(a3) +0xd4 0xe9 0x23 0xc6 + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: li v1,17767 +0x24 0x03 0x45 0x67 + +# CHECK: ll t1,9158(a3) +0xc0 0xe9 0x23 0xc6 + +# CHECK: lui a2,0x4567 +0x3c 0x06 0x45 0x67 + +# CHECK: lw a0,24(a1) +0x8c 0xa4 0x00 0x18 + +# CHECK: lwc1 $f9,9158(a3) +0xc4 0xe9 0x23 0xc6 + +# CHECK: madd a2,a3 +0x70 0xc7 0x00 0x00 + +# CHECK: maddu a2,a3 +0x70 0xc7 0x00 0x01 + +# CHECK: mfc1 a2,$f7 +0x44 0x06 0x38 0x00 + +# CHECK: mfhi a1 +0x00 0x00 0x28 0x10 + +# CHECK: mflo a1 +0x00 0x00 0x28 0x12 + +# CHECK: mov.d $f6,$f7 +0x46 0x20 0x39 0x86 + +# CHECK: mov.s $f6,$f7 +0x46 0x00 0x39 0x86 + +# CHECK: move a2,a1 +0x00 0xa0 0x30 0x21 + +# CHECK: msub a2,a3 +0x70 0xc7 0x00 0x04 + +# CHECK: msubu a2,a3 +0x70 0xc7 0x00 0x05 + +# CHECK: mtc1 a2,$f7 +0x44 0x86 0x38 0x00 + +# CHECK: mthi a3 +0x00 0xe0 0x00 0x11 + +# CHECK: mtlo a3 +0x00 0xe0 0x00 0x13 + +# CHECK: mul.d $f9,$f12,$f14 +0x46 0x27 0x32 0x42 + +# CHECK: mul.s $f9,$f6,$f7 +0x46 0x07 0x32 0x42 + +# CHECK: mul t1,a2,a3 +0x70 0xc7 0x48 0x02 + +# CHECK: mult v1,a1 +0x00 0x65 0x00 0x18 + +# CHECK: multu v1,a1 +0x00 0x65 0x00 0x19 + +# CHECK: neg.d $f12,$f14 +0x46 0x20 0x39 0x87 + +# CHECK: neg.s $f6,$f7 +0x46 0x00 0x39 0x87 + +# CHECK: neg v1,a1 +0x00 0x05 0x18 0x22 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x00 0xc7 0x48 0x27 + +# CHECK: not v1,a1 +0x00 0xa0 0x18 0x27 + +# CHECK: or v1,v1,a1 +0x00 0x65 0x18 0x25 + +# CHECK: ori t1,a2,0x4567 +0x34 0xc9 0x45 0x67 + +# CHECK: rdhwr a2,$29 +0x7c 0x06 0xe8 0x3b + +# CHECK: round.w.d $f12,$f14 +0x46 0x20 0x39 0x8c + +# CHECK: round.w.s $f6,$f7 +0x46 0x00 0x39 0x8c + +# CHECK: sb a0,9158(a1) +0xa0 0xa4 0x23 0xc6 + +# CHECK: sb a0,6(a1) +0xa0 0xa4 0x00 0x06 + +# CHECK: sc t1,9158(a3) +0xe0 0xe9 0x23 0xc6 + +# CHECK: sdc1 $f9,9158(a3) +0xf4 0xe9 0x23 0xc6 + +# CHECK: sh a0,9158(a1) +0xa4 0xa4 0x23 0xc6 + +# CHECK: sll a0,v1,0x7 +0x00 0x03 0x21 0xc0 + +# CHECK: sllv v0,v1,a1 +0x00 0xa3 0x10 0x04 + +# CHECK: slt v1,v1,a1 +0x00 0x65 0x18 0x2a + +# CHECK: slti v1,v1,103 +0x28 0x63 0x00 0x67 + +# CHECK: sltiu v1,v1,103 +0x2c 0x63 0x00 0x67 + +# CHECK: sltu v1,v1,a1 +0x00 0x65 0x18 0x2b + +# CHECK: sqrt.d $f12,$f14 +0x46 0x20 0x39 0x84 + +# CHECK: sqrt.s $f6,$f7 +0x46 0x00 0x39 0x84 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: srav v0,v1,a1 +0x00 0xa3 0x10 0x07 + +# CHECK: srl a0,v1,0x7 +0x00 0x03 0x21 0xc2 + +# CHECK: srlv v0,v1,a1 +0x00 0xa3 0x10 0x06 + +# CHECK: sub.d $f9,$f12,$f14 +0x46 0x27 0x32 0x41 + +# CHECK: sub.s $f9,$f6,$f7 +0x46 0x07 0x32 0x41 + +# CHECK: sub t1,a2,a3 +0x00 0xc7 0x48 0x22 + +# CHECK: subu a0,v1,a1 +0x00 0x65 0x20 0x23 + +# CHECK: sw a0,24(a1) +0xac 0xa4 0x00 0x18 + +# CHECK: swc1 $f9,9158(a3) +0xe4 0xe9 0x23 0xc6 + +# CHECK: sync 0x7 +0x00 0x00 0x01 0xcf + +# CHECK: trunc.w.d $f12,$f14 +0x46 0x20 0x39 0x8d + +# CHECK: trunc.w.s $f6,$f7 +0x46 0x00 0x39 0x8d + +# CHECK: xor v1,v1,a1 +0x00 0x65 0x18 0x26 + +# CHECK: xori t1,a2,0x4567 +0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt new file mode 100644 index 0000000..a5a3cfd --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -0,0 +1,424 @@ +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux + +# CHECK: abs.d $f12,$f14 +0x85 0x39 0x20 0x46 + +# CHECK: abs.s $f6,$f7 +0x85 0x39 0x00 0x46 + +# CHECK: add t1,a2,a3 +0x20 0x48 0xc7 0x00 + +# CHECK: add.d $f18,$f12,$f14 +0x40 0x32 0x27 0x46 + +# CHECK: add.s $f9,$f6,$f7 +0x40 0x32 0x07 0x46 + +# CHECK: addi t1,a2,17767 +0x67 0x45 0xc9 0x20 + +# CHECK: addiu t1,a2,-15001 +0x67 0xc5 0xc9 0x24 + +# CHECK: addu t1,a2,a3 +0x21 0x48 0xc7 0x00 + +# CHECK: and t1,a2,a3 +0x24 0x48 0xc7 0x00 + +# CHECK: andi t1,a2,0x4567 +0x67 0x45 0xc9 0x30 + +# CHECK: b 00000534 +0x4c 0x01 0x00 0x10 + +# CHECK: bal 00000534 +0x4c 0x01 0x11 0x04 + +# CHECK: bc1f 00000534 +0x4c 0x01 0x00 0x45 + +# CHECK: bc1t 00000534 +0x4c 0x01 0x01 0x45 + +# CHECK: beq t1,a2,00000534 +0x4c 0x01 0x26 0x11 + +# CHECK: bgez a2,00000534 +0x4c 0x01 0xc1 0x04 + +# CHECK: bgezal a2,00000534 +0x4c 0x01 0xd1 0x04 + +# CHECK: bgtz a2,00000534 +0x4c 0x01 0xc0 0x1c + +# CHECK: blez a2,00000534 +0x4c 0x01 0xc0 0x18 + +# CHECK: bne t1,a2,00000534 +0x4c 0x01 0x26 0x15 + +# CHECK: c.eq.d $f12,$f14 +0x32 0x30 0x27 0x46 + +# CHECK: c.eq.s $f6,$f7 +0x32 0x30 0x07 0x46 + +# CHECK: c.f.d $f12,$f14 +0x30 0x30 0x27 0x46 + +# CHECK: c.f.s $f6,$f7 +0x30 0x30 0x07 0x46 + +# CHECK: c.le.d $f12,$f14 +0x3e 0x30 0x27 0x46 + +# CHECK: c.le.s $f6,$f7 +0x3e 0x30 0x07 0x46 + +# CHECK: c.lt.d $f12,$f14 +0x3c 0x30 0x27 0x46 + +# CHECK: c.lt.s $f6,$f7 +0x3c 0x30 0x07 0x46 + +# CHECK: c.nge.d $f12,$f14 +0x3d 0x30 0x27 0x46 + +# CHECK: c.nge.s $f6,$f7 +0x3d 0x30 0x07 0x46 + +# CHECK: c.ngl.d $f12,$f14 +0x3b 0x30 0x27 0x46 + +# CHECK: c.ngl.s $f6,$f7 +0x3b 0x30 0x07 0x46 + +# CHECK: c.ngle.d $f12,$f14 +0x39 0x30 0x27 0x46 + +# CHECK: c.ngle.s $f6,$f7 +0x39 0x30 0x07 0x46 + +# CHECK: c.ngt.d $f12,$f14 +0x3f 0x30 0x27 0x46 + +# CHECK: c.ngt.s $f6,$f7 +0x3f 0x30 0x07 0x46 + +# CHECK: c.ole.d $f12,$f14 +0x36 0x30 0x27 0x46 + +# CHECK: c.ole.s $f6,$f7 +0x36 0x30 0x07 0x46 + +# CHECK: c.olt.d $f12,$f14 +0x34 0x30 0x27 0x46 + +# CHECK: c.olt.s $f6,$f7 +0x34 0x30 0x07 0x46 + +# CHECK: c.seq.d $f12,$f14 +0x3a 0x30 0x27 0x46 + +# CHECK: c.seq.s $f6,$f7 +0x3a 0x30 0x07 0x46 + +# CHECK: c.sf.d $f12,$f14 +0x38 0x30 0x27 0x46 + +# CHECK: c.sf.s $f6,$f7 +0x38 0x30 0x07 0x46 + +# CHECK: c.ueq.d $f12,$f14 +0x33 0x30 0x27 0x46 + +# CHECK: c.ueq.s $f28,$f18 +0x33 0xe0 0x12 0x46 + +# CHECK: c.ule.d $f12,$f14 +0x37 0x30 0x27 0x46 + +# CHECK: c.ule.s $f6,$f7 +0x37 0x30 0x07 0x46 + +# CHECK: c.ult.d $f12,$f14 +0x35 0x30 0x27 0x46 + +# CHECK: c.ult.s $f6,$f7 +0x35 0x30 0x07 0x46 + +# CHECK: c.un.d $f12,$f14 +0x31 0x30 0x27 0x46 + +# CHECK: c.un.s $f6,$f7 +0x31 0x30 0x07 0x46 + +# CHECK: ceil.w.d $f12,$f14 +0x8e 0x38 0x20 0x46 + +# CHECK: ceil.w.s $f6,$f7 +0x8e 0x38 0x00 0x46 + +# CHECK: cfc1 a2,$7 +0x00 0x38 0x46 0x44 + +# CHECK: clo a2,a3 +0x21 0x30 0xe6 0x70 + +# CHECK: clz a2,a3 +0x20 0x30 0xe6 0x70 + +# CHECK: ctc1 a2,$7 +0x00 0x38 0xc6 0x44 + +# CHECK: cvt.d.s $f6,$f7 +0xa1 0x39 0x00 0x46 + +# CHECK: cvt.d.w $f12,$f14 +0xa1 0x39 0x80 0x46 + +# CHECK: cvt.l.d $f12,$f14 +0xa5 0x39 0x20 0x46 + +# CHECK: cvt.l.s $f6,$f7 +0xa5 0x39 0x00 0x46 + +# CHECK: cvt.s.d $f12,$f14 +0xa0 0x39 0x20 0x46 + +# CHECK: cvt.s.w $f6,$f7 +0xa0 0x39 0x80 0x46 + +# CHECK: cvt.w.d $f12,$f14 +0xa4 0x39 0x20 0x46 + +# CHECK: cvt.w.s $f6,$f7 +0xa4 0x39 0x00 0x46 + +# CHECK: floor.w.d $f12,$f14 +0x8f 0x39 0x20 0x46 + +# CHECK: floor.w.s $f6,$f7 +0x8f 0x39 0x00 0x46 + +# CHECK: j 00000530 +0x4c 0x01 0x00 0x08 + +# CHECK: jal 00000530 +0x4c 0x01 0x00 0x0c + +# CHECK: jalr a2,a3 +0x09 0xf8 0xe0 0x00 + +# CHECK: jr a3 +0x08 0x00 0xe0 0x00 + +# CHECK: lb a0,9158(a1) +0xc6 0x23 0xa4 0x80 + +# CHECK: lbu a0,6(a1) +0x06 0x00 0xa4 0x90 + +# CHECK: ldc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xd4 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: li v1,17767 +0x67 0x45 0x03 0x24 + +# CHECK: ll t1,9158(a3) +0xc6 0x23 0xe9 0xc0 + +# CHECK: lui a2,0x4567 +0x67 0x45 0x06 0x3c + +# CHECK: lw a0,24(a1) +0x18 0x00 0xa4 0x8c + +# CHECK lw at,-18316(v0) +0x74 0xb8 0x41 0x8c + +# CHECK: lwc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xc4 + +# CHECK: madd a2,a3 +0x00 0x00 0xc7 0x70 + +# CHECK: maddu a2,a3 +0x01 0x00 0xc7 0x70 + +# CHECK: mfc1 a2,$f7 +0x00 0x38 0x06 0x44 + +# CHECK: mfhi a1 +0x10 0x28 0x00 0x00 + +# CHECK: mflo a1 +0x12 0x28 0x00 0x00 + +# CHECK: mov.d $f12,$f14 +0x86 0x39 0x20 0x46 + +# CHECK: mov.s $f6,$f7 +0x86 0x39 0x00 0x46 + +# CHECK: move a2,a1 +0x21 0x30 0xa0 0x00 + +# CHECK: msub a2,a3 +0x04 0x00 0xc7 0x70 + +# CHECK: msubu a2,a3 +0x05 0x00 0xc7 0x70 + +# CHECK: mtc1 a2,$f7 +0x00 0x38 0x86 0x44 + +# CHECK: mthi a3 +0x11 0x00 0xe0 0x00 + +# CHECK: mtlo a3 +0x13 0x00 0xe0 0x00 + +# CHECK: mul.d $f9,$f12,$f14 +0x42 0x32 0x27 0x46 + +# CHECK: mul.s $f9,$f6,$f7 +0x42 0x32 0x07 0x46 + +# CHECK: mul t1,a2,a3 +0x02 0x48 0xc7 0x70 + +# CHECK: mult v1,a1 +0x18 0x00 0x65 0x00 + +# CHECK: multu v1,a1 +0x19 0x00 0x65 0x00 + +# CHECK: neg.d $f12,$f14 +0x87 0x39 0x20 0x46 + +# CHECK: neg.s $f6,$f7 +0x87 0x39 0x00 0x46 + +# CHECK: neg v1,a1 +0x22 0x18 0x05 0x00 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x27 0x48 0xc7 0x00 + +# CHECK: not v1,a1 +0x27 0x18 0xa0 0x00 + +# CHECK: or v1,v1,a1 +0x25 0x18 0x65 0x00 + +# CHECK: ori t1,a2,0x4567 +0x67 0x45 0xc9 0x34 + +# CHECK: rdhwr a2,$29 +0x3b 0xe8 0x06 0x7c + +# CHECK: round.w.d $f12,$f14 +0x8c 0x39 0x20 0x46 + +# CHECK: round.w.s $f6,$f7 +0x8c 0x39 0x00 0x46 + +# CHECK: sb a0,9158(a1) +0xc6 0x23 0xa4 0xa0 + +# CHECK: sb a0,6(a1) +0x06 0x00 0xa4 0xa0 + +# CHECK: sc t1,9158(a3) +0xc6 0x23 0xe9 0xe0 + +# CHECK: sdc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xf4 + +# CHECK: sh a0,9158(a1) +0xc6 0x23 0xa4 0xa4 + +# CHECK: sll a0,v1,0x7 +0xc0 0x21 0x03 0x00 + +# CHECK: sllv v0,v1,a1 +0x04 0x10 0xa3 0x00 + +# CHECK: slt v1,v1,a1 +0x2a 0x18 0x65 0x00 + +# CHECK: slti v1,v1,103 +0x67 0x00 0x63 0x28 + +# CHECK: sltiu v1,v1,103 +0x67 0x00 0x63 0x2c + +# CHECK: sltu v1,v1,a1 +0x2b 0x18 0x65 0x00 + +# CHECK: sqrt.d $f12,$f14 +0x84 0x39 0x20 0x46 + +# CHECK: sqrt.s $f6,$f7 +0x84 0x39 0x00 0x46 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: srav v0,v1,a1 +0x07 0x10 0xa3 0x00 + +# CHECK: srl a0,v1,0x7 +0xc2 0x21 0x03 0x00 + +# CHECK: srlv v0,v1,a1 +0x06 0x10 0xa3 0x00 + +# CHECK: sub.d $f9,$f12,$f14 +0x41 0x32 0x27 0x46 + +# CHECK: sub.s $f9,$f6,$f7 +0x41 0x32 0x07 0x46 + +# CHECK: sub t1,a2,a3 +0x22 0x48 0xc7 0x00 + +# CHECK: subu a0,v1,a1 +0x23 0x20 0x65 0x00 + +# CHECK: sw a0,24(a1) +0x18 0x00 0xa4 0xac + +# CHECK: swc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xe4 + +# CHECK: sync 0x7 +0xcf 0x01 0x00 0x00 + +# CHECK: trunc.w.d $f12,$f14 +0x8d 0x39 0x20 0x46 + +# CHECK: trunc.w.s $f6,$f7 +0x8d 0x39 0x00 0x46 + +# CHECK: xor v1,v1,a1 +0x26 0x18 0x65 0x00 + +# CHECK: xori t1,a2,0x4567 +0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt new file mode 100644 index 0000000..295ffd0 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -0,0 +1,439 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 + +# CHECK: abs.d $f12,$f14 +0x46 0x20 0x39 0x85 + +# CHECK: abs.s $f6,$f7 +0x46 0x00 0x39 0x85 + +# CHECK: add t1,a2,a3 +0x00 0xc7 0x48 0x20 + +# CHECK: add.d $f18,$f12,$f14 +0x46 0x27 0x32 0x40 + +# CHECK: add.s $f9,$f6,$f7 +0x46 0x07 0x32 0x40 + +# CHECK: addi t1,a2,17767 +0x20 0xc9 0x45 0x67 + +# CHECK: addiu t1,a2,-15001 +0x24 0xc9 0xc5 0x67 + +# CHECK: addu t1,a2,a3 +0x00 0xc7 0x48 0x21 + +# CHECK: and t1,a2,a3 +0x00 0xc7 0x48 0x24 + +# CHECK: andi t1,a2,0x4567 +0x30 0xc9 0x45 0x67 + +# CHECK: b 00000534 +0x10 0x00 0x01 0x4c + +# CHECK: bal 00000534 +0x04 0x11 0x01 0x4c + +# CHECK: bc1f 00000534 +0x45 0x00 0x01 0x4c + +# CHECK: bc1t 00000534 +0x45 0x01 0x01 0x4c + +# CHECK: beq t1,a2,00000534 +0x11 0x26 0x01 0x4c + +# CHECK: bgez a2,00000534 +0x04 0xc1 0x01 0x4c + +# CHECK: bgezal a2,00000534 +0x04 0xd1 0x01 0x4c + +# CHECK: bgtz a2,00000534 +0x1c 0xc0 0x01 0x4c + +# CHECK: blez a2,00000534 +0x18 0xc0 0x01 0x4c + +# CHECK: bne t1,a2,00000534 +0x15 0x26 0x01 0x4c + +# CHECK: c.eq.d $f12,$f14 +0x46 0x27 0x30 0x32 + +# CHECK: c.eq.s $f6,$f7 +0x46 0x07 0x30 0x32 + +# CHECK: c.f.d $f12,$f14 +0x46 0x27 0x30 0x30 + +# CHECK: c.f.s $f6,$f7 +0x46 0x07 0x30 0x30 + +# CHECK: c.le.d $f12,$f14 +0x46 0x27 0x30 0x3e + +# CHECK: c.le.s $f6,$f7 +0x46 0x07 0x30 0x3e + +# CHECK: c.lt.d $f12,$f14 +0x46 0x27 0x30 0x3c + +# CHECK: c.lt.s $f6,$f7 +0x46 0x07 0x30 0x3c + +# CHECK: c.nge.d $f12,$f14 +0x46 0x27 0x30 0x3d + +# CHECK: c.nge.s $f6,$f7 +0x46 0x07 0x30 0x3d + +# CHECK: c.ngl.d $f12,$f14 +0x46 0x27 0x30 0x3b + +# CHECK: c.ngl.s $f6,$f7 +0x46 0x07 0x30 0x3b + +# CHECK: c.ngle.d $f12,$f14 +0x46 0x27 0x30 0x39 + +# CHECK: c.ngle.s $f6,$f7 +0x46 0x07 0x30 0x39 + +# CHECK: c.ngt.d $f12,$f14 +0x46 0x27 0x30 0x3f + +# CHECK: c.ngt.s $f6,$f7 +0x46 0x07 0x30 0x3f + +# CHECK: c.ole.d $f12,$f14 +0x46 0x27 0x30 0x36 + +# CHECK: c.ole.s $f6,$f7 +0x46 0x07 0x30 0x36 + +# CHECK: c.olt.d $f12,$f14 +0x46 0x27 0x30 0x34 + +# CHECK: c.olt.s $f6,$f7 +0x46 0x07 0x30 0x34 + +# CHECK: c.seq.d $f12,$f14 +0x46 0x27 0x30 0x3a + +# CHECK: c.seq.s $f6,$f7 +0x46 0x07 0x30 0x3a + +# CHECK: c.sf.d $f12,$f14 +0x46 0x27 0x30 0x38 + +# CHECK: c.sf.s $f6,$f7 +0x46 0x07 0x30 0x38 + +# CHECK: c.ueq.d $f12,$f14 +0x46 0x27 0x30 0x33 + +# CHECK: c.ueq.s $f28,$f18 +0x46 0x12 0xe0 0x33 + +# CHECK: c.ule.d $f12,$f14 +0x46 0x27 0x30 0x37 + +# CHECK: c.ule.s $f6,$f7 +0x46 0x07 0x30 0x37 + +# CHECK: c.ult.d $f12,$f14 +0x46 0x27 0x30 0x35 + +# CHECK: c.ult.s $f6,$f7 +0x46 0x07 0x30 0x35 + +# CHECK: c.un.d $f12,$f14 +0x46 0x27 0x30 0x31 + +# CHECK: c.un.s $f6,$f7 +0x46 0x07 0x30 0x31 + +# CHECK: ceil.w.d $f12,$f14 +0x46 0x20 0x39 0x8e + +# CHECK: ceil.w.s $f6,$f7 +0x46 0x00 0x39 0x8e + +# CHECK: cfc1 a2,$7 +0x44 0x46 0x38 0x00 + +# CHECK: clo a2,a3 +0x70 0xe6 0x30 0x21 + +# CHECK: clz a2,a3 +0x70 0xe6 0x30 0x20 + +# CHECK: ctc1 a2,$7 +0x44 0xc6 0x38 0x00 + +# CHECK: cvt.d.s $f6,$f7 +0x46 0x00 0x38 0xa1 + +# CHECK: cvt.d.w $f12,$f14 +0x46 0x80 0x38 0xa1 + +# CHECK: cvt.l.d $f12,$f14 +0x46 0x20 0x39 0xa5 + +# CHECK: cvt.l.s $f6,$f7 +0x46 0x00 0x39 0xa5 + +# CHECK: cvt.s.d $f12,$f14 +0x46 0x20 0x39 0xa0 + +# CHECK: cvt.s.w $f6,$f7 +0x46 0x80 0x39 0xa0 + +# CHECK: cvt.w.d $f12,$f14 +0x46 0x20 0x39 0xa4 + +# CHECK: cvt.w.s $f6,$f7 +0x46 0x00 0x39 0xa4 + +# CHECK: floor.w.d $f12,$f14 +0x46 0x20 0x39 0x8f + +# CHECK: floor.w.s $f6,$f7 +0x46 0x00 0x39 0x8f + +# CHECK: ins s3,t1,0x6,0x7 +0x7d 0x33 0x61 0x84 + +# CHECK: j 00000530 +0x08 0x00 0x01 0x4c + +# CHECK: jal 00000530 +0x0c 0x00 0x01 0x4c + +# CHECK: jalr a2,a3 +0x00 0xe0 0xf8 0x09 + +# CHECK: jr a3 +0x00 0xe0 0x00 0x08 + +# CHECK: lb a0,9158(a1) +0x80 0xa4 0x23 0xc6 + +# CHECK: lbu a0,6(a1) +0x90 0xa4 0x00 0x06 + +# CHECK: ldc1 $f9,9158(a3) +0xd4 0xe9 0x23 0xc6 + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: lh a0,12(a1) +0x84 0xa4 0x00 0x0c + +# CHECK: li v1,17767 +0x24 0x03 0x45 0x67 + +# CHECK: ll t1,9158(a3) +0xc0 0xe9 0x23 0xc6 + +# CHECK: lui a2,0x4567 +0x3c 0x06 0x45 0x67 + +# CHECK: lw a0,24(a1) +0x8c 0xa4 0x00 0x18 + +# CHECK: lwc1 $f9,9158(a3) +0xc4 0xe9 0x23 0xc6 + +# CHECK: madd a2,a3 +0x70 0xc7 0x00 0x00 + +# CHECK: maddu a2,a3 +0x70 0xc7 0x00 0x01 + +# CHECK: mfc1 a2,$f7 +0x44 0x06 0x38 0x00 + +# CHECK: mfhi a1 +0x00 0x00 0x28 0x10 + +# CHECK: mflo a1 +0x00 0x00 0x28 0x12 + +# CHECK: mov.d $f6,$f7 +0x46 0x20 0x39 0x86 + +# CHECK: mov.s $f6,$f7 +0x46 0x00 0x39 0x86 + +# CHECK: move a2,a1 +0x00 0xa0 0x30 0x21 + +# CHECK: msub a2,a3 +0x70 0xc7 0x00 0x04 + +# CHECK: msubu a2,a3 +0x70 0xc7 0x00 0x05 + +# CHECK: mtc1 a2,$f7 +0x44 0x86 0x38 0x00 + +# CHECK: mthi a3 +0x00 0xe0 0x00 0x11 + +# CHECK: mtlo a3 +0x00 0xe0 0x00 0x13 + +# CHECK: mul.d $f9,$f12,$f14 +0x46 0x27 0x32 0x42 + +# CHECK: mul.s $f9,$f6,$f7 +0x46 0x07 0x32 0x42 + +# CHECK: mul t1,a2,a3 +0x70 0xc7 0x48 0x02 + +# CHECK: mult v1,a1 +0x00 0x65 0x00 0x18 + +# CHECK: multu v1,a1 +0x00 0x65 0x00 0x19 + +# CHECK: neg.d $f12,$f14 +0x46 0x20 0x39 0x87 + +# CHECK: neg.s $f6,$f7 +0x46 0x00 0x39 0x87 + +# CHECK: neg v1,a1 +0x00 0x05 0x18 0x22 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x00 0xc7 0x48 0x27 + +# CHECK: not v1,a1 +0x00 0xa0 0x18 0x27 + +# CHECK: or v1,v1,a1 +0x00 0x65 0x18 0x25 + +# CHECK: ori t1,a2,0x4567 +0x34 0xc9 0x45 0x67 + +# CHECK: rdhwr a2,$29 +0x7c 0x06 0xe8 0x3b + +# CHECK: ror t1,a2,0x7 +0x00 0x26 0x49 0xc2 + +# CHECK: rorv t1,a2,a3 +0x00 0xe6 0x48 0x46 + +# CHECK: round.w.d $f12,$f14 +0x46 0x20 0x39 0x8c + +# CHECK: round.w.s $f6,$f7 +0x46 0x00 0x39 0x8c + +# CHECK: sb a0,9158(a1) +0xa0 0xa4 0x23 0xc6 + +# CHECK: sb a0,6(a1) +0xa0 0xa4 0x00 0x06 + +# CHECK: sc t1,9158(a3) +0xe0 0xe9 0x23 0xc6 + +# CHECK: sdc1 $f9,9158(a3) +0xf4 0xe9 0x23 0xc6 + +# CHECK: seb a2,a3 +0x7c 0x07 0x34 0x20 + +# CHECK: seh a2,a3 +0x7c 0x07 0x36 0x20 + +# CHECK: sh a0,9158(a1) +0xa4 0xa4 0x23 0xc6 + +# CHECK: sll a0,v1,0x7 +0x00 0x03 0x21 0xc0 + +# CHECK: sllv v0,v1,a1 +0x00 0xa3 0x10 0x04 + +# CHECK: slt v1,v1,a1 +0x00 0x65 0x18 0x2a + +# CHECK: slti v1,v1,103 +0x28 0x63 0x00 0x67 + +# CHECK: sltiu v1,v1,103 +0x2c 0x63 0x00 0x67 + +# CHECK: sltu v1,v1,a1 +0x00 0x65 0x18 0x2b + +# CHECK: sqrt.d $f12,$f14 +0x46 0x20 0x39 0x84 + +# CHECK: sqrt.s $f6,$f7 +0x46 0x00 0x39 0x84 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: sra a0,v1,0x7 +0x00 0x03 0x21 0xc3 + +# CHECK: srav v0,v1,a1 +0x00 0xa3 0x10 0x07 + +# CHECK: srl a0,v1,0x7 +0x00 0x03 0x21 0xc2 + +# CHECK: srlv v0,v1,a1 +0x00 0xa3 0x10 0x06 + +# CHECK: sub.d $f9,$f12,$f14 +0x46 0x27 0x32 0x41 + +# CHECK: sub.s $f9,$f6,$f7 +0x46 0x07 0x32 0x41 + +# CHECK: sub t1,a2,a3 +0x00 0xc7 0x48 0x22 + +# CHECK: subu a0,v1,a1 +0x00 0x65 0x20 0x23 + +# CHECK: sw a0,24(a1) +0xac 0xa4 0x00 0x18 + +# CHECK: swc1 $f9,9158(a3) +0xe4 0xe9 0x23 0xc6 + +# CHECK: sync 0x7 +0x00 0x00 0x01 0xcf + +# CHECK: trunc.w.d $f12,$f14 +0x46 0x20 0x39 0x8d + +# CHECK: trunc.w.s $f6,$f7 +0x46 0x00 0x39 0x8d + +# CHECK: wsbh a2,a3 +0x7c 0x07 0x30 0xa0 + +# CHECK: xor v1,v1,a1 +0x00 0x65 0x18 0x26 + +# CHECK: xori t1,a2,0x4567 +0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt new file mode 100644 index 0000000..6d8be79 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -0,0 +1,442 @@ +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 + +# CHECK: abs.d $f12,$f14 +0x85 0x39 0x20 0x46 + +# CHECK: abs.s $f6,$f7 +0x85 0x39 0x00 0x46 + +# CHECK: add t1,a2,a3 +0x20 0x48 0xc7 0x00 + +# CHECK: add.d $f18,$f12,$f14 +0x40 0x32 0x27 0x46 + +# CHECK: add.s $f9,$f6,$f7 +0x40 0x32 0x07 0x46 + +# CHECK: addi t1,a2,17767 +0x67 0x45 0xc9 0x20 + +# CHECK: addiu t1,a2,-15001 +0x67 0xc5 0xc9 0x24 + +# CHECK: addu t1,a2,a3 +0x21 0x48 0xc7 0x00 + +# CHECK: and t1,a2,a3 +0x24 0x48 0xc7 0x00 + +# CHECK: andi t1,a2,0x4567 +0x67 0x45 0xc9 0x30 + +# CHECK: b 00000534 +0x4c 0x01 0x00 0x10 + +# CHECK: bal 00000534 +0x4c 0x01 0x11 0x04 + +# CHECK: bc1f 00000534 +0x4c 0x01 0x00 0x45 + +# CHECK: bc1t 00000534 +0x4c 0x01 0x01 0x45 + +# CHECK: beq t1,a2,00000534 +0x4c 0x01 0x26 0x11 + +# CHECK: bgez a2,00000534 +0x4c 0x01 0xc1 0x04 + +# CHECK: bgezal a2,00000534 +0x4c 0x01 0xd1 0x04 + +# CHECK: bgtz a2,00000534 +0x4c 0x01 0xc0 0x1c + +# CHECK: blez a2,00000534 +0x4c 0x01 0xc0 0x18 + +# CHECK: bne t1,a2,00000534 +0x4c 0x01 0x26 0x15 + +# CHECK: c.eq.d $f12,$f14 +0x32 0x30 0x27 0x46 + +# CHECK: c.eq.s $f6,$f7 +0x32 0x30 0x07 0x46 + +# CHECK: c.f.d $f12,$f14 +0x30 0x30 0x27 0x46 + +# CHECK: c.f.s $f6,$f7 +0x30 0x30 0x07 0x46 + +# CHECK: c.le.d $f12,$f14 +0x3e 0x30 0x27 0x46 + +# CHECK: c.le.s $f6,$f7 +0x3e 0x30 0x07 0x46 + +# CHECK: c.lt.d $f12,$f14 +0x3c 0x30 0x27 0x46 + +# CHECK: c.lt.s $f6,$f7 +0x3c 0x30 0x07 0x46 + +# CHECK: c.nge.d $f12,$f14 +0x3d 0x30 0x27 0x46 + +# CHECK: c.nge.s $f6,$f7 +0x3d 0x30 0x07 0x46 + +# CHECK: c.ngl.d $f12,$f14 +0x3b 0x30 0x27 0x46 + +# CHECK: c.ngl.s $f6,$f7 +0x3b 0x30 0x07 0x46 + +# CHECK: c.ngle.d $f12,$f14 +0x39 0x30 0x27 0x46 + +# CHECK: c.ngle.s $f6,$f7 +0x39 0x30 0x07 0x46 + +# CHECK: c.ngt.d $f12,$f14 +0x3f 0x30 0x27 0x46 + +# CHECK: c.ngt.s $f6,$f7 +0x3f 0x30 0x07 0x46 + +# CHECK: c.ole.d $f12,$f14 +0x36 0x30 0x27 0x46 + +# CHECK: c.ole.s $f6,$f7 +0x36 0x30 0x07 0x46 + +# CHECK: c.olt.d $f12,$f14 +0x34 0x30 0x27 0x46 + +# CHECK: c.olt.s $f6,$f7 +0x34 0x30 0x07 0x46 + +# CHECK: c.seq.d $f12,$f14 +0x3a 0x30 0x27 0x46 + +# CHECK: c.seq.s $f6,$f7 +0x3a 0x30 0x07 0x46 + +# CHECK: c.sf.d $f12,$f14 +0x38 0x30 0x27 0x46 + +# CHECK: c.sf.s $f6,$f7 +0x38 0x30 0x07 0x46 + +# CHECK: c.ueq.d $f12,$f14 +0x33 0x30 0x27 0x46 + +# CHECK: c.ueq.s $f28,$f18 +0x33 0xe0 0x12 0x46 + +# CHECK: c.ule.d $f12,$f14 +0x37 0x30 0x27 0x46 + +# CHECK: c.ule.s $f6,$f7 +0x37 0x30 0x07 0x46 + +# CHECK: c.ult.d $f12,$f14 +0x35 0x30 0x27 0x46 + +# CHECK: c.ult.s $f6,$f7 +0x35 0x30 0x07 0x46 + +# CHECK: c.un.d $f12,$f14 +0x31 0x30 0x27 0x46 + +# CHECK: c.un.s $f6,$f7 +0x31 0x30 0x07 0x46 + +# CHECK: ceil.w.d $f12,$f14 +0x8e 0x38 0x20 0x46 + +# CHECK: ceil.w.s $f6,$f7 +0x8e 0x38 0x00 0x46 + +# CHECK: cfc1 a2,$7 +0x00 0x38 0x46 0x44 + +# CHECK: clo a2,a3 +0x21 0x30 0xe6 0x70 + +# CHECK: clz a2,a3 +0x20 0x30 0xe6 0x70 + +# CHECK: ctc1 a2,$7 +0x00 0x38 0xc6 0x44 + +# CHECK: cvt.d.s $f6,$f7 +0xa1 0x39 0x00 0x46 + +# CHECK: cvt.d.w $f12,$f14 +0xa1 0x39 0x80 0x46 + +# CHECK: cvt.l.d $f12,$f14 +0xa5 0x39 0x20 0x46 + +# CHECK: cvt.l.s $f6,$f7 +0xa5 0x39 0x00 0x46 + +# CHECK: cvt.s.d $f12,$f14 +0xa0 0x39 0x20 0x46 + +# CHECK: cvt.s.w $f6,$f7 +0xa0 0x39 0x80 0x46 + +# CHECK: cvt.w.d $f12,$f14 +0xa4 0x39 0x20 0x46 + +# CHECK: cvt.w.s $f6,$f7 +0xa4 0x39 0x00 0x46 + +# CHECK: floor.w.d $f12,$f14 +0x8f 0x39 0x20 0x46 + +# CHECK: floor.w.s $f6,$f7 +0x8f 0x39 0x00 0x46 + +# CHECK: ins s3,t1,0x6,0x7 +0x84 0x61 0x33 0x7d + +# CHECK: j 00000530 +0x4c 0x01 0x00 0x08 + +# CHECK: jal 00000530 +0x4c 0x01 0x00 0x0c + +# CHECK: jalr a2,a3 +0x09 0xf8 0xe0 0x00 + +# CHECK: jr a3 +0x08 0x00 0xe0 0x00 + +# CHECK: lb a0,9158(a1) +0xc6 0x23 0xa4 0x80 + +# CHECK: lbu a0,6(a1) +0x06 0x00 0xa4 0x90 + +# CHECK: ldc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xd4 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: lh a0,12(a1) +0x0c 0x00 0xa4 0x84 + +# CHECK: li v1,17767 +0x67 0x45 0x03 0x24 + +# CHECK: ll t1,9158(a3) +0xc6 0x23 0xe9 0xc0 + +# CHECK: lui a2,0x4567 +0x67 0x45 0x06 0x3c + +# CHECK: lw a0,24(a1) +0x18 0x00 0xa4 0x8c + +# CHECK lw at,-18316(v0) +0x74 0xb8 0x41 0x8c + +# CHECK: lwc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xc4 + +# CHECK: madd a2,a3 +0x00 0x00 0xc7 0x70 + +# CHECK: maddu a2,a3 +0x01 0x00 0xc7 0x70 + +# CHECK: mfc1 a2,$f7 +0x00 0x38 0x06 0x44 + +# CHECK: mfhi a1 +0x10 0x28 0x00 0x00 + +# CHECK: mflo a1 +0x12 0x28 0x00 0x00 + +# CHECK: mov.d $f12,$f14 +0x86 0x39 0x20 0x46 + +# CHECK: mov.s $f6,$f7 +0x86 0x39 0x00 0x46 + +# CHECK: move a2,a1 +0x21 0x30 0xa0 0x00 + +# CHECK: msub a2,a3 +0x04 0x00 0xc7 0x70 + +# CHECK: msubu a2,a3 +0x05 0x00 0xc7 0x70 + +# CHECK: mtc1 a2,$f7 +0x00 0x38 0x86 0x44 + +# CHECK: mthi a3 +0x11 0x00 0xe0 0x00 + +# CHECK: mtlo a3 +0x13 0x00 0xe0 0x00 + +# CHECK: mul.d $f9,$f12,$f14 +0x42 0x32 0x27 0x46 + +# CHECK: mul.s $f9,$f6,$f7 +0x42 0x32 0x07 0x46 + +# CHECK: mul t1,a2,a3 +0x02 0x48 0xc7 0x70 + +# CHECK: mult v1,a1 +0x18 0x00 0x65 0x00 + +# CHECK: multu v1,a1 +0x19 0x00 0x65 0x00 + +# CHECK: neg.d $f12,$f14 +0x87 0x39 0x20 0x46 + +# CHECK: neg.s $f6,$f7 +0x87 0x39 0x00 0x46 + +# CHECK: neg v1,a1 +0x22 0x18 0x05 0x00 + +# CHECK: nop +0x00 0x00 0x00 0x00 + +# CHECK: nor t1,a2,a3 +0x27 0x48 0xc7 0x00 + +# CHECK: not v1,a1 +0x27 0x18 0xa0 0x00 + +# CHECK: or v1,v1,a1 +0x25 0x18 0x65 0x00 + +# CHECK: ori t1,a2,0x4567 +0x67 0x45 0xc9 0x34 + +# CHECK: rdhwr a2,$29 +0x3b 0xe8 0x06 0x7c + +# CHECK: ror t1,a2,0x7 +0xc2 0x49 0x26 0x00 + +# CHECK: rorv t1,a2,a3 +0x46 0x48 0xe6 0x00 + +# CHECK: round.w.d $f12,$f14 +0x8c 0x39 0x20 0x46 + +# CHECK: round.w.s $f6,$f7 +0x8c 0x39 0x00 0x46 + +# CHECK: sb a0,9158(a1) +0xc6 0x23 0xa4 0xa0 + +# CHECK: sb a0,6(a1) +0x06 0x00 0xa4 0xa0 + +# CHECK: sc t1,9158(a3) +0xc6 0x23 0xe9 0xe0 + +# CHECK: sdc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xf4 + +# CHECK: seb a2,a3 +0x20 0x34 0x07 0x7c + +# CHECK: seh a2,a3 +0x20 0x36 0x07 0x7c + +# CHECK: sh a0,9158(a1) +0xc6 0x23 0xa4 0xa4 + +# CHECK: sll a0,v1,0x7 +0xc0 0x21 0x03 0x00 + +# CHECK: sllv v0,v1,a1 +0x04 0x10 0xa3 0x00 + +# CHECK: slt v1,v1,a1 +0x2a 0x18 0x65 0x00 + +# CHECK: slti v1,v1,103 +0x67 0x00 0x63 0x28 + +# CHECK: sltiu v1,v1,103 +0x67 0x00 0x63 0x2c + +# CHECK: sltu v1,v1,a1 +0x2b 0x18 0x65 0x00 + +# CHECK: sqrt.d $f12,$f14 +0x84 0x39 0x20 0x46 + +# CHECK: sqrt.s $f6,$f7 +0x84 0x39 0x00 0x46 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: sra a0,v1,0x7 +0xc3 0x21 0x03 0x00 + +# CHECK: srav v0,v1,a1 +0x07 0x10 0xa3 0x00 + +# CHECK: srl a0,v1,0x7 +0xc2 0x21 0x03 0x00 + +# CHECK: srlv v0,v1,a1 +0x06 0x10 0xa3 0x00 + +# CHECK: sub.d $f9,$f12,$f14 +0x41 0x32 0x27 0x46 + +# CHECK: sub.s $f9,$f6,$f7 +0x41 0x32 0x07 0x46 + +# CHECK: sub t1,a2,a3 +0x22 0x48 0xc7 0x00 + +# CHECK: subu a0,v1,a1 +0x23 0x20 0x65 0x00 + +# CHECK: sw a0,24(a1) +0x18 0x00 0xa4 0xac + +# CHECK: swc1 $f9,9158(a3) +0xc6 0x23 0xe9 0xe4 + +# CHECK: sync 0x7 +0xcf 0x01 0x00 0x00 + +# CHECK: trunc.w.d $f12,$f14 +0x8d 0x39 0x20 0x46 + +# CHECK: trunc.w.s $f6,$f7 +0x8d 0x39 0x00 0x46 + +# CHECK: wsbh a2,a3 +0xa0 0x30 0x07 0x7c + +# CHECK: xor v1,v1,a1 +0x26 0x18 0x65 0x00 + +# CHECK: xori t1,a2,0x4567 +0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt new file mode 100644 index 0000000..1c7447a --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -0,0 +1,67 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux
+
+# CHECK: daddiu t3,k0,31949
+0x67 0x4b 0x7c 0xcd
+
+# CHECK: daddu k0,at,t3
+0x00 0x2b 0xd0 0x2d
+
+# CHECK: ddiv zero,k0,s6
+0x03 0x56 0x00 0x1e
+
+# CHECK: ddivu zero,t1,t8
+0x01 0x38 0x00 0x1f
+
+# CHECK: dmfc1 v0,$f14
+0x44 0x22 0x70 0x00
+
+# CHECK: dmtc1 s7,$f5
+0x44 0xb7 0x28 0x00
+
+# CHECK: dmult t3,k0
+0x01 0x7a 0x00 0x1c
+
+# CHECK: dmultu s7,t5
+0x02 0xed 0x00 0x1d
+
+# CHECK: dsll v1,t8,0x11
+0x00 0x18 0x1c 0x78
+
+# CHECK: dsllv gp,k1,t8
+0x03 0x1b 0xe0 0x14
+
+# CHECK: dsra at,at,0x1e
+0x00 0x01 0x0f 0xbb
+
+# CHECK: dsrav at,at,s8
+0x03 0xc1 0x08 0x17
+
+# CHECK: dsrl t2,gp,0x18
+0x00 0x1c 0x56 0x3a
+
+# CHECK: dsrlv gp,t2,s7
+0x02 0xea 0xe0 0x16
+
+# CHECK: dsubu gp,k1,t8
+0x03 0x78 0xe0 0x2f
+
+# CHECK: lw k1,-15155(at)
+0x8c 0x3b 0xc4 0xcd
+
+# CHECK: lui at,0x1
+0x3c 0x01 0x00 0x01
+
+# CHECK: lwu v1,-1746(v1)
+0x9c 0x63 0xf9 0x2e
+
+# CHECK: lui ra,0x1
+0x3c 0x1f 0x00 0x01
+
+# CHECK: sw k0,-15159(at)
+0xac 0x3a 0xc4 0xc9
+
+# CHECK: ld k0,3958(zero)
+0xdc 0x1a 0x0f 0x76
+
+# CHECK: sd a2,17767(zero)
+0xfc 0x06 0x45 0x67
diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt new file mode 100644 index 0000000..dd87522 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -0,0 +1,67 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux
+
+# CHECK: daddiu t3,k0,31949
+0xcd 0x7c 0x4b 0x67
+
+# CHECK: daddu k0,at,t3
+0x2d 0xd0 0x2b 0x00
+
+# CHECK: ddiv zero,k0,s6
+0x1e 0x00 0x56 0x03
+
+# CHECK: ddivu zero,t1,t8
+0x1f 0x00 0x38 0x01
+
+# CHECK: dmfc1 v0,$f14
+0x00 0x70 0x22 0x44
+
+# CHECK: dmtc1 s7,$f5
+0x00 0x28 0xb7 0x44
+
+# CHECK: dmult t3,k0
+0x1c 0x00 0x7a 0x01
+
+# CHECK: dmultu s7,t5
+0x1d 0x00 0xed 0x02
+
+# CHECK: dsll v1,t8,0x11
+0x78 0x1c 0x18 0x00
+
+# CHECK: dsllv gp,k1,t8
+0x14 0xe0 0x1b 0x03
+
+# CHECK: dsra at,at,0x1e
+0xbb 0x0f 0x01 0x00
+
+# CHECK: dsrav at,at,s8
+0x17 0x08 0xc1 0x03
+
+# CHECK: dsrl t2,gp,0x18
+0x3a 0x56 0x1c 0x00
+
+# CHECK: dsrlv gp,t2,s7
+0x16 0xe0 0xea 0x02
+
+# CHECK: dsubu gp,k1,t8
+0x2f 0xe0 0x78 0x03
+
+# CHECK: lw k1,-15155(at)
+0xcd 0xc4 0x3b 0x8c
+
+# CHECK: lui at,0x1
+0x01 0x00 0x01 0x3c
+
+# CHECK: lwu v1,-1746(v1)
+0x2e 0xf9 0x63 0x9c
+
+# CHECK: lui ra,0x1
+0x01 0x00 0x1f 0x3c
+
+# CHECK: sw k0,-15159(at)
+0xc9 0xc4 0x3a 0xac
+
+# CHECK: ld k0,3958(zero)
+0x76 0x0f 0x1a 0xdc
+
+# CHECK: sd a2,17767(zero)
+0x67 0x45 0x06 0xfc
diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt new file mode 100644 index 0000000..26bc94d --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -0,0 +1,91 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2
+
+# CHECK: daddiu t3,k0,31949
+0x67 0x4b 0x7c 0xcd
+
+# CHECK: daddu k0,at,t3
+0x00 0x2b 0xd0 0x2d
+
+# CHECK: ddiv zero,k0,s6
+0x03 0x56 0x00 0x1e
+
+# CHECK: ddivu zero,t1,t8
+0x01 0x38 0x00 0x1f
+
+# CHECK: dmfc1 v0,$f14
+0x44 0x22 0x70 0x00
+
+# CHECK: dmtc1 s7,$f5
+0x44 0xb7 0x28 0x00
+
+# CHECK: dmult t3,k0
+0x01 0x7a 0x00 0x1c
+
+# CHECK: dmultu s7,t5
+0x02 0xed 0x00 0x1d
+
+# CHECK: dsll v1,t8,0x11
+0x00 0x18 0x1c 0x78
+
+# CHECK: dsllv gp,k1,t8
+0x03 0x1b 0xe0 0x14
+
+# CHECK: dsra at,at,0x1e
+0x00 0x01 0x0f 0xbb
+
+# CHECK: dsrav at,at,s8
+0x03 0xc1 0x08 0x17
+
+# CHECK: dsrl t2,gp,0x18
+0x00 0x1c 0x56 0x3a
+
+# CHECK: dsrlv gp,t2,s7
+0x02 0xea 0xe0 0x16
+
+# CHECK: dsubu gp,k1,t8
+0x03 0x78 0xe0 0x2f
+
+# CHECK: lw k1,-15155(at)
+0x8c 0x3b 0xc4 0xcd
+
+# CHECK: lui at,0x1
+0x3c 0x01 0x00 0x01
+
+# CHECK: lwu v1,-1746(v1)
+0x9c 0x63 0xf9 0x2e
+
+# CHECK: lui ra,0x1
+0x3c 0x1f 0x00 0x01
+
+# CHECK: sw k0,-15159(at)
+0xac 0x3a 0xc4 0xc9
+
+# CHECK: ld k0,3958(zero)
+0xdc 0x1a 0x0f 0x76
+
+# CHECK: sd a2,17767(zero)
+0xfc 0x06 0x45 0x67
+
+# CHECK: dclo t1,t8
+0x73 0x09 0x48 0x25
+
+# CHECK: dclz k0,t1
+0x71 0x3a 0xd0 0x24
+
+# CHECK: dext a3,gp,0x1d,0x1f
+0x7f 0x87 0xf7 0x43
+
+# CHECK: dins s4,gp,0xf,0x1
+0x7f 0x94 0x7b 0xc7
+
+# CHECK: dsbh a3,gp
+0x7c 0x1c 0x38 0xa4
+
+# CHECK: dshd v1,t6
+0x7c 0x0e 0x19 0x64
+
+# CHECK: drotr s4,k1,0x6
+0x00 0x3b 0xa1 0xba
+
+# CHECK: drotrv t8,s7,a1
+0x00 0xb7 0xc0 0x56
diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt new file mode 100644 index 0000000..81a7c66 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -0,0 +1,91 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2
+
+# CHECK: daddiu t3,k0,31949
+0xcd 0x7c 0x4b 0x67
+
+# CHECK: daddu k0,at,t3
+0x2d 0xd0 0x2b 0x00
+
+# CHECK: ddiv zero,k0,s6
+0x1e 0x00 0x56 0x03
+
+# CHECK: ddivu zero,t1,t8
+0x1f 0x00 0x38 0x01
+
+# CHECK: dmfc1 v0,$f14
+0x00 0x70 0x22 0x44
+
+# CHECK: dmtc1 s7,$f5
+0x00 0x28 0xb7 0x44
+
+# CHECK: dmult t3,k0
+0x1c 0x00 0x7a 0x01
+
+# CHECK: dmultu s7,t5
+0x1d 0x00 0xed 0x02
+
+# CHECK: dsll v1,t8,0x11
+0x78 0x1c 0x18 0x00
+
+# CHECK: dsllv gp,k1,t8
+0x14 0xe0 0x1b 0x03
+
+# CHECK: dsra at,at,0x1e
+0xbb 0x0f 0x01 0x00
+
+# CHECK: dsrav at,at,s8
+0x17 0x08 0xc1 0x03
+
+# CHECK: dsrl t2,gp,0x18
+0x3a 0x56 0x1c 0x00
+
+# CHECK: dsrlv gp,t2,s7
+0x16 0xe0 0xea 0x02
+
+# CHECK: dsubu gp,k1,t8
+0x2f 0xe0 0x78 0x03
+
+# CHECK: lw k1,-15155(at)
+0xcd 0xc4 0x3b 0x8c
+
+# CHECK: lui at,0x1
+0x01 0x00 0x01 0x3c
+
+# CHECK: lwu v1,-1746(v1)
+0x2e 0xf9 0x63 0x9c
+
+# CHECK: lui ra,0x1
+0x01 0x00 0x1f 0x3c
+
+# CHECK: sw k0,-15159(at)
+0xc9 0xc4 0x3a 0xac
+
+# CHECK: ld k0,3958(zero)
+0x76 0x0f 0x1a 0xdc
+
+# CHECK: sd a2,17767(zero)
+0x67 0x45 0x06 0xfc
+
+# CHECK: dclo t1,t8
+0x25 0x48 0x09 0x73
+
+# CHECK: dclz k0,t1
+0x24 0xd0 0x3a 0x71
+
+# CHECK: dext a3,gp,0x1d,0x1f
+0x43 0xf7 0x87 0x7f
+
+# CHECK: dins s4,gp,0xf,0x1
+0xc7 0x7b 0x94 0x7f
+
+# CHECK: dsbh a3,gp
+0xa4 0x38 0x1c 0x7c
+
+# CHECK: dshd v1,t6
+0x64 0x19 0x0e 0x7c
+
+# CHECK: drotr s4,k1,0x6
+0xba 0xa1 0x3b 0x00
+
+# CHECK: drotrv t8,s7,a1
+0x56 0xc0 0xb7 0x00
diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index e2883c7..a5dbcf2 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 -x86-asm-syntax=intel | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 --output-asm-variant=1 | FileCheck %s # CHECK: movsb 0xa4 @@ -99,3 +99,9 @@ # CHECK: iretq 0x48 0xcf +# CHECK: ret +0x66 0xc3 + +# CHECK: retf +0x66 0xcb + diff --git a/test/MC/Disassembler/X86/invalid-cmp-imm.txt b/test/MC/Disassembler/X86/invalid-cmp-imm.txt new file mode 100644 index 0000000..bf8699b --- /dev/null +++ b/test/MC/Disassembler/X86/invalid-cmp-imm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} + +# This instruction would decode as cmpordps if the immediate byte was less than 8. +0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordpd if the immediate byte was less than 8. +0x66 0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordss if the immediate byte was less than 8. +0xf3 0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordsd if the immediate byte was less than 8. +0xf2 0x0f 0xc2 0xc7 0x08 diff --git a/test/MC/Disassembler/X86/lit.local.cfg b/test/MC/Disassembler/X86/lit.local.cfg index 5f3ae7d..6211b3e 100644 --- a/test/MC/Disassembler/X86/lit.local.cfg +++ b/test/MC/Disassembler/X86/lit.local.cfg @@ -1,13 +1,6 @@ config.suffixes = ['.txt'] -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 5f2f608..739fa6a 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -421,6 +421,18 @@ # CHECK: movl %eax, 0 0xa3 0x00 0x00 0x00 0x00 +# CHECK: cmpordpd %xmm7, %xmm0 +0x66 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordps %xmm7, %xmm0 +0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordsd %xmm7, %xmm0 +0xf2 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordss %xmm7, %xmm0 +0xf3 0x0f 0xc2 0xc7 0x07 + # CHECK: vaddps %xmm3, %xmm7, %xmm0 0xc4 0xe1 0x00 0x58 0xc3 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt new file mode 100644 index 0000000..f4b8f46 --- /dev/null +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -0,0 +1,63 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s + +# Coverage + +# CHECK: vcmptrue_usps +0xc5 0x04 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_uspd +0xc5 0x05 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_usss +0xc5 0x06 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_ussd +0xc5 0x07 0xc2 0xc7 0x1f + +# CHECK: vcmpeq_uqps +0xc5 0x04 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqpd +0xc5 0x05 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqss +0xc5 0x06 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqsd +0xc5 0x07 0xc2 0xc7 0x08 + +# CHECK: vcmpeqps +0xc5 0x04 0xc2 0xc7 0x00 + +# CHECK: vcmpeqpd +0xc5 0x05 0xc2 0xc7 0x00 + +# CHECK: vcmpeqss +0xc5 0x06 0xc2 0xc7 0x00 + +# CHECK: vcmpeqsd +0xc5 0x07 0xc2 0xc7 0x00 + +# CHECK: cmpeqps +0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqpd +0x66 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqss +0xf3 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqsd +0xf2 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpordps +0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordpd +0x66 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordss +0xf3 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordsd +0xf2 0x0f 0xc2 0xc7 0x07 |