diff options
Diffstat (limited to 'test/MC/Disassembler')
92 files changed, 3212 insertions, 1816 deletions
diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt new file mode 100644 index 0000000..40d1f4c --- /dev/null +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -0,0 +1,673 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# Vector Integer Add/Sub +#------------------------------------------------------------------------------ +# CHECK: add v31.8b, v31.8b, v31.8b +# CHECK: sub v0.2d, v0.2d, v0.2d +0xff 0x87 0x3f 0x0e +0x00 0x84 0xe0 0x6e + +#------------------------------------------------------------------------------ +# Vector Floating-Point Add/Sub +#------------------------------------------------------------------------------ + +# CHECK: fadd v0.4s, v0.4s, v0.4s +# CHECK: fsub v31.2s, v31.2s, v31.2s +0x00 0xd4 0x20 0x4e +0xff 0xd7 0xbf 0x0e + +#------------------------------------------------------------------------------ +# Vector Integer Mul +#------------------------------------------------------------------------------ +# CHECK: mul v0.8b, v1.8b, v2.8b +0x20 0x9c 0x22 0x0e + +#------------------------------------------------------------------------------ +# Vector Floating-Point Mul/Div +#------------------------------------------------------------------------------ +# CHECK: fmul v0.2s, v1.2s, v2.2s +# CHECK: fdiv v31.2s, v31.2s, v31.2s +0x20 0xdc 0x22 0x2e +0xff 0xff 0x3f 0x2e + +#---------------------------------------------------------------------- +# Vector Polynomial Multiply +#---------------------------------------------------------------------- +# CHECK: pmul v0.8b, v15.8b, v16.8b +# CHECK: pmul v31.16b, v7.16b, v8.16b +0xe0 0x9d 0x30 0x2e +0xff 0x9c 0x28 0x6e + +#------------------------------------------------------------------------------ +# Vector And, Orr, Eor, Orn, Bic +#------------------------------------------------------------------------------ +# CHECK: and v2.8b, v2.8b, v2.8b +# CHECK: orr v31.16b, v31.16b, v30.16b +# CHECK: eor v0.16b, v1.16b, v2.16b +# CHECK: orn v9.16b, v10.16b, v11.16b +# CHECK: bic v31.8b, v30.8b, v29.8b +0x42 0x1c 0x22 0x0e +0xff 0x1f 0xbe 0x4e +0x20 0x1c 0x22 0x6e +0x49 0x1d 0xeb 0x4e +0xdf 0x1f 0x7d 0x0e + +#------------------------------------------------------------------------------ +# Vector Bsl, Bit, Bif +#------------------------------------------------------------------------------ +# CHECK: bsl v0.8b, v1.8b, v2.8b +# CHECK: bit v31.16b, v31.16b, v31.16b +# CHECK: bif v0.16b, v1.16b, v2.16b +0x20 0x1c 0x62 0x2e +0xff 0x1f 0xbf 0x6e +0x20 0x1c 0xe2 0x6e + + +#------------------------------------------------------------------------------ +# Vector Integer Multiply-accumulate and Multiply-subtract +#------------------------------------------------------------------------------ +# CHECK: mla v0.8b, v1.8b, v2.8b +# CHECK: mls v31.4h, v31.4h, v31.4h +0x20 0x94 0x22 0x0e +0xff 0x97 0x7f 0x2e + +#------------------------------------------------------------------------------ +# Vector Floating-Point Multiply-accumulate and Multiply-subtract +#------------------------------------------------------------------------------ +# CHECK: fmla v0.2s, v1.2s, v2.2s +# CHECK: fmls v31.2s, v31.2s, v31.2s +0x20 0xcc 0x22 0x0e +0xff 0xcf 0xbf 0x0e + +#------------------------------------------------------------------------------ +# Vector Move Immediate Shifted +# Vector Move Inverted Immediate Shifted +# Vector Bitwise Bit Clear (AND NOT) - immediate +# Vector Bitwise OR - immedidate +#------------------------------------------------------------------------------ +# CHECK: movi v31.4s, #0xff, lsl #24 +# CHECK: mvni v0.2s, #0x0 +# CHECK: bic v15.4h, #0xf, lsl #8 +# CHECK: orr v16.8h, #0x1f +0xff 0x67 0x07 0x4f +0x00 0x04 0x00 0x2f +0xef 0xb5 0x00 0x2f +0xf0 0x97 0x00 0x4f + +#------------------------------------------------------------------------------ +# Vector Move Immediate Masked +# Vector Move Inverted Immediate Masked +#------------------------------------------------------------------------------ +# CHECK: movi v8.2s, #0x8, msl #8 +# CHECK: mvni v16.4s, #0x10, msl #16 +0x08 0xc5 0x00 0x0f +0x10 0xd6 0x00 0x6f + +#------------------------------------------------------------------------------ +# Vector Immediate - per byte +# Vector Move Immediate - bytemask, per doubleword +# Vector Move Immediate - bytemask, one doubleword +#------------------------------------------------------------------------------ +# CHECK: movi v16.8b, #0xff +# CHECK: movi v31.16b, #0x1f +# CHECK: movi d15, #0xff00ff00ff00ff +# CHECK: movi v31.2d, #0xff0000ff0000ffff +0xf0 0xe7 0x07 0x0f +0xff 0xe7 0x00 0x4f +0xaf 0xe6 0x02 0x2f +0x7f 0xe6 0x04 0x6f + +#------------------------------------------------------------------------------ +# Vector Floating Point Move Immediate +#------------------------------------------------------------------------------ +# CHECK: fmov v0.2s, #13.0 +# CHECK: fmov v15.4s, #1.0 +# CHECK: fmov v31.2d, #-1.25 +0x40 0xf5 0x01 0x0f +0x0f 0xf6 0x03 0x4f +0x9f 0xf6 0x07 0x6f + +#------------------------------------------------------------------------------ +# Vector Move - register +#------------------------------------------------------------------------------ +# CHECK: mov v1.16b, v15.16b +# CHECK: mov v25.8b, v4.8b +0xe1 0x1d 0xaf 0x4e +0x99 0x1c 0xa4 0x0e + +#---------------------------------------------------------------------- +# Vector Absolute Difference and Accumulate (Signed, Unsigned) +# Vector Absolute Difference (Signed, Unsigned) +# Vector Absolute Difference (Floating Point) +#---------------------------------------------------------------------- + +# CHECK: uaba v0.8b, v1.8b, v2.8b +# CHECK: saba v31.16b, v30.16b, v29.16b +# CHECK: uabd v15.4h, v16.4h, v17.4h +# CHECK: sabd v5.4h, v4.4h, v6.4h +# CHECK: fabd v1.4s, v31.4s, v16.4s +0x20 0x7c 0x22 0x2e +0xdf 0x7f 0x3d 0x4e +0x0f 0x76 0x71 0x2e +0x85 0x74 0x66 0x0e +0xe1 0xd7 0xb0 0x6e + +#---------------------------------------------------------------------- +# Scalar Integer Add +# Scalar Integer Sub +#---------------------------------------------------------------------- + +# CHECK: add d17, d31, d29 +# CHECK: sub d15, d5, d16 +0xf1 0x87 0xfd 0x5e +0xaf 0x84 0xf0 0x7e + +#---------------------------------------------------------------------- +# Vector Reciprocal Square Root Step (Floating Point) +#---------------------------------------------------------------------- +# CHECK: frsqrts v31.2d, v15.2d, v8.2d +0xff 0xfd 0xe8 0x4e + +#---------------------------------------------------------------------- +# Vector Reciprocal Step (Floating Point) +#---------------------------------------------------------------------- +# CHECK: frecps v5.4s, v7.4s, v16.4s +0xe5 0xfc 0x30 0x4e + +#---------------------------------------------------------------------- +# Vector Absolute Compare Mask Less Than Or Equal (Floating Point) +#---------------------------------------------------------------------- +# CHECK: facge v0.4s, v31.4s, v16.4s +0xe0 0xef 0x30 0x6e + +#---------------------------------------------------------------------- +# Vector Absolute Compare Mask Less Than (Floating Point) +#---------------------------------------------------------------------- +# CHECK: facgt v31.2d, v29.2d, v28.2d +0xbf 0xef 0xfc 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Equal (Integer) +#---------------------------------------------------------------------- +# CHECK: cmeq v5.16b, v15.16b, v31.16b +0xe5 0x8d 0x3f 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Higher or Same (Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: cmhs v1.8b, v16.8b, v30.8b +0x01 0x3e 0x3e 0x2e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than or Equal (Integer) +#---------------------------------------------------------------------- +# CHECK: cmge v20.4h, v11.4h, v23.4h +0x74 0x3d 0x77 0x0e + +#---------------------------------------------------------------------- +# Vector Compare Mask Higher (Unsigned Integer) +# CHECK: cmhi v13.8h, v3.8h, v27.8h +0x6d 0x34 0x7b 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than (Integer) +#---------------------------------------------------------------------- +# CHECK: cmgt v9.4s, v4.4s, v28.4s +0x89 0x34 0xbc 0x4e + +#---------------------------------------------------------------------- +# Vector Compare Mask Bitwise Test (Integer) +#---------------------------------------------------------------------- +# CHECK: cmtst v21.2s, v19.2s, v18.2s +0x75 0x8e 0xb2 0x0e + +#---------------------------------------------------------------------- +# Vector Compare Mask Equal (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmeq v0.2s, v15.2s, v16.2s +0xe0 0xe5 0x30 0x0e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than Or Equal (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmge v31.4s, v7.4s, v29.4s +0xff 0xe4 0x3d 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmgt v17.4s, v8.4s, v25.4s +0x11 0xe5 0xb9 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Equal to Zero (Integer) +#---------------------------------------------------------------------- +# CHECK: cmeq v31.16b, v15.16b, #0x0 +0xff 0x99 0x20 0x4e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) +#---------------------------------------------------------------------- +# CHECK: cmge v3.8b, v15.8b, #0x0 +0xe3 0x89 0x20 0x2e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than Zero (Signed Integer) +#---------------------------------------------------------------------- +# CHECK: cmgt v22.2s, v9.2s, #0x0 +0x36 0x89 0xa0 0x0e + +#---------------------------------------------------------------------- +# Vector Compare Mask Less Than or Equal To Zero (Signed Integer) +#---------------------------------------------------------------------- +# CHECK: cmle v5.2d, v14.2d, #0x0 +0xc5 0x99 0xe0 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Less Than Zero (Signed Integer) +#---------------------------------------------------------------------- +# CHECK: cmlt v13.8h, v11.8h, #0x0 +0x6d 0xa9 0x60 0x4e + +#---------------------------------------------------------------------- +# Vector Compare Mask Equal to Zero (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmeq v15.2s, v21.2s, #0.0 +0xaf 0xda 0xa0 0x0e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than or Equal to Zero (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmge v14.2d, v13.2d, #0.0 +0xae 0xc9 0xe0 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Greater Than Zero (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmgt v9.4s, v23.4s, #0.0 +0xe9 0xca 0xa0 0x4e + +#---------------------------------------------------------------------- +# Vector Compare Mask Less Than or Equal To Zero (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmle v11.2d, v6.2d, #0.0 +0xcb 0xd8 0xe0 0x6e + +#---------------------------------------------------------------------- +# Vector Compare Mask Less Than Zero (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fcmlt v12.4s, v25.4s, #0.0 +0x2c 0xeb 0xa0 0x4e + + +#------------------------------------------------------------------------------ +# Vector Integer Halving Add (Signed) +# Vector Integer Halving Add (Unsigned) +# Vector Integer Halving Sub (Signed) +# Vector Integer Halving Sub (Unsigned) +#------------------------------------------------------------------------------ +# CHECK: shadd v0.8b, v31.8b, v29.8b +# CHECK: uhadd v15.16b, v16.16b, v17.16b +# CHECK: shsub v0.4h, v1.4h, v2.4h +# CHECK: uhadd v5.8h, v7.8h, v8.8h +# CHECK: shsub v9.2s, v11.2s, v21.2s +# CHECK: uhsub v22.4s, v30.4s, v19.4s +0xe0 0x07 0x3d 0x0e +0x0f 0x06 0x31 0x6e +0x20 0x24 0x62 0x0e +0xe5 0x04 0x68 0x6e +0x69 0x25 0xb5 0x0e +0xd6 0x27 0xb3 0x6e + +#------------------------------------------------------------------------------ +# Vector Integer Rouding Halving Add (Signed) +# Vector Integer Rouding Halving Add (Unsigned) +#------------------------------------------------------------------------------ +# CHECK: srhadd v3.8b, v5.8b, v7.8b +# CHECK: urhadd v7.16b, v17.16b, v27.16b +# CHECK: srhadd v10.4h, v11.4h, v13.4h +# CHECK: urhadd v1.8h, v2.8h, v3.8h +# CHECK: srhadd v4.2s, v5.2s, v6.2s +# CHECK: urhadd v7.4s, v7.4s, v7.4s +0xa3 0x14 0x27 0x0e +0x27 0x16 0x3b 0x6e +0x6a 0x15 0x6d 0x0e +0x41 0x14 0x63 0x6e +0xa4 0x14 0xa6 0x0e +0xe7 0x14 0xa7 0x6e + +#------------------------------------------------------------------------------ +# Vector Integer Saturating Add (Signed) +# Vector Integer Saturating Add (Unsigned) +# Vector Integer Saturating Sub (Signed) +# Vector Integer Saturating Sub (Unsigned) +#------------------------------------------------------------------------------ +# CHECK: sqsub v0.8b, v1.8b, v2.8b +# CHECK: sqadd v0.16b, v1.16b, v2.16b +# CHECK: uqsub v0.4h, v1.4h, v2.4h +# CHECK: uqadd v0.8h, v1.8h, v2.8h +# CHECK: sqadd v0.2s, v1.2s, v2.2s +# CHECK: sqsub v0.4s, v1.4s, v2.4s +# CHECK: sqsub v0.2d, v1.2d, v2.2d +0x20 0x2c 0x22 0x0e +0x20 0x0c 0x22 0x4e +0x20 0x2c 0x62 0x2e +0x20 0x0c 0x62 0x6e +0x20 0x0c 0xa2 0x0e +0x20 0x2c 0xa2 0x4e +0x20 0x2c 0xe2 0x4e + +#------------------------------------------------------------------------------ +# Scalar Integer Saturating Add (Signed) +# Scalar Integer Saturating Add (Unsigned) +# Scalar Integer Saturating Sub (Signed) +# Scalar Integer Saturating Add (Unsigned) +#------------------------------------------------------------------------------ +# CHECK: sqadd b20, b11, b15 +# CHECK: uqadd h0, h1, h5 +# CHECK: sqsub s20, s10, s7 +# CHECK: uqsub d16, d16, d16 +0x74 0x0d 0x2f 0x5e +0x20 0x0c 0x65 0x7e +0x54 0x2d 0xa7 0x5e +0x10 0x2e 0xf0 0x7e + + +#---------------------------------------------------------------------- +# Vector Shift Left (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: sshl v10.8b, v15.8b, v22.8b +# CHECK: ushl v10.16b, v5.16b, v2.16b +# CHECK: sshl v10.4h, v15.4h, v22.4h +# CHECK: ushl v10.8h, v5.8h, v2.8h +# CHECK: sshl v10.2s, v15.2s, v22.2s +# CHECK: ushl v10.4s, v5.4s, v2.4s +# CHECK: sshl v0.2d, v1.2d, v2.2d +0xea 0x45 0x36 0x0e +0xaa 0x44 0x22 0x6e +0xea 0x45 0x76 0x0e +0xaa 0x44 0x62 0x6e +0xea 0x45 0xb6 0x0e +0xaa 0x44 0xa2 0x6e +0x20 0x44 0xe2 0x4e + +#---------------------------------------------------------------------- +# Vector Saturating Shift Left (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: sqshl v1.8b, v15.8b, v22.8b +# CHECK: uqshl v2.16b, v14.16b, v23.16b +# CHECK: sqshl v3.4h, v13.4h, v24.4h +# CHECK: uqshl v4.8h, v12.8h, v25.8h +# CHECK: sqshl v5.2s, v11.2s, v26.2s +# CHECK: uqshl v6.4s, v10.4s, v27.4s +# CHECK: uqshl v0.2d, v1.2d, v2.2d +0xe1 0x4d 0x36 0x0e +0xc2 0x4d 0x37 0x6e +0xa3 0x4d 0x78 0x0e +0x84 0x4d 0x79 0x6e +0x65 0x4d 0xba 0x0e +0x46 0x4d 0xbb 0x6e +0x20 0x4c 0xe2 0x6e + +#---------------------------------------------------------------------- +# Vector Rouding Shift Left (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: srshl v10.8b, v5.8b, v22.8b +# CHECK: urshl v10.16b, v5.16b, v2.16b +# CHECK: srshl v1.4h, v5.4h, v31.4h +# CHECK: urshl v1.8h, v5.8h, v2.8h +# CHECK: srshl v10.2s, v15.2s, v2.2s +# CHECK: urshl v1.4s, v5.4s, v2.4s +# CHECK: urshl v0.2d, v1.2d, v2.2d +0xaa 0x54 0x36 0x0e +0xaa 0x54 0x22 0x6e +0xa1 0x54 0x7f 0x0e +0xa1 0x54 0x62 0x6e +0xea 0x55 0xa2 0x0e +0xa1 0x54 0xa2 0x6e +0x20 0x54 0xe2 0x6e + +#---------------------------------------------------------------------- +# Vector Saturating Rouding Shift Left (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: sqrshl v1.8b, v15.8b, v22.8b +# CHECK: uqrshl v2.16b, v14.16b, v23.16b +# CHECK: sqrshl v3.4h, v13.4h, v24.4h +# CHECK: uqrshl v4.8h, v12.8h, v25.8h +# CHECK: sqrshl v5.2s, v11.2s, v26.2s +# CHECK: uqrshl v6.4s, v10.4s, v27.4s +# CHECK: uqrshl v6.4s, v10.4s, v27.4s +0xe1 0x5d 0x36 0x0e +0xc2 0x5d 0x37 0x6e +0xa3 0x5d 0x78 0x0e +0x84 0x5d 0x79 0x6e +0x65 0x5d 0xba 0x0e +0x46 0x5d 0xbb 0x6e +0x46 0x5d 0xbb 0x6e + +#---------------------------------------------------------------------- +# Scalar Integer Shift Left (Signed, Unsigned) +#---------------------------------------------------------------------- +# CHECK: sshl d31, d31, d31 +# CHECK: ushl d0, d0, d0 +0xff 0x47 0xff 0x5e +0x00 0x44 0xe0 0x7e + +#---------------------------------------------------------------------- +# Scalar Integer Saturating Shift Left (Signed, Unsigned) +#---------------------------------------------------------------------- +# CHECK: sqshl d31, d31, d31 +# CHECK: uqshl s23, s20, s16 +# CHECK: sqshl h3, h4, h15 +# CHECK: uqshl b11, b20, b30 +0xff 0x4f 0xff 0x5e +0x97 0x4e 0xb0 0x7e +0x83 0x4c 0x6f 0x5e +0x8b 0x4e 0x3e 0x7e + +#---------------------------------------------------------------------- +# Scalar Integer Rouding Shift Left (Signed, Unsigned) +#---------------------------------------------------------------------- +# CHECK: srshl d16, d16, d16 +# CHECK: urshl d8, d7, d4 +0x10 0x56 0xf0 0x5e +0xe8 0x54 0xe4 0x7e + +#---------------------------------------------------------------------- +# Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned) +#---------------------------------------------------------------------- +# CHECK: sqrshl d31, d31, d31 +# CHECK: uqrshl s23, s20, s16 +# CHECK: sqrshl h3, h4, h15 +# CHECK: uqrshl b11, b20, b30 +0xff 0x5f 0xff 0x5e +0x97 0x5e 0xb0 0x7e +0x83 0x5c 0x6f 0x5e +0x8b 0x5e 0x3e 0x7e + +#---------------------------------------------------------------------- +# Vector Maximum (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: smax v1.8b, v15.8b, v22.8b +# CHECK: umax v2.16b, v14.16b, v23.16b +# CHECK: smax v3.4h, v13.4h, v24.4h +# CHECK: umax v4.8h, v12.8h, v25.8h +# CHECK: smax v5.2s, v11.2s, v26.2s +# CHECK: umax v6.4s, v10.4s, v27.4s +0xe1 0x65 0x36 0x0e +0xc2 0x65 0x37 0x6e +0xa3 0x65 0x78 0x0e +0x84 0x65 0x79 0x6e +0x65 0x65 0xba 0x0e +0x46 0x65 0xbb 0x6e + +#---------------------------------------------------------------------- +# Vector Minimum (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: umin v1.8b, v15.8b, v22.8b +# CHECK: smin v2.16b, v14.16b, v23.16b +# CHECK: umin v3.4h, v13.4h, v24.4h +# CHECK: smin v4.8h, v12.8h, v25.8h +# CHECK: umin v5.2s, v11.2s, v26.2s +# CHECK: smin v6.4s, v10.4s, v27.4s +0xe1 0x6d 0x36 0x2e +0xc2 0x6d 0x37 0x4e +0xa3 0x6d 0x78 0x2e +0x84 0x6d 0x79 0x4e +0x65 0x6d 0xba 0x2e +0x46 0x6d 0xbb 0x4e + +#---------------------------------------------------------------------- +# Vector Maximum (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fmax v29.2s, v28.2s, v25.2s +# CHECK: fmax v9.4s, v8.4s, v5.4s +# CHECK: fmax v11.2d, v10.2d, v7.2d +0x9d 0xf7 0x39 0x0e +0x09 0xf5 0x25 0x4e +0x4b 0xf5 0x67 0x4e + +#---------------------------------------------------------------------- +# Vector Minimum (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fmin v29.2s, v28.2s, v25.2s +# CHECK: fmin v9.4s, v8.4s, v5.4s +# CHECK: fmin v11.2d, v10.2d, v7.2d +0x9d 0xf7 0xb9 0x0e +0x09 0xf5 0xa5 0x4e +0x4b 0xf5 0xe7 0x4e + +#---------------------------------------------------------------------- +# Vector maxNum (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fmaxnm v9.2s, v8.2s, v5.2s +# CHECK: fmaxnm v9.4s, v8.4s, v5.4s +# CHECK: fmaxnm v11.2d, v10.2d, v7.2d +0x09 0xc5 0x25 0x0e +0x09 0xc5 0x25 0x4e +0x4b 0xc5 0x67 0x4e + +#---------------------------------------------------------------------- +# Vector minNum (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fminnm v2.2s, v8.2s, v25.2s +# CHECK: fminnm v9.4s, v8.4s, v5.4s +# CHECK: fminnm v11.2d, v10.2d, v7.2d +0x02 0xc5 0xb9 0x0e +0x09 0xc5 0xa5 0x4e +0x4b 0xc5 0xe7 0x4e + + +#---------------------------------------------------------------------- +# Vector Maximum Pairwise (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: smaxp v1.8b, v15.8b, v22.8b +# CHECK: umaxp v2.16b, v14.16b, v23.16b +# CHECK: smaxp v3.4h, v13.4h, v24.4h +# CHECK: umaxp v4.8h, v12.8h, v25.8h +# CHECK: smaxp v5.2s, v11.2s, v26.2s +# CHECK: umaxp v6.4s, v10.4s, v27.4s +0xe1 0xa5 0x36 0x0e +0xc2 0xa5 0x37 0x6e +0xa3 0xa5 0x78 0x0e +0x84 0xa5 0x79 0x6e +0x65 0xa5 0xba 0x0e +0x46 0xa5 0xbb 0x6e + +#---------------------------------------------------------------------- +# Vector Minimum Pairwise (Signed and Unsigned Integer) +#---------------------------------------------------------------------- +# CHECK: uminp v1.8b, v15.8b, v22.8b +# CHECK: sminp v2.16b, v14.16b, v23.16b +# CHECK: uminp v3.4h, v13.4h, v24.4h +# CHECK: sminp v4.8h, v12.8h, v25.8h +# CHECK: uminp v5.2s, v11.2s, v26.2s +# CHECK: sminp v6.4s, v10.4s, v27.4s +0xe1 0xad 0x36 0x2e +0xc2 0xad 0x37 0x4e +0xa3 0xad 0x78 0x2e +0x84 0xad 0x79 0x4e +0x65 0xad 0xba 0x2e +0x46 0xad 0xbb 0x4e + +#---------------------------------------------------------------------- +# Vector Maximum Pairwise (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fmaxp v29.2s, v28.2s, v25.2s +# CHECK: fmaxp v9.4s, v8.4s, v5.4s +# CHECK: fmaxp v11.2d, v10.2d, v7.2d +0x9d 0xf7 0x39 0x2e +0x09 0xf5 0x25 0x6e +0x4b 0xf5 0x67 0x6e + +#---------------------------------------------------------------------- +# Vector Minimum Pairwise (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fminp v29.2s, v28.2s, v25.2s +# CHECK: fminp v9.4s, v8.4s, v5.4s +# CHECK: fminp v11.2d, v10.2d, v7.2d +0x9d 0xf7 0xb9 0x2e +0x09 0xf5 0xa5 0x6e +0x4b 0xf5 0xe7 0x6e + +#---------------------------------------------------------------------- +# Vector maxNum Pairwise (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fmaxnmp v9.2s, v8.2s, v5.2s +# CHECK: fmaxnmp v9.4s, v8.4s, v5.4s +# CHECK: fmaxnmp v11.2d, v10.2d, v7.2d +0x09 0xc5 0x25 0x2e +0x09 0xc5 0x25 0x6e +0x4b 0xc5 0x67 0x6e + +#---------------------------------------------------------------------- +# Vector minNum Pairwise (Floating Point) +#---------------------------------------------------------------------- +# CHECK: fminnmp v2.2s, v8.2s, v25.2s +# CHECK: fminnmp v9.4s, v8.4s, v5.4s +# CHECK: fminnmp v11.2d, v10.2d, v7.2d +0x02 0xc5 0xb9 0x2e +0x09 0xc5 0xa5 0x6e +0x4b 0xc5 0xe7 0x6e + +#------------------------------------------------------------------------------ +# Vector Add Pairwise (Integer) +#------------------------------------------------------------------------------ +# CHECK: addp v31.8b, v31.8b, v31.8b +# CHECK: addp v0.2d, v0.2d, v0.2d +0xff 0xbf 0x3f 0x0e +0x00 0xbc 0xe0 0x4e + +#------------------------------------------------------------------------------ +# Vector Add Pairwise (Floating Point) +#------------------------------------------------------------------------------ +# CHECK: faddp v0.4s, v0.4s, v0.4s +# CHECK: faddp v31.2s, v31.2s, v31.2s +0x00 0xd4 0x20 0x6e +0xff 0xd7 0x3f 0x2e + + +#------------------------------------------------------------------------------ +# Vector Saturating Doubling Multiply High +# Vector Saturating Rouding Doubling Multiply High +#------------------------------------------------------------------------------ +# CHECK: sqdmulh v31.2s, v31.2s, v31.2s +# CHECK: sqdmulh v5.4s, v7.4s, v9.4s +# CHECK: sqrdmulh v31.4h, v3.4h, v13.4h +# CHECK: sqrdmulh v0.8h, v10.8h, v20.8h +0xff 0xb7 0xbf 0x0e +0xe5 0xb4 0xa9 0x4e +0x7f 0xb4 0x6d 0x2e +0x40 0xb5 0x74 0x6e + +#------------------------------------------------------------------------------ +# Vector Multiply Extended +#------------------------------------------------------------------------------ +# CHECK: fmulx v1.2s, v22.2s, v2.2s +# CHECK: fmulx v21.4s, v15.4s, v3.4s +# CHECK: fmulx v11.2d, v5.2d, v23.2d +0xc1 0xde 0x22 0x0e +0xf5 0xdd 0x23 0x4e +0xab 0xdc 0x77 0x4e + diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 98daaa7..acc2d9f 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -362,7 +362,3 @@ # CHECK: ldmgt sp!, {r9} 0x00 0x02 0xbd 0xc8 - -# CHECK: cdp2 p10, #0, c6, c12, c0, #7 -0xe0 0x6a 0x0c 0xfe - diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt deleted file mode 100644 index f7acce9..0000000 --- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == 15 then UNPREDICTABLE; -0x16 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt deleted file mode 100644 index 356c376..0000000 --- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if cond = '1110' then UNDEFINED -0x6f 0xde diff --git a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS-arm.txt deleted file mode 100644 index e447eb6..0000000 --- a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt +++ /dev/null @@ -1,9 +0,0 @@ -# CPS: various encodings that are ambiguous with other instructions - -# RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt deleted file mode 100644 index bc8b7e1..0000000 --- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# invalid imod value (0b01) -0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt deleted file mode 100644 index 842a52b..0000000 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# invalid (imod, M, iflags) combination -0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt deleted file mode 100644 index 8396156..0000000 --- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. -# Reject invalid encodings. -# -# See also A8.6.42 DSB -# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options -# other than SY are implemented. All unsupported and reserved options must execute as a full -# system DSB operation, but software must not rely on this behavior. -0xbf 0xf3 0x51 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt deleted file mode 100644 index 2c6e6a7..0000000 --- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. -# Reject invalid encodings. -# -# See also A8.6.42 DSB -# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options -# other than SY are implemented. All unsupported and reserved options must execute as a full -# system DSB operation, but software must not rely on this behavior. -0x40 0xf0 0x7f 0xf5 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt deleted file mode 100644 index 4297c016..0000000 --- a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# CBZ / CBNZ not allowed in IT block. - -0xdb 0xbf 0x42 0xbb diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt deleted file mode 100644 index 1a8ff48..0000000 --- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt +++ /dev/null @@ -1,3 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding" - -0xff 0xbf 0x6b 0x80 0x00 0x75 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt deleted file mode 100644 index 6cff09e..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. -0x92 0xb4 0x1f 0xdc - diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt deleted file mode 100644 index 7d8c492..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# Writeback is not allowed is Rn is in the target register list. - -0xb4 0xe8 0x34 0x04 diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt deleted file mode 100644 index 68d22de..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# if wback && (n == 15 || n == t) then UNPREDICTABLE -0x05 0x70 0xd7 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt deleted file mode 100644 index 4df5309..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.66 LDRD (immediate) -# if Rn = '1111' then SEE LDRD (literal) -# A8.6.67 LDRD (literal) -# Inst{21} = 0 -0xff 0xe9 0x0 0xeb diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt deleted file mode 100644 index ecab5a5..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# LDR_PRE/POST has encoding Inst{4} = 0. -0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt deleted file mode 100644 index 30cb727..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if m == 15 then UNPREDICTABLE -0x8f 0x60 0xb7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt deleted file mode 100644 index 7b7286a..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# LDR (register) has encoding Inst{4} = 0. -0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt deleted file mode 100644 index bb4b06c..0000000 --- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C -0x1b 0x1b 0xa0 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt deleted file mode 100644 index 528563a..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == 15 then UNPREDICTABLE -0x00 0xf0 0x41 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt deleted file mode 100644 index 41ec53f..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. -# The instruction is UNPREDICTABLE, and is not a valid intruction. -# -# See also -# A8.6.97 MOV (register) -0x2 0xd0 0xbc 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt deleted file mode 100644 index e5f2a5e..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt +++ /dev/null @@ -1,9 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# A8.6.89 LSL (register): Inst{7-4} = 0b0001 -0x93 0x42 0xa0 0xd1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt deleted file mode 100644 index 3f4c1e5..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt +++ /dev/null @@ -1,17 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. -# The instruction is UNPREDICTABLE, and is not a valid intruction. -# -# See also -# A8.6.88 LSL (immediate) -# A8.6.98 MOV (shifted register), and -# I.1 Instruction encoding diagrams and pseudocode -0x2 0xd1 0xbc 0xf1 - - diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt deleted file mode 100644 index c20ce54..0000000 --- a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding -0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt deleted file mode 100644 index 901667a..0000000 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) -# The hints instructions have more specific encodings, so if mask == 0, -# we should reject this as an invalid instruction. -0xa7 0xf1 0x20 0x3 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt deleted file mode 100644 index 499aa86..0000000 --- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction -# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction -0x32 0xb1 0x99 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt deleted file mode 100644 index 7bc97d5..0000000 --- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if d == 15 || n == 15 then UNPREDICTABLE; -0x5f 0x54 0xa7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt deleted file mode 100644 index fe4f43a..0000000 --- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.167 -# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE -0x1b 0x68 0xf 0x97 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt deleted file mode 100644 index bf9aac4..0000000 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ /dev/null @@ -1,17 +0,0 @@ -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# Unknown format -# -# B6.1.10 SRS -# Inst{19-8} = 0xd05 -# Inst{7-5} = 0b000 -# RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt deleted file mode 100644 index 3d5235d..0000000 --- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if BitCount(registers) < 1 then UNPREDICTABLE -0x00 0xc7 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt deleted file mode 100644 index f67f38e..0000000 --- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.223 SXTB -# if d == 15 || m == 15 then UNPREDICTABLE; -0x75 0xf4 0xaf 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt deleted file mode 100644 index f57c48f..0000000 --- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.244 UMAAL -# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; -0x98 0xbf 0x4f 0xf0 diff --git a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt b/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt deleted file mode 100644 index 113507c..0000000 --- a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt +++ /dev/null @@ -1,8 +0,0 @@ -# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD) -# imm6=0b0xxxxx -> UNDEFINED - -# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s - -# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt deleted file mode 100644 index b76485e..0000000 --- a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding" - -# invalid imm4 value (0b1xxx) -# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; -0x8f 0xf9 0xf7 0xf2 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt deleted file mode 100644 index 00b8526..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# 'a' == 1 and data_size == 8 is invalid -0x3d 0x3c 0xa0 0xf4 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt deleted file mode 100644 index 9bb0995..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0xa0 0xf9 0x10 0x08 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt deleted file mode 100644 index 58def05..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.315 VLD3 (single 3-element structure to all lanes) -# The a bit must be encoded as 0. -0xa2 0xf9 0x92 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt deleted file mode 100644 index 84c98bf..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0xa0 0xf9 0xc0 0x0f -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt deleted file mode 100644 index 9024b09..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0xa0 0xf9 0x30 0x0b -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt deleted file mode 100644 index 54fcadb..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# core registers out of range -0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt deleted file mode 100644 index e363110..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt +++ /dev/null @@ -1,62 +0,0 @@ -# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined -# RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined -# RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined -# RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined -# RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined -# RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined -# RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined -# RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST3 multi-element, size = 0b11 -> undefined -# RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST3 multi-element, align = 0b10 -> undefined -# RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST3 multi-element, align = 0b11 -> undefined -# RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST4 multi-element, size = 0b11 -> undefined -# RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VLD1 multi-element, type=0b1010 align=0b11 -# RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD1 multi-element type=0b0111 align=0b1x -# RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD1 multi-element type=0b0010 align=0b1x -# RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD2 multi-element size=0b11 -# RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD2 multi-element type=0b1111 align=0b11 -# RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD2 multi-element type=0b1001 align=0b11 -# RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD3 multi-element size=0b11 -# RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD3 multi-element align=0b1x -# RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD4 multi-element size=0b11 -# RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding - diff --git a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt deleted file mode 100644 index 9d6cd5c..0000000 --- a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt +++ /dev/null @@ -1,7 +0,0 @@ -# VMOV cmode=0b1111 op=1 -# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VMOV cmode=0b1111 op=1 -# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt deleted file mode 100644 index e8e5d6f..0000000 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# Qm -> bit[0] == 0, otherwise UNDEFINED -0xdb 0xe0 0x40 0xf2 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt deleted file mode 100644 index 9462812..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0x80 0xf9 0x10 0x08 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt deleted file mode 100644 index 99da8ce..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.391 VST1 (multiple single elements) -# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] -# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> -# contains two or four registers. rdar://11220250 -0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt deleted file mode 100644 index 497822a..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt +++ /dev/null @@ -1,18 +0,0 @@ -# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.393 VST2 (multiple 2-element structures) -# type == '1001' and align == '11' ==> UNDEFINED -# RUN: echo "0xb3 0x09 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# size == '11' ==> UNDEFINED -# RUN: echo "0xc3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# type == '1000' and align == '11' ==> UNDEFINED -# RUN: echo "0xb3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding - diff --git a/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt deleted file mode 100644 index f6e71bc..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0x80 0xf9 0x30 0x0b -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-armv7.txt b/test/MC/Disassembler/ARM/invalid-armv7.txt new file mode 100644 index 0000000..be79326 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-armv7.txt @@ -0,0 +1,510 @@ +# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s + +# This file is checking ARMv7 encodings which are globally invalid, usually due +# to the constraints of the instructions not being met. For example invalid +# combinations of registers. + + +#------------------------------------------------------------------------------ +# Undefined encodings for bfi +#------------------------------------------------------------------------------ + +# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE; +[0x16 0xf0 0xcf 0xe7] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7] + +#------------------------------------------------------------------------------ +# Undefined encodings for cdp2 +#------------------------------------------------------------------------------ + +[0xe0 0x6a 0x0c 0xfe] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe] + + +#------------------------------------------------------------------------------ +# Undefined encodings for cps* +#------------------------------------------------------------------------------ + +# invalid imod value (0b01) +[0xc0 0x67 0x4 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xc0 0x67 0x4 0xf1] + +# invalid (imod, M, iflags) combination +[0x93 0x00 0x02 0xf1] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x93 0x00 0x02 0xf1] + +# CPS: various encodings that are ambiguous with other instructions +[0x9f 0xff 0x4e 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1] + +[0x80 0x80 0x2c 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0x80 0x2c 0xf1] + +[0xce 0x3f 0x28 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xce 0x3f 0x28 0xf1] + +[0x80 0x00 0x20 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0x00 0x20 0xf1] + +[0xa0 0x00 0x00 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0x00 0x00 0xf1] + + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +[0x05 0xf0 0x20 0xe3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x05 0xf0 0x20 0xe3] + +[0x41 0xf0 0x20 0xe3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x41 0xf0 0x20 0xe3] + +# FIXME: is it "dbg #14" or not???? +[0xfe 0xf0 0x20 0xe3] +# CHCK: invalid instruction encoding + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldc +#------------------------------------------------------------------------------ + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. + +[0x92 0xb4 0x1f 0xdc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldm +#------------------------------------------------------------------------------ + +# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction +# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction + +[0x32 0xb1 0x99 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x32 0xb1 0x99 0xf8] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldr +#------------------------------------------------------------------------------ + +# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if m == 15 then UNPREDICTABLE + +[0x8f 0x60 0xb7 0xe7] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7] + +# LDR (register) has encoding Inst{4} = 0. +[0xba 0xae 0x9f 0x57] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xba 0xae 0x9f 0x57] + +# LDR_PRE/POST has encoding Inst{4} = 0. +[0xde 0x69 0x18 0x46] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xde 0x69 0x18 0x46] + +# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == 15 || n == t) then UNPREDICTABLE +[0x05 0x70 0xd7 0xe6] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x05 0x70 0xd7 0xe6] + + + +#------------------------------------------------------------------------------ +# Undefined encodings for mcr +#------------------------------------------------------------------------------ + +# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C + +[0x1b 0x1b 0xa0 0x2e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e] + + +#------------------------------------------------------------------------------ +# Undefined encodings for mov/lsl +#------------------------------------------------------------------------------ + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.88 LSL (immediate) +# A8.6.98 MOV (shifted register), and +# I.1 Instruction encoding diagrams and pseudocode + +[0x2 0xd1 0xbc 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1] + + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.97 MOV (register) + +[0x2 0xd0 0xbc 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1] + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# A8.6.89 LSL (register): Inst{7-4} = 0b0001 +[0x93 0x42 0xa0 0xd1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x93 0x42 0xa0 0xd1] + +# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE +[0x00 0xf0 0x41 0xe3] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x00 0xf0 0x41 0xe3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for mrrc2 +#------------------------------------------------------------------------------ + +[0x00 0x1a 0x50 0xfc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x1a 0x50 0xfc] + + +#------------------------------------------------------------------------------ +# Undefined encodings for msr (imm) +#------------------------------------------------------------------------------ + +# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) +# The hints instructions have more specific encodings, so if mask == 0, +# we should reject this as an invalid instruction. + +[0xa7 0xf1 0x20 0x3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa7 0xf1 0x20 0x3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for sbfx +#------------------------------------------------------------------------------ + +# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 || n == 15 then UNPREDICTABLE; + +[0x5f 0x54 0xa7 0xe7] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7] + +#------------------------------------------------------------------------------ +# Undefined encodings for smlad +#------------------------------------------------------------------------------ + +# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.167 +# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE + +[0x1b 0x68 0xf 0x97] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x1b 0x68 0xf 0x97] + + +#------------------------------------------------------------------------------ +# Undefined encodings for srs +#------------------------------------------------------------------------------ + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# Unknown format +# +# B6.1.10 SRS +# Inst{19-8} = 0xd05 +# Inst{7-5} = 0b000 + +[0x83 0x1c 0xc5 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8] + +[0x00 0x00 0x20 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x00 0x20 0xf8] + +[0xff 0xff 0xaf 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xff 0xff 0xaf 0xf8] + +[0x13 0x00 0xa0 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x13 0x00 0xa0 0xf8] + +#------------------------------------------------------------------------------ +# Undefined encodings for sxtb +#------------------------------------------------------------------------------ + +# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.223 SXTB +# if d == 15 || m == 15 then UNPREDICTABLE; + +[0x75 0xf4 0xaf 0xe6] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON umaal +#------------------------------------------------------------------------------ + +# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.244 UMAAL +# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; +[0x98 0xbf 0x4f 0xf0] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vcvt (float <-> fixed) +#------------------------------------------------------------------------------ + +# imm6=0b0xxxxx -> UNDEFINED +[0x1e 0xcf 0x92 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3] + +[0x3e 0xcf 0x92 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vext +#------------------------------------------------------------------------------ + +# invalid imm4 value (0b1xxx) +# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; +[0x8f 0xf9 0xf7 0xf2] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vldmsdb +#------------------------------------------------------------------------------ + +# core registers out of range +[0xa5 0xba 0x72 0xed] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xa5 0xba 0x72 0xed] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vmov +#------------------------------------------------------------------------------ + +# VMOV cmode=0b1111 op=1 is UNDEFINED +[0x70 0xef 0xc7 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x70 0xef 0xc7 0xf3] + +# VMOV cmode=0b1111 op=1 is UNDEFINED +[0x30 0x0f 0x80 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x30 0x0f 0x80 0xf3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vqadd +#------------------------------------------------------------------------------ + +# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Qm -> bit[0] == 0, otherwise UNDEFINED +[0xdb 0xe0 0x40 0xf2] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vld/vst +#------------------------------------------------------------------------------ + +# A8.6.393 VST2 (multiple 2-element structures) +[0xb3 0x09 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb3 0x09 0x03 0xf4] + +# size == '11' ==> UNDEFINED +[0xc3 0x08 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xc3 0x08 0x03 0xf4] + +# type == '1000' and align == '11' ==> UNDEFINED +[0xb3 0x08 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb3 0x08 0x03 0xf4] + +# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined +[0xaf 0xb7 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4] + +# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined +[0xbf 0xb7 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4] + +# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined +[0xbf 0x8a 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4] + +# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined +[0xaf 0xb6 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4] + +# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined +[0xbf 0xb6 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4] + +# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined +[0x4f 0xa8 0x07 0xf7] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7] + +# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined +[0x4f 0xa9 0x07 0xf7] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7] + +# VST3 multi-element, size = 0b11 -> undefined +[0xbf 0xa4 0x0b 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4] + +# VST3 multi-element, align = 0b10 -> undefined +[0x6f 0xa4 0x0b 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4] + +# VST3 multi-element, align = 0b11 -> undefined +[0x7f 0xa4 0x0b 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4] + +# VST4 multi-element, size = 0b11 -> undefined +[0xcf 0x50 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xcf 0x50 0x03 0xf4] + + +# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# 'a' == 1 and data_size == 8 is invalid +[0x3d 0x3c 0xa0 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4] diff --git a/test/MC/Disassembler/ARM/invalid-because-armv7.txt b/test/MC/Disassembler/ARM/invalid-because-armv7.txt new file mode 100644 index 0000000..4bf4833 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-because-armv7.txt @@ -0,0 +1,20 @@ +# RUN: not llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s + +# This file is checking encodings that are valid on some triples, but not on the +# ARMv7 triple, probably because the relevant instruction is v8, though there +# could be other reasons. + +# Would be vcvtt.f64.f16 d3, s1 +[0xe0 0x3b 0xb2 0xee] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xe0 0x3b 0xb2 0xee] + +# Would be vcvtb.f16.f64 s4, d1 +[0x41 0x2b 0xb3 0xee] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x41 0x2b 0xb3 0xee] + +# Would be vcvtblt.f16.f64 s4, d1 +[0x41 0x2b 0xb3 0xbe] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe] diff --git a/test/MC/Disassembler/ARM/invalid-hint-arm.txt b/test/MC/Disassembler/ARM/invalid-hint-arm.txt deleted file mode 100644 index 7da96d8..0000000 --- a/test/MC/Disassembler/ARM/invalid-hint-arm.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s - -#------------------------------------------------------------------------------ -# Undefined encoding space for hint instructions -#------------------------------------------------------------------------------ - -0x05 0xf0 0x20 0xe3 -# CHECK: invalid instruction encoding -0x41 0xf0 0x20 0xe3 -# CHECK: invalid instruction encoding -0xfe 0xf0 0x20 0xe3 -# CHECK: invalid instruction encoding - diff --git a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt deleted file mode 100644 index 1e41336..0000000 --- a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt +++ /dev/null @@ -1,8 +0,0 @@ -# RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s - -#------------------------------------------------------------------------------ -# Undefined encoding space for hint instructions -#------------------------------------------------------------------------------ - -0xaf 0xf3 0x05 0x80 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt deleted file mode 100644 index c9f1cf1..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.16 B -# if cond<3:1> == '111' then SEE "Related Encodings" -0xaf 0xf7 0x44 0x8b diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt deleted file mode 100644 index eb415f7..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# The unpriviledged Load/Store cannot have SP or PC as Rt. -0x10 0xf8 0x3 0xfe diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt deleted file mode 100644 index 6c13560..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * - -# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if t == t2 then UNPREDICTABLE -0xd2 0xe8 0x7f 0x88 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt deleted file mode 100644 index 7f84e08..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if Rt = '1111' then SEE "Unallocated memory hints" -0xb3 0xf9 0xdf 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt deleted file mode 100644 index e44cf95..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" -0x35 0xf9 0x00 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt deleted file mode 100644 index 8c0d48b..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# SP and PC are not allowed in the register list on STM instructions in Thumb2. - -0x2d 0xe9 0xf7 0xb6 diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt deleted file mode 100644 index 64ba368..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * - -# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# if wback && (n == t || n == t2) then UNPREDICTABLE -0xe4 0xe9 0x02 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt deleted file mode 100644 index 243c11d..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * - -# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == n || d == t then UNPREDICTABLE -0xc2 0xe8 0x42 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt deleted file mode 100644 index 7a7c4a5..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == n || d == t || d == t2 then UNPREDICTABLE -mc-input.txt:1:1: warning: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt deleted file mode 100644 index 2ad3e7d..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if Rn == '1111' then UNDEFINED -0x4f 0xf8 0xff 0xeb diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt b/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt new file mode 100644 index 0000000..ca5dd65 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt @@ -0,0 +1,38 @@ +# RUN: llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s +# XFAIL: * + +#------------------------------------------------------------------------------ +# Undefined encodings for ldrexd/strexd +#------------------------------------------------------------------------------ + +# FIXME: "ldrexd r8, r8, [r2]" +# Rt == Rt2 is UNPREDICTABLE + +[0xd2 0xe8 0x7f 0x88] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xd2 0xe8 0x7f 0x88] + +# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t then UNPREDICTABLE + +[0xc2 0xe8 0x42 0x8f] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xc2 0xe8 0x42 0x8f] + +# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t || d == t2 then UNPREDICTABLE + +# FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]" +[0xc2 0xe8 0x78 0x78] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xc2 0xe8 0x78 0x78] diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt new file mode 100644 index 0000000..f465b3c --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -0,0 +1,404 @@ +# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s + +# This file is checking Thumbv7 encodings which are globally invalid, usually due +# to the constraints of the instructions not being met. For example invalid +# combinations of registers. + +#------------------------------------------------------------------------------ +# Undefined encoding for b.cc +#------------------------------------------------------------------------------ + +# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.16 B +# if cond<3:1> == '111' then SEE "Related Encodings" + +[0xaf 0xf7 0x44 0x8b] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] + +# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if cond = '1110' then UNDEFINED +[0x6f 0xde] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x6f 0xde] + + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +[0xaf 0xf3 0x05 0x80] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xf3 0x05 0x80] + + +#------------------------------------------------------------------------------ +# Undefined encoding for it +#------------------------------------------------------------------------------ + +[0xff 0xbf 0x6b 0x80 0x00 0x75] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75] + +# mask = 0 +[0x50 0xbf 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x50 0xbf 0x00 0x00] + +# Two warnings from this block since there are two instructions in there +[0xdb 0xbf 0x42 0xbb] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] + +#------------------------------------------------------------------------------ +# Undefined encoding for ldm +#------------------------------------------------------------------------------ + +# Writeback is not allowed is Rn is in the target register list. +[0xb4 0xe8 0x34 0x04] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xb4 0xe8 0x34 0x04] + + +#------------------------------------------------------------------------------ +# Undefined encoding for ldrd +#------------------------------------------------------------------------------ + +# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.66 LDRD (immediate) +# if Rn = '1111' then SEE LDRD (literal) +# A8.6.67 LDRD (literal) +# Inst{21} = 0 + +[0xff 0xe9 0x0 0xeb] +# CHECK: potentially undefined +# CHECK-NEXT: [0xff 0xe9 0x0 0xeb] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldrbt +#------------------------------------------------------------------------------ + +# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# The unpriviledged Load/Store cannot have SP or PC as Rt. +[0x10 0xf8 0x3 0xfe] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x10 0xf8 0x3 0xfe] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldrsh +#------------------------------------------------------------------------------ + +# invalid LDRSHs Rt=PC +[0x30 0xf9 0x00 0xf0] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x30 0xf9 0x00 0xf0] + +# invalid LDRSHi8 Rt=PC +[0x30 0xf9 0x00 0xfc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x30 0xf9 0x00 0xfc] + +# invalid LDRSHi12 Rt=PC +[0xb0 0xf9 0x00 0xf0] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0] + +# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" +[0x35 0xf9 0x00 0xfc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x35 0xf9 0x00 0xfc] + +# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rt = '1111' then SEE "Unallocated memory hints" +[0xb3 0xf9 0xdf 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8] + + +#------------------------------------------------------------------------------ +# Undefined encoding for push +#------------------------------------------------------------------------------ + +# SP and PC are not allowed in the register list on STM instructions in Thumb2. +[0x2d 0xe9 0xf7 0xb6] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6] + + +#------------------------------------------------------------------------------ +# Undefined encoding for stmia +#------------------------------------------------------------------------------ + +# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if BitCount(registers) < 1 then UNPREDICTABLE +[0x00 0xc7] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xc7] + + +#------------------------------------------------------------------------------ +# Undefined encodings for str +#------------------------------------------------------------------------------ + +# invalid STRi12 Rn=PC +[0xcf 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xcf 0xf8 0x00 0x00] + +# invalid STRi8 Rn=PC +[0x4f 0xf8 0x00 0x0c] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c] + +# invalid STRs Rn=PC +[0x4f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0x00 0x00] + +# invalid STRBi12 Rn=PC +[0x0f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] + +# invalid STRBi8 Rn=PC +[0x0f 0xf8 0x00 0x0c] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c] + +# invalid STRBs Rn=PC +[0x0f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] + +# invalid STRHi12 Rn=PC +[0xaf 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xf8 0x00 0x00] + +# invalid STRHi8 Rn=PC +[0x2f 0xf8 0x00 0x0c] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c] + +# invalid STRHs Rn=PC +[0x2f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2f 0xf8 0x00 0x00] + +# invalid STRBT Rn=PC +[0x0f 0xf8 0x00 0x0e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e] + +# invalid STRHT Rn=PC +[0x2f 0xf8 0x00 0x0e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e] + +# invalid STRT Rn=PC +[0x4f 0xf8 0x00 0x0e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e] + +# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rn == '1111' then UNDEFINED + +[0x4f 0xf8 0xff 0xeb] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb] + +#------------------------------------------------------------------------------ +# Undefined encodings for strd +#------------------------------------------------------------------------------ + +# Rt == Rn is UNPREDICTABLE +[0xe4 0xe9 0x02 0x46] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0xe4 0xe9 0x02 0x46] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON/VFP instructions with invalid predicate bits +#------------------------------------------------------------------------------ + +# VABS +[0x40 0xde 0x00 0x0a] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x40 0xde 0x00 0x0a] + + +# VMLA +[0xf0 0xde 0xe0 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] + +# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) + +# VMOV +[0x00 0xde 0x10 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xde 0x10 0x0b] + +# VDUP +[0xff 0xde 0xf0 0xfb] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xff 0xde 0xf0 0xfb] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vld instructions +#------------------------------------------------------------------------------ + +# size = '00' and index_align == '0001' so UNDEFINED +[0xa0 0xf9 0x10 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0xf9 0x10 0x08] + + +# vld3 + +# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.315 VLD3 (single 3-element structure to all lanes) +# The a bit must be encoded as 0. + +[0xa2 0xf9 0x92 0x2e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e] + + +# Some vld4 ones +# size == '11' and a == '0' so UNDEFINED +[0xa0 0xf9 0xc0 0x0f] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f] + +[0xa0 0xf9 0x30 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b] + + +# VLD1 multi-element, type=0b1010 align=0b11 +[0x24 0xf9 0xbf 0x8a] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a] + +# VLD1 multi-element type=0b0111 align=0b1x +[0x24 0xf9 0xbf 0x87] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x24 0xf9 0xbf 0x87] + +# VLD1 multi-element type=0b0010 align=0b1x +[0x24 0xf9 0xbf 0x86] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x24 0xf9 0xbf 0x86] + +# VLD2 multi-element size=0b11 +[0x60 0xf9 0xcf 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xcf 0x08] + +# VLD2 multi-element type=0b1111 align=0b11 +[0x60 0xf9 0xbf 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xbf 0x08] + +# VLD2 multi-element type=0b1001 align=0b11 +[0x60 0xf9 0xbf 0x09] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xbf 0x09] + +# VLD3 multi-element size=0b11 +[0x60 0xf9 0x7f 0x04] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0x7f 0x04] + +# VLD3 multi-element align=0b1x +[0x60 0xf9 0xcf 0x04] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xcf 0x04] + +# VLD4 multi-element size=0b11 +[0x60 0xf9 0xcd 0x11] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xcd 0x11] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vst1 +#------------------------------------------------------------------------------ + +# size == '10' and index_align == '0001' so UNDEFINED +[0x80 0xf9 0x10 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xf9 0x10 0x08] + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +[0x00 0xf9 0x2f 0x06] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xf9 0x2f 0x06] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vst4 +#------------------------------------------------------------------------------ + +[0x80 0xf9 0x30 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xf9 0x30 0x0b] diff --git a/test/MC/Disassembler/ARM/neon-v8.txt b/test/MC/Disassembler/ARM/neon-v8.txt new file mode 100644 index 0000000..8c6e689 --- /dev/null +++ b/test/MC/Disassembler/ARM/neon-v8.txt @@ -0,0 +1,71 @@ +# RUN: llvm-mc -triple armv8-unknown-unknown -mattr=+neon -disassemble < %s | FileCheck %s + +0x11 0x4f 0x05 0xf3 +# CHECK: vmaxnm.f32 d4, d5, d1 +0x5c 0x4f 0x08 0xf3 +# CHECK: vmaxnm.f32 q2, q4, q6 +0x3e 0x5f 0x24 0xf3 +# CHECK: vminnm.f32 d5, d4, d30 +0xd4 0x0f 0x2a 0xf3 +# CHECK: vminnm.f32 q0, q13, q2 + +0x06 0x40 0xbb 0xf3 +# CHECK: vcvta.s32.f32 d4, d6 +0x8a 0xc0 0xbb 0xf3 +# CHECK: vcvta.u32.f32 d12, d10 +0x4c 0x80 0xbb 0xf3 +# CHECK: vcvta.s32.f32 q4, q6 +0xe4 0x80 0xbb 0xf3 +# CHECK: vcvta.u32.f32 q4, q10 + +0x2e 0x13 0xbb 0xf3 +# CHECK: vcvtm.s32.f32 d1, d30 +0x8a 0xc3 0xbb 0xf3 +# CHECK: vcvtm.u32.f32 d12, d10 +0x64 0x23 0xbb 0xf3 +# CHECK: vcvtm.s32.f32 q1, q10 +0xc2 0xa3 0xfb 0xf3 +# CHECK: vcvtm.u32.f32 q13, q1 + +0x21 0xf1 0xbb 0xf3 +# CHECK: vcvtn.s32.f32 d15, d17 +0x83 0x51 0xbb 0xf3 +# CHECK: vcvtn.u32.f32 d5, d3 +0x60 0x61 0xbb 0xf3 +# CHECK: vcvtn.s32.f32 q3, q8 +0xc6 0xa1 0xbb 0xf3 +# CHECK: vcvtn.u32.f32 q5, q3 + +0x25 0xb2 0xbb 0xf3 +# CHECK: vcvtp.s32.f32 d11, d21 +0xa7 0xe2 0xbb 0xf3 +# CHECK: vcvtp.u32.f32 d14, d23 +0x6e 0x82 0xbb 0xf3 +# CHECK: vcvtp.s32.f32 q4, q15 +0xe0 0x22 0xfb 0xf3 +# CHECK: vcvtp.u32.f32 q9, q8 + +0x00 0x34 0xba 0xf3 +# CHECK: vrintn.f32 d3, d0 +0x48 0x24 0xba 0xf3 +# CHECK: vrintn.f32 q1, q4 +0x8c 0x54 0xba 0xf3 +# CHECK: vrintx.f32 d5, d12 +0xc6 0x04 0xba 0xf3 +# CHECK: vrintx.f32 q0, q3 +0x00 0x35 0xba 0xf3 +# CHECK: vrinta.f32 d3, d0 +0x44 0x05 0xfa 0xf3 +# CHECK: vrinta.f32 q8, q2 +0xa2 0xc5 0xba 0xf3 +# CHECK: vrintz.f32 d12, d18 +0xc8 0x25 0xfa 0xf3 +# CHECK: vrintz.f32 q9, q4 +0x80 0x36 0xba 0xf3 +# CHECK: vrintm.f32 d3, d0 +0xc8 0x26 0xba 0xf3 +# CHECK: vrintm.f32 q1, q4 +0x80 0x37 0xba 0xf3 +# CHECK: vrintp.f32 d3, d0 +0xc8 0x27 0xba 0xf3 +# CHECK: vrintp.f32 q1, q4 diff --git a/test/MC/Disassembler/ARM/thumb-neon-v8.txt b/test/MC/Disassembler/ARM/thumb-neon-v8.txt new file mode 100644 index 0000000..27c09ea --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-neon-v8.txt @@ -0,0 +1,71 @@ +# RUN: llvm-mc -triple thumbv8-unknown-unknown -mattr=+neon -disassemble < %s | FileCheck %s + +0x5 0xff 0x11 0x4f +# CHECK: vmaxnm.f32 d4, d5, d1 +0x08 0xff 0x5c 0x4f +# CHECK: vmaxnm.f32 q2, q4, q6 +0x24 0xff 0x3e 0x5f +# CHECK: vminnm.f32 d5, d4, d30 +0x2a 0xff 0xd4 0x0f +# CHECK: vminnm.f32 q0, q13, q2 + +0xbb 0xff 0x06 0x40 +# CHECK: vcvta.s32.f32 d4, d6 +0xbb 0xff 0x8a 0xc0 +# CHECK: vcvta.u32.f32 d12, d10 +0xbb 0xff 0x4c 0x80 +# CHECK: vcvta.s32.f32 q4, q6 +0xbb 0xff 0xe4 0x80 +# CHECK: vcvta.u32.f32 q4, q10 + +0xbb 0xff 0x2e 0x13 +# CHECK: vcvtm.s32.f32 d1, d30 +0xbb 0xff 0x8a 0xc3 +# CHECK: vcvtm.u32.f32 d12, d10 +0xbb 0xff 0x64 0x23 +# CHECK: vcvtm.s32.f32 q1, q10 +0xfb 0xff 0xc2 0xa3 +# CHECK: vcvtm.u32.f32 q13, q1 + +0xbb 0xff 0x21 0xf1 +# CHECK: vcvtn.s32.f32 d15, d17 +0xbb 0xff 0x83 0x51 +# CHECK: vcvtn.u32.f32 d5, d3 +0xbb 0xff 0x60 0x61 +# CHECK: vcvtn.s32.f32 q3, q8 +0xbb 0xff 0xc6 0xa1 +# CHECK: vcvtn.u32.f32 q5, q3 + +0xbb 0xff 0x25 0xb2 +# CHECK: vcvtp.s32.f32 d11, d21 +0xbb 0xff 0xa7 0xe2 +# CHECK: vcvtp.u32.f32 d14, d23 +0xbb 0xff 0x6e 0x82 +# CHECK: vcvtp.s32.f32 q4, q15 +0xfb 0xff 0xe0 0x22 +# CHECK: vcvtp.u32.f32 q9, q8 + +0xba 0xff 0x00 0x34 +# CHECK: vrintn.f32 d3, d0 +0xba 0xff 0x48 0x24 +# CHECK: vrintn.f32 q1, q4 +0xba 0xff 0x8c 0x54 +# CHECK: vrintx.f32 d5, d12 +0xba 0xff 0xc6 0x04 +# CHECK: vrintx.f32 q0, q3 +0xba 0xff 0x00 0x35 +# CHECK: vrinta.f32 d3, d0 +0xfa 0xff 0x44 0x05 +# CHECK: vrinta.f32 q8, q2 +0xba 0xff 0xa2 0xc5 +# CHECK: vrintz.f32 d12, d18 +0xfa 0xff 0xc8 0x25 +# CHECK: vrintz.f32 q9, q4 +0xba 0xff 0x80 0x36 +# CHECK: vrintm.f32 d3, d0 +0xba 0xff 0xc8 0x26 +# CHECK: vrintm.f32 q1, q4 +0xba 0xff 0x80 0x37 +# CHECK: vrintp.f32 d3, d0 +0xba 0xff 0xc8 0x27 +# CHECK: vrintp.f32 q1, q4 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 757ce6e..84dd075 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -221,6 +221,9 @@ # CHECK: stc2 p12, c15, [r9], {137} 0x89 0xfc 0x89 0xfc +# CHECK: stc2 p0, c0, [r0, #0]! +0xa0 0xfd 0x00 0x00 + # CHECK: vmov r1, r0, d11 0x50 0xec 0x1b 0x1b diff --git a/test/MC/Disassembler/ARM/thumb-v8fp.txt b/test/MC/Disassembler/ARM/thumb-v8fp.txt new file mode 100644 index 0000000..3457192 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-v8fp.txt @@ -0,0 +1,163 @@ +# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s + +0xb2 0xee 0xe0 0x3b +# CHECK: vcvtt.f64.f16 d3, s1 + +0xf3 0xee 0xcc 0x2b +# CHECK: vcvtt.f16.f64 s5, d12 + +0xb2 0xee 0x60 0x3b +# CHECK: vcvtb.f64.f16 d3, s1 + +0xb3 0xee 0x41 0x2b +# CHECK: vcvtb.f16.f64 s4, d1 + +0xa8 0xbf # IT block +0xb2 0xee 0xe0 0x3b +# CHECK: vcvttge.f64.f16 d3, s1 + +0xc8 0xbf # IT block +0xf3 0xee 0xcc 0x2b +# CHECK: vcvttgt.f16.f64 s5, d12 + +0x08 0xbf # IT block +0xb2 0xee 0x60 0x3b +# CHECK: vcvtbeq.f64.f16 d3, s1 + +0xb8 0xbf # IT block +0xb3 0xee 0x41 0x2b +# CHECK: vcvtblt.f16.f64 s4, d1 + + +0xbc 0xfe 0xe1 0x1a +# CHECK: vcvta.s32.f32 s2, s3 + +0xbc 0xfe 0xc3 0x1b +# CHECK: vcvta.s32.f64 s2, d3 + +0xbd 0xfe 0xeb 0x3a +# CHECK: vcvtn.s32.f32 s6, s23 + +0xbd 0xfe 0xe7 0x3b +# CHECK: vcvtn.s32.f64 s6, d23 + +0xbe 0xfe 0xc2 0x0a +# CHECK: vcvtp.s32.f32 s0, s4 + +0xbe 0xfe 0xc4 0x0b +# CHECK: vcvtp.s32.f64 s0, d4 + +0xff 0xfe 0xc4 0x8a +# CHECK: vcvtm.s32.f32 s17, s8 + +0xff 0xfe 0xc8 0x8b +# CHECK: vcvtm.s32.f64 s17, d8 + +0xbc 0xfe 0x61 0x1a +# CHECK: vcvta.u32.f32 s2, s3 + +0xbc 0xfe 0x43 0x1b +# CHECK: vcvta.u32.f64 s2, d3 + +0xbd 0xfe 0x6b 0x3a +# CHECK: vcvtn.u32.f32 s6, s23 + +0xbd 0xfe 0x67 0x3b +# CHECK: vcvtn.u32.f64 s6, d23 + +0xbe 0xfe 0x42 0x0a +# CHECK: vcvtp.u32.f32 s0, s4 + +0xbe 0xfe 0x44 0x0b +# CHECK: vcvtp.u32.f64 s0, d4 + +0xff 0xfe 0x44 0x8a +# CHECK: vcvtm.u32.f32 s17, s8 + +0xff 0xfe 0x48 0x8b +# CHECK: vcvtm.u32.f64 s17, d8 + + +0x20 0xfe 0xab 0x2a +# CHECK: vselge.f32 s4, s1, s23 + +0x6f 0xfe 0xa7 0xeb +# CHECK: vselge.f64 d30, d31, d23 + +0x30 0xfe 0x80 0x0a +# CHECK: vselgt.f32 s0, s1, s0 + +0x3a 0xfe 0x24 0x5b +# CHECK: vselgt.f64 d5, d10, d20 + +0x0e 0xfe 0x2b 0xfa +# CHECK: vseleq.f32 s30, s28, s23 + +0x04 0xfe 0x08 0x2b +# CHECK: vseleq.f64 d2, d4, d8 + +0x58 0xfe 0x07 0xaa +# CHECK: vselvs.f32 s21, s16, s14 + +0x11 0xfe 0x2f 0x0b +# CHECK: vselvs.f64 d0, d1, d31 + + +0xc6 0xfe 0x00 0x2a +# CHECK: vmaxnm.f32 s5, s12, s0 + +0x86 0xfe 0xae 0x5b +# CHECK: vmaxnm.f64 d5, d22, d30 + +0x80 0xfe 0x46 0x0a +# CHECK: vminnm.f32 s0, s0, s12 + +0x86 0xfe 0x49 0x4b +# CHECK: vminnm.f64 d4, d6, d9 + + +0xa8 0xbf # IT block +0xb6 0xee 0xcc 0x3b +# CHECK: vrintzge.f64 d3, d12 + +0xf6 0xee 0xcc 0x1a +# CHECK: vrintz.f32 s3, s24 + +0xb8 0xbf # IT block +0xb6 0xee 0x40 0x5b +# CHECK: vrintrlt.f64 d5, d0 + +0xb6 0xee 0x64 0x0a +# CHECK: vrintr.f32 s0, s9 + +0x08 0xbf # IT block +0xf7 0xee 0x6e 0xcb +# CHECK: vrintxeq.f64 d28, d30 + +0x68 0xbf # IT block +0xb7 0xee 0x47 0x5a +# CHECK: vrintxvs.f32 s10, s14 + +0xb8 0xfe 0x44 0x3b +# CHECK: vrinta.f64 d3, d4 + +0xb8 0xfe 0x60 0x6a +# CHECK: vrinta.f32 s12, s1 + +0xb9 0xfe 0x44 0x3b +# CHECK: vrintn.f64 d3, d4 + +0xb9 0xfe 0x60 0x6a +# CHECK: vrintn.f32 s12, s1 + +0xba 0xfe 0x44 0x3b +# CHECK: vrintp.f64 d3, d4 + +0xba 0xfe 0x60 0x6a +# CHECK: vrintp.f32 s12, s1 + +0xbb 0xfe 0x44 0x3b +# CHECK: vrintm.f64 d3, d4 + +0xbb 0xfe 0x60 0x6a +# CHECK: vrintm.f32 s12, s1 diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index de9596a..a129abb 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -54,8 +54,12 @@ #------------------------------------------------------------------------------ # ADR #------------------------------------------------------------------------------ -# CHECK: adr r2, #3 +# CHECK: adr r5, #0 +# CHECK: adr r2, #12 +# CHECK: adr r3, #1020 +0x00 0xa5 0x03 0xa2 +0xff 0xa3 #------------------------------------------------------------------------------ # ASR (immediate) @@ -279,9 +283,11 @@ #------------------------------------------------------------------------------ # CHECK: mov r3, r4 # CHECK: movs r1, r3 +# CHECK: mov r8, r8 0x23 0x46 0x19 0x00 +0xc0 0x46 #------------------------------------------------------------------------------ @@ -310,14 +316,6 @@ #------------------------------------------------------------------------------ -# NOP -#------------------------------------------------------------------------------ -# CHECK: nop - -0xc0 0x46 - - -#------------------------------------------------------------------------------ # ORR #------------------------------------------------------------------------------ # CHECK: orrs r3, r4 diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index fc237ab..9fc166f 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -170,8 +170,10 @@ 0x13 0xf5 0xce 0xa9 # CHECK: b.w #208962 +# CHECK: b.w #-16777216 0x33 0xf0 0x21 0xb8 # rdar://12585795 +0x00 0xf4 0x00 0x90 #------------------------------------------------------------------------------ # BFC @@ -551,6 +553,17 @@ #------------------------------------------------------------------------------ +# LDR(literal) +#------------------------------------------------------------------------------ +# CHECK: ldr.w r4, [pc, #-0] +# CHECK: ldr.w r2, [pc, #-40] +# CHECK: ldr.w r1, [pc, #1024] +0x5f 0xf8 0x00 0x40 +0x5f 0xf8 0x28 0x20 +0xdf 0xf8 0x00 0x14 + + +#------------------------------------------------------------------------------ # LDR(register) #------------------------------------------------------------------------------ # CHECK: ldr.w r1, [r8, r1] @@ -563,6 +576,7 @@ # CHECK: ldr r2, [r4, #255]! # CHECK: ldr r8, [sp, #4]! # CHECK: ldr lr, [sp, #-4]! +# CHECK: ldr lr, [sp, #0]! # CHECK: ldr r2, [r4], #255 # CHECK: ldr r8, [sp], #4 # CHECK: ldr lr, [sp], #-4 @@ -577,6 +591,7 @@ 0x54 0xf8 0xff 0x2f 0x5d 0xf8 0x04 0x8f 0x5d 0xf8 0x04 0xed +0x5d 0xf8 0x00 0xef 0x54 0xf8 0xff 0x2b 0x5d 0xf8 0x04 0x8b 0x5d 0xf8 0x04 0xe9 @@ -610,6 +625,7 @@ # CHECK: ldrb r5, [r8, #255]! # CHECK: ldrb r2, [r5, #4]! # CHECK: ldrb r1, [r4, #-4]! +# CHECK: ldrb r1, [r4, #0]! # CHECK: ldrb lr, [r3], #255 # CHECK: ldrb r9, [r2], #4 # CHECK: ldrb r3, [sp], #-4 @@ -623,12 +639,24 @@ 0x18 0xf8 0xff 0x5f 0x15 0xf8 0x04 0x2f 0x14 0xf8 0x04 0x1d +0x14 0xf8 0x00 0x1f 0x13 0xf8 0xff 0xeb 0x12 0xf8 0x04 0x9b 0x1d 0xf8 0x04 0x39 #------------------------------------------------------------------------------ +# LDRB(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrb.w r6, [pc, #-0] +# CHECK: ldrb.w r10, [pc, #227] +# CHECK: ldrb.w r5, [pc, #0] +0x1f 0xf8 0x00 0x60 +0x9f 0xf8 0xe3 0xa0 +0x9f 0xf8 0x00 0x50 + + +#------------------------------------------------------------------------------ # LDRBT #------------------------------------------------------------------------------ # CHECK: ldrbt r1, [r2] @@ -653,7 +681,9 @@ # CHECK: ldrd r8, r1, [r3] # CHECK: ldrd r0, r1, [r2], #-0 # CHECK: ldrd r0, r1, [r2, #-0]! +# CHECK: ldrd r0, r1, [r2, #0]! # CHECK: ldrd r0, r1, [r2, #-0] +# CHECK: ldrd r1, r1, [r0], #0 0xd6 0xe9 0x06 0x35 0xf6 0xe9 0x06 0x35 @@ -663,7 +693,9 @@ 0xd3 0xe9 0x00 0x81 0x72 0xe8 0x00 0x01 0x72 0xe9 0x00 0x01 +0xf2 0xe9 0x00 0x01 0x52 0xe9 0x00 0x01 +0xf0 0xe8 0x00 0x11 #------------------------------------------------------------------------------ @@ -697,14 +729,12 @@ # CHECK: ldrh.w r5, [r6, #33] # CHECK: ldrh.w r5, [r6, #257] # CHECK: ldrh.w lr, [r7, #257] -# CHECK: ldrh.w r0, [pc, #-21] 0x35 0xf8 0x04 0x5c 0x35 0x8c 0xb6 0xf8 0x21 0x50 0xb6 0xf8 0x01 0x51 0xb7 0xf8 0x01 0xe1 -0x3f 0xf8 0x15 0x00 #------------------------------------------------------------------------------ @@ -719,6 +749,7 @@ # CHECK: ldrh r5, [r8, #255]! # CHECK: ldrh r2, [r5, #4]! # CHECK: ldrh r1, [r4, #-4]! +# CHECK: ldrh r1, [r4, #0]! # CHECK: ldrh lr, [r3], #255 # CHECK: ldrh r9, [r2], #4 # CHECK: ldrh r3, [sp], #-4 @@ -732,12 +763,24 @@ 0x38 0xf8 0xff 0x5f 0x35 0xf8 0x04 0x2f 0x34 0xf8 0x04 0x1d +0x34 0xf8 0x00 0x1f 0x33 0xf8 0xff 0xeb 0x32 0xf8 0x04 0x9b 0x3d 0xf8 0x04 0x39 #------------------------------------------------------------------------------ +# LDRH(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrh.w r7, [pc, #-0] +# CHECK: ldrh.w r5, [pc, #121] +# CHECK: ldrh.w r4, [pc, #0] +0x3f 0xf8 0x00 0x70 +0xbf 0xf8 0x79 0x50 +0xbf 0xf8 0x00 0x40 + + +#------------------------------------------------------------------------------ # LDRSB(immediate) #------------------------------------------------------------------------------ # CHECK: ldrsb r5, [r5, #-4] @@ -765,6 +808,7 @@ # CHECK: ldrsb r5, [r8, #255]! # CHECK: ldrsb r2, [r5, #4]! # CHECK: ldrsb r1, [r4, #-4]! +# CHECK: ldrsb r1, [r4, #0]! # CHECK: ldrsb lr, [r3], #255 # CHECK: ldrsb r9, [r2], #4 # CHECK: ldrsb r3, [sp], #-4 @@ -778,12 +822,24 @@ 0x18 0xf9 0xff 0x5f 0x15 0xf9 0x04 0x2f 0x14 0xf9 0x04 0x1d +0x14 0xf9 0x00 0x1f 0x13 0xf9 0xff 0xeb 0x12 0xf9 0x04 0x9b 0x1d 0xf9 0x04 0x39 #------------------------------------------------------------------------------ +# LDRSB(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrsb.w r0, [pc, #-0] +# CHECK: ldrsb.w r12, [pc, #80] +# CHECK: ldrsb.w r3, [pc, #0] +0x1f 0xf9 0x00 0x00 +0x9f 0xf9 0x50 0xc0 +0x9f 0xf9 0x00 0x30 + + +#------------------------------------------------------------------------------ # LDRSBT #------------------------------------------------------------------------------ # CHECK: ldrsbt r1, [r2] @@ -826,6 +882,7 @@ # CHECK: ldrsh r5, [r8, #255]! # CHECK: ldrsh r2, [r5, #4]! # CHECK: ldrsh r1, [r4, #-4]! +# CHECK: ldrsh r1, [r4, #0]! # CHECK: ldrsh lr, [r3], #255 # CHECK: ldrsh r9, [r2], #4 # CHECK: ldrsh r3, [sp], #-4 @@ -839,12 +896,24 @@ 0x38 0xf9 0xff 0x5f 0x35 0xf9 0x04 0x2f 0x34 0xf9 0x04 0x1d +0x34 0xf9 0x00 0x1f 0x33 0xf9 0xff 0xeb 0x32 0xf9 0x04 0x9b 0x3d 0xf9 0x04 0x39 #------------------------------------------------------------------------------ +# LDRSH(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrsh.w r0, [pc, #-0] +# CHECK: ldrsh.w r10, [pc, #-231] +# CHECK: ldrsh.w r6, [pc, #0] +0x3f 0xf9 0x00 0x00 +0x3f 0xf9 0xe7 0xa0 +0xbf 0xf9 0x00 0x60 + + +#------------------------------------------------------------------------------ # LDRSHT #------------------------------------------------------------------------------ # CHECK: ldrsht r1, [r2] @@ -1237,6 +1306,17 @@ 0x1d 0xf8 0x02 0xf0 #------------------------------------------------------------------------------ +# PLD(literal) +#------------------------------------------------------------------------------ +# CHECK: pld [pc, #-0] +# CHECK: pld [pc, #455] +# CHECK: pld [pc, #0] + +0x1f 0xf8 0x00 0xf0 +0x9f 0xf8 0xc7 0xf1 +0x9f 0xf8 0x00 0xf0 + +#------------------------------------------------------------------------------ # PLI(immediate) #------------------------------------------------------------------------------ # CHECK: pli [r5, #-4] @@ -1268,6 +1348,17 @@ 0x1d 0xf9 0x12 0xf0 0x1d 0xf9 0x02 0xf0 +#------------------------------------------------------------------------------ +# PLI(literal) +#------------------------------------------------------------------------------ +# CHECK: pli [pc, #-0] +# CHECK: pli [pc, #-328] +# CHECK: pli [pc, #0] + +0x1f 0xf9 0x00 0xf0 +0x1f 0xf9 0x48 0xf1 +0x9f 0xf9 0x00 0xf0 + #------------------------------------------------------------------------------ # QADD/QADD16/QADD8 @@ -1837,16 +1928,20 @@ #------------------------------------------------------------------------------ # STRD (immediate) #------------------------------------------------------------------------------ +# CHECK: strd r1, r1, [r0], #0 # CHECK: strd r6, r3, [r5], #-8 # CHECK: strd r8, r5, [r5], #-0 # CHECK: strd r7, r4, [r5], #-4 # CHECK: strd r0, r1, [r2, #-0]! +# CHECK: strd r0, r1, [r2, #0]! # CHECK: strd r0, r1, [r2, #-0] +0xe0 0xe8 0x00 0x11 0x65 0xe8 0x02 0x63 0x65 0xe8 0x00 0x85 0x65 0xe8 0x01 0x74 0x62 0xe9 0x00 0x01 +0xe2 0xe9 0x00 0x01 0x42 0xe9 0x00 0x01 #------------------------------------------------------------------------------ @@ -1878,6 +1973,7 @@ # CHECK: strh r5, [r8, #255]! # CHECK: strh r2, [r5, #4]! # CHECK: strh r1, [r4, #-4]! +# CHECK: strh r1, [r4, #0]! # CHECK: strh lr, [r3], #255 # CHECK: strh r9, [r2], #4 # CHECK: strh r3, [sp], #-4 @@ -1890,6 +1986,7 @@ 0x28 0xf8 0xff 0x5f 0x25 0xf8 0x04 0x2f 0x24 0xf8 0x04 0x1d +0x24 0xf8 0x00 0x1f 0x23 0xf8 0xff 0xeb 0x22 0xf8 0x04 0x9b 0x2d 0xf8 0x04 0x39 @@ -1954,6 +2051,7 @@ # CHECK: sub.w r12, r6, #256 # CHECK: subw r12, r6, #256 # CHECK: subs.w r1, r2, #496 +# CHECK: subs pc, lr, #4 0x0a 0xbf 0x11 0x1f @@ -1965,6 +2063,7 @@ 0xa6 0xf5 0x80 0x7c 0xa6 0xf2 0x00 0x1c 0xb2 0xf5 0xf8 0x71 +0xde 0xf3 0x04 0x8f #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/v8fp.txt b/test/MC/Disassembler/ARM/v8fp.txt new file mode 100644 index 0000000..a6e88b6 --- /dev/null +++ b/test/MC/Disassembler/ARM/v8fp.txt @@ -0,0 +1,155 @@ +# RUN: llvm-mc -disassemble -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s + +0xe0 0x3b 0xb2 0xee +# CHECK: vcvtt.f64.f16 d3, s1 + +0xcc 0x2b 0xf3 0xee +# CHECK: vcvtt.f16.f64 s5, d12 + +0x60 0x3b 0xb2 0xee +# CHECK: vcvtb.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xee +# CHECK: vcvtb.f16.f64 s4, d1 + +0xe0 0x3b 0xb2 0xae +# CHECK: vcvttge.f64.f16 d3, s1 + +0xcc 0x2b 0xf3 0xce +# CHECK: vcvttgt.f16.f64 s5, d12 + +0x60 0x3b 0xb2 0x0e +# CHECK: vcvtbeq.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xbe +# CHECK: vcvtblt.f16.f64 s4, d1 + + +0xe1 0x1a 0xbc 0xfe +# CHECK: vcvta.s32.f32 s2, s3 + +0xc3 0x1b 0xbc 0xfe +# CHECK: vcvta.s32.f64 s2, d3 + +0xeb 0x3a 0xbd 0xfe +# CHECK: vcvtn.s32.f32 s6, s23 + +0xe7 0x3b 0xbd 0xfe +# CHECK: vcvtn.s32.f64 s6, d23 + +0xc2 0x0a 0xbe 0xfe +# CHECK: vcvtp.s32.f32 s0, s4 + +0xc4 0x0b 0xbe 0xfe +# CHECK: vcvtp.s32.f64 s0, d4 + +0xc4 0x8a 0xff 0xfe +# CHECK: vcvtm.s32.f32 s17, s8 + +0xc8 0x8b 0xff 0xfe +# CHECK: vcvtm.s32.f64 s17, d8 + +0x61 0x1a 0xbc 0xfe +# CHECK: vcvta.u32.f32 s2, s3 + +0x43 0x1b 0xbc 0xfe +# CHECK: vcvta.u32.f64 s2, d3 + +0x6b 0x3a 0xbd 0xfe +# CHECK: vcvtn.u32.f32 s6, s23 + +0x67 0x3b 0xbd 0xfe +# CHECK: vcvtn.u32.f64 s6, d23 + +0x42 0x0a 0xbe 0xfe +# CHECK: vcvtp.u32.f32 s0, s4 + +0x44 0x0b 0xbe 0xfe +# CHECK: vcvtp.u32.f64 s0, d4 + +0x44 0x8a 0xff 0xfe +# CHECK: vcvtm.u32.f32 s17, s8 + +0x48 0x8b 0xff 0xfe +# CHECK: vcvtm.u32.f64 s17, d8 + + +0xab 0x2a 0x20 0xfe +# CHECK: vselge.f32 s4, s1, s23 + +0xa7 0xeb 0x6f 0xfe +# CHECK: vselge.f64 d30, d31, d23 + +0x80 0x0a 0x30 0xfe +# CHECK: vselgt.f32 s0, s1, s0 + +0x24 0x5b 0x3a 0xfe +# CHECK: vselgt.f64 d5, d10, d20 + +0x2b 0xfa 0x0e 0xfe +# CHECK: vseleq.f32 s30, s28, s23 + +0x08 0x2b 0x04 0xfe +# CHECK: vseleq.f64 d2, d4, d8 + +0x07 0xaa 0x58 0xfe +# CHECK: vselvs.f32 s21, s16, s14 + +0x2f 0x0b 0x11 0xfe +# CHECK: vselvs.f64 d0, d1, d31 + + +0x00 0x2a 0xc6 0xfe +# CHECK: vmaxnm.f32 s5, s12, s0 + +0xae 0x5b 0x86 0xfe +# CHECK: vmaxnm.f64 d5, d22, d30 + +0x46 0x0a 0x80 0xfe +# CHECK: vminnm.f32 s0, s0, s12 + +0x49 0x4b 0x86 0xfe +# CHECK: vminnm.f64 d4, d6, d9 + + +0xcc 0x3b 0xb6 0xae +# CHECK: vrintzge.f64 d3, d12 + +0xcc 0x1a 0xf6 0xee +# CHECK: vrintz.f32 s3, s24 + +0x40 0x5b 0xb6 0xbe +# CHECK: vrintrlt.f64 d5, d0 + +0x64 0x0a 0xb6 0xee +# CHECK: vrintr.f32 s0, s9 + +0x6e 0xcb 0xf7 0x0e +# CHECK: vrintxeq.f64 d28, d30 + +0x47 0x5a 0xb7 0x6e +# CHECK: vrintxvs.f32 s10, s14 + +0x44 0x3b 0xb8 0xfe +# CHECK: vrinta.f64 d3, d4 + +0x60 0x6a 0xb8 0xfe +# CHECK: vrinta.f32 s12, s1 + +0x44 0x3b 0xb9 0xfe +# CHECK: vrintn.f64 d3, d4 + +0x60 0x6a 0xb9 0xfe +# CHECK: vrintn.f32 s12, s1 + +0x44 0x3b 0xba 0xfe +# CHECK: vrintp.f64 d3, d4 + +0x60 0x6a 0xba 0xfe +# CHECK: vrintp.f32 s12, s1 + +0x44 0x3b 0xbb 0xfe +# CHECK: vrintm.f64 d3, d4 + +0x60 0x6a 0xbb 0xfe +# CHECK: vrintm.f32 s12, s1 diff --git a/test/MC/Disassembler/MBlaze/lit.local.cfg b/test/MC/Disassembler/MBlaze/lit.local.cfg deleted file mode 100644 index 3955b4e..0000000 --- a/test/MC/Disassembler/MBlaze/lit.local.cfg +++ /dev/null @@ -1,6 +0,0 @@ -config.suffixes = ['.txt'] - -targets = set(config.root.targets_to_build.split()) -if not 'MBlaze' in targets: - config.unsupported = True - diff --git a/test/MC/Disassembler/MBlaze/mblaze_branch.txt b/test/MC/Disassembler/MBlaze/mblaze_branch.txt deleted file mode 100644 index 5f40517..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_branch.txt +++ /dev/null @@ -1,119 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Branch instructions -################################################################################ - -# CHECK: beq r2, r3 -0x9c 0x02 0x18 0x00 - -# CHECK: bge r2, r3 -0x9c 0xa2 0x18 0x00 - -# CHECK: bgt r2, r3 -0x9c 0x82 0x18 0x00 - -# CHECK: ble r2, r3 -0x9c 0x62 0x18 0x00 - -# CHECK: blt r2, r3 -0x9c 0x42 0x18 0x00 - -# CHECK: bne r2, r3 -0x9c 0x22 0x18 0x00 - -# CHECK: beqd r2, r3 -0x9e 0x02 0x18 0x00 - -# CHECK: bged r2, r3 -0x9e 0xa2 0x18 0x00 - -# CHECK: bgtd r2, r3 -0x9e 0x82 0x18 0x00 - -# CHECK: bled r2, r3 -0x9e 0x62 0x18 0x00 - -# CHECK: bltd r2, r3 -0x9e 0x42 0x18 0x00 - -# CHECK: bned r2, r3 -0x9e 0x22 0x18 0x00 - -# CHECK: br r3 -0x98 0x00 0x18 0x00 - -# CHECK: bra r3 -0x98 0x08 0x18 0x00 - -# CHECK: brd r3 -0x98 0x10 0x18 0x00 - -# CHECK: brad r3 -0x98 0x18 0x18 0x00 - -# CHECK: brld r15, r3 -0x99 0xf4 0x18 0x00 - -# CHECK: brald r15, r3 -0x99 0xfc 0x18 0x00 - -# CHECK: brk r15, r3 -0x99 0xec 0x18 0x00 - -# CHECK: beqi r2, 0 -0xbc 0x02 0x00 0x00 - -# CHECK: bgei r2, 0 -0xbc 0xa2 0x00 0x00 - -# CHECK: bgti r2, 0 -0xbc 0x82 0x00 0x00 - - # CHECK: blei r2, 0 -0xbc 0x62 0x00 0x00 - -# CHECK: blti r2, 0 -0xbc 0x42 0x00 0x00 - -# CHECK: bnei r2, 0 -0xbc 0x22 0x00 0x00 - -# CHECK: beqid r2, 0 -0xbe 0x02 0x00 0x00 - -# CHECK: bgeid r2, 0 -0xbe 0xa2 0x00 0x00 - -# CHECK: bgtid r2, 0 -0xbe 0x82 0x00 0x00 - -# CHECK: bleid r2, 0 -0xbe 0x62 0x00 0x00 - -# CHECK: bltid r2, 0 -0xbe 0x42 0x00 0x00 - -# CHECK: bneid r2, 0 -0xbe 0x22 0x00 0x00 - -# CHECK: bri 0 -0xb8 0x00 0x00 0x00 - -# CHECK: brai 0 -0xb8 0x08 0x00 0x00 - -# CHECK: brid 0 -0xb8 0x10 0x00 0x00 - -# CHECK: braid 0 -0xb8 0x18 0x00 0x00 - -# CHECK: brlid r15, 0 -0xb9 0xf4 0x00 0x00 - -# CHECK: bralid r15, 0 -0xb9 0xfc 0x00 0x00 - -# CHECK: brki r15, 0 -0xb9 0xec 0x00 0x00 diff --git a/test/MC/Disassembler/MBlaze/mblaze_fpu.txt b/test/MC/Disassembler/MBlaze/mblaze_fpu.txt deleted file mode 100644 index 0fb7abc..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_fpu.txt +++ /dev/null @@ -1,47 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# FPU instructions -################################################################################ - -# CHECK: fadd r0, r1, r2 -0x58 0x01 0x10 0x00 - -# CHECK: frsub r0, r1, r2 -0x58 0x01 0x10 0x80 - -# CHECK: fmul r0, r1, r2 -0x58 0x01 0x11 0x00 - -# CHECK: fdiv r0, r1, r2 -0x58 0x01 0x11 0x80 - -# CHECK: fsqrt r0, r1 -0x58 0x01 0x03 0x80 - -# CHECK: fint r0, r1 -0x58 0x01 0x03 0x00 - -# CHECK: flt r0, r1 -0x58 0x01 0x02 0x80 - -# CHECK: fcmp.un r0, r1, r2 -0x58 0x01 0x12 0x00 - -# CHECK: fcmp.lt r0, r1, r2 -0x58 0x01 0x12 0x10 - -# CHECK: fcmp.eq r0, r1, r2 -0x58 0x01 0x12 0x20 - -# CHECK: fcmp.le r0, r1, r2 -0x58 0x01 0x12 0x30 - -# CHECK: fcmp.gt r0, r1, r2 -0x58 0x01 0x12 0x40 - -# CHECK: fcmp.ne r0, r1, r2 -0x58 0x01 0x12 0x50 - -# CHECK: fcmp.ge r0, r1, r2 -0x58 0x01 0x12 0x60 diff --git a/test/MC/Disassembler/MBlaze/mblaze_fsl.txt b/test/MC/Disassembler/MBlaze/mblaze_fsl.txt deleted file mode 100644 index a12b3b4..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_fsl.txt +++ /dev/null @@ -1,338 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# FSL instructions -################################################################################ - -# CHECK: get r0, rfsl0 -0x6c 0x00 0x00 0x00 - -# CHECK: nget r0, rfsl0 -0x6c 0x00 0x40 0x00 - -# CHECK: cget r0, rfsl0 -0x6c 0x00 0x20 0x00 - -# CHECK: ncget r0, rfsl0 -0x6c 0x00 0x60 0x00 - -# CHECK: tget r0, rfsl0 -0x6c 0x00 0x10 0x00 - -# CHECK: tnget r0, rfsl0 -0x6c 0x00 0x50 0x00 - -# CHECK: tcget r0, rfsl0 -0x6c 0x00 0x30 0x00 - -# CHECK: tncget r0, rfsl0 -0x6c 0x00 0x70 0x00 - -# CHECK: aget r0, rfsl0 -0x6c 0x00 0x08 0x00 - -# CHECK: naget r0, rfsl0 -0x6c 0x00 0x48 0x00 - -# CHECK: caget r0, rfsl0 -0x6c 0x00 0x28 0x00 - -# CHECK: ncaget r0, rfsl0 -0x6c 0x00 0x68 0x00 - -# CHECK: taget r0, rfsl0 -0x6c 0x00 0x18 0x00 - -# CHECK: tnaget r0, rfsl0 -0x6c 0x00 0x58 0x00 - -# CHECK: tcaget r0, rfsl0 -0x6c 0x00 0x38 0x00 - -# CHECK: tncaget r0, rfsl0 -0x6c 0x00 0x78 0x00 - -# CHECK: eget r0, rfsl0 -0x6c 0x00 0x04 0x00 - -# CHECK: neget r0, rfsl0 -0x6c 0x00 0x44 0x00 - -# CHECK: ecget r0, rfsl0 -0x6c 0x00 0x24 0x00 - -# CHECK: necget r0, rfsl0 -0x6c 0x00 0x64 0x00 - -# CHECK: teget r0, rfsl0 -0x6c 0x00 0x14 0x00 - -# CHECK: tneget r0, rfsl0 -0x6c 0x00 0x54 0x00 - -# CHECK: tecget r0, rfsl0 -0x6c 0x00 0x34 0x00 - -# CHECK: tnecget r0, rfsl0 -0x6c 0x00 0x74 0x00 - -# CHECK: eaget r0, rfsl0 -0x6c 0x00 0x0c 0x00 - -# CHECK: neaget r0, rfsl0 -0x6c 0x00 0x4c 0x00 - -# CHECK: ecaget r0, rfsl0 -0x6c 0x00 0x2c 0x00 - -# CHECK: necaget r0, rfsl0 -0x6c 0x00 0x6c 0x00 - -# CHECK: teaget r0, rfsl0 -0x6c 0x00 0x1c 0x00 - -# CHECK: tneaget r0, rfsl0 -0x6c 0x00 0x5c 0x00 - -# CHECK: tecaget r0, rfsl0 -0x6c 0x00 0x3c 0x00 - -# CHECK: tnecaget r0, rfsl0 -0x6c 0x00 0x7c 0x00 - -# CHECK: getd r0, r1 -0x4c 0x00 0x08 0x00 - -# CHECK: ngetd r0, r1 -0x4c 0x00 0x0a 0x00 - -# CHECK: cgetd r0, r1 -0x4c 0x00 0x09 0x00 - -# CHECK: ncgetd r0, r1 -0x4c 0x00 0x0b 0x00 - -# CHECK: tgetd r0, r1 -0x4c 0x00 0x08 0x80 - -# CHECK: tngetd r0, r1 -0x4c 0x00 0x0a 0x80 - -# CHECK: tcgetd r0, r1 -0x4c 0x00 0x09 0x80 - -# CHECK: tncgetd r0, r1 -0x4c 0x00 0x0b 0x80 - -# CHECK: agetd r0, r1 -0x4c 0x00 0x08 0x40 - -# CHECK: nagetd r0, r1 -0x4c 0x00 0x0a 0x40 - -# CHECK: cagetd r0, r1 -0x4c 0x00 0x09 0x40 - -# CHECK: ncagetd r0, r1 -0x4c 0x00 0x0b 0x40 - -# CHECK: tagetd r0, r1 -0x4c 0x00 0x08 0xc0 - -# CHECK: tnagetd r0, r1 -0x4c 0x00 0x0a 0xc0 - -# CHECK: tcagetd r0, r1 -0x4c 0x00 0x09 0xc0 - -# CHECK: tncagetd r0, r1 -0x4c 0x00 0x0b 0xc0 - -# CHECK: egetd r0, r1 -0x4c 0x00 0x08 0x20 - -# CHECK: negetd r0, r1 -0x4c 0x00 0x0a 0x20 - -# CHECK: ecgetd r0, r1 -0x4c 0x00 0x09 0x20 - -# CHECK: necgetd r0, r1 -0x4c 0x00 0x0b 0x20 - -# CHECK: tegetd r0, r1 -0x4c 0x00 0x08 0xa0 - -# CHECK: tnegetd r0, r1 -0x4c 0x00 0x0a 0xa0 - -# CHECK: tecgetd r0, r1 -0x4c 0x00 0x09 0xa0 - -# CHECK: tnecgetd r0, r1 -0x4c 0x00 0x0b 0xa0 - -# CHECK: eagetd r0, r1 -0x4c 0x00 0x08 0x60 - -# CHECK: neagetd r0, r1 -0x4c 0x00 0x0a 0x60 - -# CHECK: ecagetd r0, r1 -0x4c 0x00 0x09 0x60 - -# CHECK: necagetd r0, r1 -0x4c 0x00 0x0b 0x60 - -# CHECK: teagetd r0, r1 -0x4c 0x00 0x08 0xe0 - -# CHECK: tneagetd r0, r1 -0x4c 0x00 0x0a 0xe0 - -# CHECK: tecagetd r0, r1 -0x4c 0x00 0x09 0xe0 - -# CHECK: tnecagetd r0, r1 -0x4c 0x00 0x0b 0xe0 - -# CHECK: put r0, rfsl0 -0x6c 0x00 0x80 0x00 - -# CHECK: aput r0, rfsl0 -0x6c 0x00 0x88 0x00 - -# CHECK: cput r0, rfsl0 -0x6c 0x00 0xa0 0x00 - -# CHECK: caput r0, rfsl0 -0x6c 0x00 0xa8 0x00 - -# CHECK: nput r0, rfsl0 -0x6c 0x00 0xc0 0x00 - -# CHECK: naput r0, rfsl0 -0x6c 0x00 0xc8 0x00 - -# CHECK: ncput r0, rfsl0 -0x6c 0x00 0xe0 0x00 - -# CHECK: ncaput r0, rfsl0 -0x6c 0x00 0xe8 0x00 - -# CHECK: tput rfsl0 -0x6c 0x00 0x90 0x00 - -# CHECK: taput rfsl0 -0x6c 0x00 0x98 0x00 - -# CHECK: tcput rfsl0 -0x6c 0x00 0xb0 0x00 - -# CHECK: tcaput rfsl0 -0x6c 0x00 0xb8 0x00 - -# CHECK: tnput rfsl0 -0x6c 0x00 0xd0 0x00 - -# CHECK: tnaput rfsl0 -0x6c 0x00 0xd8 0x00 - -# CHECK: tncput rfsl0 -0x6c 0x00 0xf0 0x00 - -# CHECK: tncaput rfsl0 -0x6c 0x00 0xf8 0x00 - -# CHECK: putd r0, r1 -0x4c 0x00 0x0c 0x00 - -# CHECK: aputd r0, r1 -0x4c 0x00 0x0c 0x40 - -# CHECK: cputd r0, r1 -0x4c 0x00 0x0d 0x00 - -# CHECK: caputd r0, r1 -0x4c 0x00 0x0d 0x40 - -# CHECK: nputd r0, r1 -0x4c 0x00 0x0e 0x00 - -# CHECK: naputd r0, r1 -0x4c 0x00 0x0e 0x40 - -# CHECK: ncputd r0, r1 -0x4c 0x00 0x0f 0x00 - -# CHECK: ncaputd r0, r1 -0x4c 0x00 0x0f 0x40 - -# CHECK: tputd r1 -0x4c 0x00 0x0c 0x80 - -# CHECK: taputd r1 -0x4c 0x00 0x0c 0xc0 - -# CHECK: tcputd r1 -0x4c 0x00 0x0d 0x80 - -# CHECK: tcaputd r1 -0x4c 0x00 0x0d 0xc0 - -# CHECK: tnputd r1 -0x4c 0x00 0x0e 0x80 - -# CHECK: tnaputd r1 -0x4c 0x00 0x0e 0xc0 - -# CHECK: tncputd r1 -0x4c 0x00 0x0f 0x80 - -# CHECK: tncaputd r1 -0x4c 0x00 0x0f 0xc0 - -# CHECK: get r0, rfsl1 -0x6c 0x00 0x00 0x01 - -# CHECK: get r0, rfsl2 -0x6c 0x00 0x00 0x02 - -# CHECK: get r0, rfsl3 -0x6c 0x00 0x00 0x03 - -# CHECK: get r0, rfsl4 -0x6c 0x00 0x00 0x04 - -# CHECK: get r0, rfsl5 -0x6c 0x00 0x00 0x05 - -# CHECK: get r0, rfsl6 -0x6c 0x00 0x00 0x06 - -# CHECK: get r0, rfsl7 -0x6c 0x00 0x00 0x07 - -# CHECK: get r0, rfsl8 -0x6c 0x00 0x00 0x08 - -# CHECK: get r0, rfsl9 -0x6c 0x00 0x00 0x09 - -# CHECK: get r0, rfsl10 -0x6c 0x00 0x00 0x0a - -# CHECK: get r0, rfsl11 -0x6c 0x00 0x00 0x0b - -# CHECK: get r0, rfsl12 -0x6c 0x00 0x00 0x0c - -# CHECK: get r0, rfsl13 -0x6c 0x00 0x00 0x0d - -# CHECK: get r0, rfsl14 -0x6c 0x00 0x00 0x0e - -# CHECK: get r0, rfsl15 -0x6c 0x00 0x00 0x0f diff --git a/test/MC/Disassembler/MBlaze/mblaze_imm.txt b/test/MC/Disassembler/MBlaze/mblaze_imm.txt deleted file mode 100644 index 3833ea8..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_imm.txt +++ /dev/null @@ -1,121 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# IMM instruction processing -################################################################################ - -# CHECK: addi r0, r0, 0 -0x20 0x00 0x00 0x00 - -# CHECK: addi r0, r0, 1 -0x20 0x00 0x00 0x01 - -# CHECK: addi r0, r0, 2 -0x20 0x00 0x00 0x02 - -# CHECK: addi r0, r0, 4 -0x20 0x00 0x00 0x04 - -# CHECK: addi r0, r0, 8 -0x20 0x00 0x00 0x08 - -# CHECK: addi r0, r0, 16 -0x20 0x00 0x00 0x10 - -# CHECK: addi r0, r0, 32 -0x20 0x00 0x00 0x20 - -# CHECK: addi r0, r0, 64 -0x20 0x00 0x00 0x40 - -# CHECK: addi r0, r0, 128 -0x20 0x00 0x00 0x80 - -# CHECK: addi r0, r0, 256 -0x20 0x00 0x01 0x00 - -# CHECK: addi r0, r0, 512 -0x20 0x00 0x02 0x00 - -# CHECK: addi r0, r0, 1024 -0x20 0x00 0x04 0x00 - -# CHECK: addi r0, r0, 2048 -0x20 0x00 0x08 0x00 - -# CHECK: addi r0, r0, 4096 -0x20 0x00 0x10 0x00 - -# CHECK: addi r0, r0, 8192 -0x20 0x00 0x20 0x00 - -# CHECK: addi r0, r0, 16384 -0x20 0x00 0x40 0x00 - -# CHECK: imm 0 -# CHECK: addi r0, r0, -32768 -0xb0 0x00 0x00 0x00 0x20 0x00 0x80 0x00 - -# CHECK: imm 1 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x01 0x20 0x00 0x00 0x00 - -# CHECK: imm 2 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x02 0x20 0x00 0x00 0x00 - -# CHECK: imm 4 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x04 0x20 0x00 0x00 0x00 - -# CHECK: imm 8 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x08 0x20 0x00 0x00 0x00 - -# CHECK: imm 16 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x10 0x20 0x00 0x00 0x00 - -# CHECK: imm 32 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x20 0x20 0x00 0x00 0x00 - -# CHECK: imm 64 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x40 0x20 0x00 0x00 0x00 - -# CHECK: imm 128 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x00 0x80 0x20 0x00 0x00 0x00 - -# CHECK: imm 256 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x01 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm 512 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x02 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm 1024 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x04 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm 2048 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x08 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm 4096 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x10 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm 8192 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x20 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm 16384 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x40 0x00 0x20 0x00 0x00 0x00 - -# CHECK: imm -32768 -# CHECK: addi r0, r0, 0 -0xb0 0x00 0x80 0x00 0x20 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/MBlaze/mblaze_mbar.txt b/test/MC/Disassembler/MBlaze/mblaze_mbar.txt deleted file mode 100644 index 6beba86..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_mbar.txt +++ /dev/null @@ -1,14 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Memory Barrier instructions -################################################################################ - -# CHECK: mbar 0 -0xB8 0x02 0x00 0x04 - -# CHECK: mbar 1 -0xB8 0x22 0x00 0x04 - -# CHECK: mbar 2 -0xB8 0x42 0x00 0x04 diff --git a/test/MC/Disassembler/MBlaze/mblaze_memory.txt b/test/MC/Disassembler/MBlaze/mblaze_memory.txt deleted file mode 100644 index 584d61c..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_memory.txt +++ /dev/null @@ -1,65 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Memory instructions -################################################################################ - -# CHECK: lbu r1, r2, r3 -0xc0 0x22 0x18 0x00 - -# CHECK: lbur r1, r2, r3 -0xc0 0x22 0x1a 0x00 - -# CHECK: lbui r1, r2, 28 -0xe0 0x22 0x00 0x1c - -# CHECK: lhu r1, r2, r3 -0xc4 0x22 0x18 0x00 - -# CHECK: lhur r1, r2, r3 -0xc4 0x22 0x1a 0x00 - -# CHECK: lhui r1, r2, 28 -0xe4 0x22 0x00 0x1c - -# CHECK: lw r1, r2, r3 -0xc8 0x22 0x18 0x00 - -# CHECK: lwr r1, r2, r3 -0xc8 0x22 0x1a 0x00 - -# CHECK: lwi r1, r2, 28 -0xe8 0x22 0x00 0x1c - -# CHECK: lwx r1, r2, r3 -0xc8 0x22 0x1c 0x00 - -# CHECK: sb r1, r2, r3 -0xd0 0x22 0x18 0x00 - -# CHECK: sbr r1, r2, r3 -0xd0 0x22 0x1a 0x00 - -# CHECK: sbi r1, r2, 28 -0xf0 0x22 0x00 0x1c - -# CHECK: sh r1, r2, r3 -0xd4 0x22 0x18 0x00 - -# CHECK: shr r1, r2, r3 -0xd4 0x22 0x1a 0x00 - -# CHECK: shi r1, r2, 28 -0xf4 0x22 0x00 0x1c - -# CHECK: sw r1, r2, r3 -0xd8 0x22 0x18 0x00 - -# CHECK: swr r1, r2, r3 -0xd8 0x22 0x1a 0x00 - -# CHECK: swi r1, r2, 28 -0xf8 0x22 0x00 0x1c - -# CHECK: swx r1, r2, r3 -0xd8 0x22 0x1c 0x00 diff --git a/test/MC/Disassembler/MBlaze/mblaze_operands.txt b/test/MC/Disassembler/MBlaze/mblaze_operands.txt deleted file mode 100644 index f0304b1..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_operands.txt +++ /dev/null @@ -1,197 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Operands disassembly -################################################################################ - -# CHECK: add r0, r0, r0 -0x00 0x00 0x00 0x00 - -# CHECK: add r1, r1, r1 -0x00 0x21 0x08 0x00 - -# CHECK: add r2, r2, r2 -0x00 0x42 0x10 0x00 - -# CHECK: add r3, r3, r3 -0x00 0x63 0x18 0x00 - -# CHECK: add r4, r4, r4 -0x00 0x84 0x20 0x00 - -# CHECK: add r5, r5, r5 -0x00 0xa5 0x28 0x00 - -# CHECK: add r6, r6, r6 -0x00 0xc6 0x30 0x00 - -# CHECK: add r7, r7, r7 -0x00 0xe7 0x38 0x00 - -# CHECK: add r8, r8, r8 -0x01 0x08 0x40 0x00 - -# CHECK: add r9, r9, r9 -0x01 0x29 0x48 0x00 - -# CHECK: add r10, r10, r10 -0x01 0x4a 0x50 0x00 - -# CHECK: add r11, r11, r11 -0x01 0x6b 0x58 0x00 - -# CHECK: add r12, r12, r12 -0x01 0x8c 0x60 0x00 - -# CHECK: add r13, r13, r13 -0x01 0xad 0x68 0x00 - -# CHECK: add r14, r14, r14 -0x01 0xce 0x70 0x00 - -# CHECK: add r15, r15, r15 -0x01 0xef 0x78 0x00 - -# CHECK: add r16, r16, r16 -0x02 0x10 0x80 0x00 - -# CHECK: add r17, r17, r17 -0x02 0x31 0x88 0x00 - -# CHECK: add r18, r18, r18 -0x02 0x52 0x90 0x00 - -# CHECK: add r19, r19, r19 -0x02 0x73 0x98 0x00 - -# CHECK: add r20, r20, r20 -0x02 0x94 0xa0 0x00 - -# CHECK: add r21, r21, r21 -0x02 0xb5 0xa8 0x00 - -# CHECK: add r22, r22, r22 -0x02 0xd6 0xb0 0x00 - -# CHECK: add r23, r23, r23 -0x02 0xf7 0xb8 0x00 - -# CHECK: add r24, r24, r24 -0x03 0x18 0xc0 0x00 - -# CHECK: add r25, r25, r25 -0x03 0x39 0xc8 0x00 - -# CHECK: add r26, r26, r26 -0x03 0x5a 0xd0 0x00 - -# CHECK: add r27, r27, r27 -0x03 0x7b 0xd8 0x00 - -# CHECK: add r28, r28, r28 -0x03 0x9c 0xe0 0x00 - -# CHECK: add r29, r29, r29 -0x03 0xbd 0xe8 0x00 - -# CHECK: add r30, r30, r30 -0x03 0xde 0xf0 0x00 - -# CHECK: add r31, r31, r31 -0x03 0xff 0xf8 0x00 - -# CHECK: addi r0, r0, 0 -0x20 0x00 0x00 0x00 - -# CHECK: addi r0, r0, 1 -0x20 0x00 0x00 0x01 - -# CHECK: addi r0, r0, 2 -0x20 0x00 0x00 0x02 - -# CHECK: addi r0, r0, 4 -0x20 0x00 0x00 0x04 - -# CHECK: addi r0, r0, 8 -0x20 0x00 0x00 0x08 - -# CHECK: addi r0, r0, 16 -0x20 0x00 0x00 0x10 - -# CHECK: addi r0, r0, 32 -0x20 0x00 0x00 0x20 - -# CHECK: addi r0, r0, 64 -0x20 0x00 0x00 0x40 - -# CHECK: addi r0, r0, 128 -0x20 0x00 0x00 0x80 - -# CHECK: addi r0, r0, 256 -0x20 0x00 0x01 0x00 - -# CHECK: addi r0, r0, 512 -0x20 0x00 0x02 0x00 - -# CHECK: addi r0, r0, 1024 -0x20 0x00 0x04 0x00 - -# CHECK: addi r0, r0, 2048 -0x20 0x00 0x08 0x00 - -# CHECK: addi r0, r0, 4096 -0x20 0x00 0x10 0x00 - -# CHECK: addi r0, r0, 8192 -0x20 0x00 0x20 0x00 - -# CHECK: addi r0, r0, 16384 -0x20 0x00 0x40 0x00 - -# CHECK: addi r0, r0, -1 -0x20 0x00 0xff 0xff - -# CHECK: addi r0, r0, -2 -0x20 0x00 0xff 0xfe - -# CHECK: addi r0, r0, -4 -0x20 0x00 0xff 0xfc - -# CHECK: addi r0, r0, -8 -0x20 0x00 0xff 0xf8 - -# CHECK: addi r0, r0, -16 -0x20 0x00 0xff 0xf0 - -# CHECK: addi r0, r0, -32 -0x20 0x00 0xff 0xe0 - -# CHECK: addi r0, r0, -64 -0x20 0x00 0xff 0xc0 - -# CHECK: addi r0, r0, -128 -0x20 0x00 0xff 0x80 - -# CHECK: addi r0, r0, -256 -0x20 0x00 0xff 0x00 - -# CHECK: addi r0, r0, -512 -0x20 0x00 0xfe 0x00 - -# CHECK: addi r0, r0, -1024 -0x20 0x00 0xfc 0x00 - -# CHECK: addi r0, r0, -2048 -0x20 0x00 0xf8 0x00 - -# CHECK: addi r0, r0, -4096 -0x20 0x00 0xf0 0x00 - -# CHECK: addi r0, r0, -8192 -0x20 0x00 0xe0 0x00 - -# CHECK: addi r0, r0, -16384 -0x20 0x00 0xc0 0x00 - -# CHECK: addi r0, r0, -32768 -0x20 0x00 0x80 0x00 diff --git a/test/MC/Disassembler/MBlaze/mblaze_pattern.txt b/test/MC/Disassembler/MBlaze/mblaze_pattern.txt deleted file mode 100644 index cb19ee0..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_pattern.txt +++ /dev/null @@ -1,17 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Pattern instructions -################################################################################ - -# CHECK: pcmpbf r0, r1, r2 -0x80 0x01 0x14 0x00 - -# CHECK: pcmpne r0, r1, r2 -0x8c 0x01 0x14 0x00 - -# CHECK: pcmpeq r0, r1, r2 -0x88 0x01 0x14 0x00 - -# CHECK: clz r0, r1 -0x90 0x01 0x00 0xE0 diff --git a/test/MC/Disassembler/MBlaze/mblaze_shift.txt b/test/MC/Disassembler/MBlaze/mblaze_shift.txt deleted file mode 100644 index 2783ffc..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_shift.txt +++ /dev/null @@ -1,29 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Shift instructions -################################################################################ - -# CHECK: bsrl r1, r2, r3 -0x44 0x22 0x18 0x00 - -# CHECK: bsra r1, r2, r3 -0x44 0x22 0x1a 0x00 - -# CHECK: bsll r1, r2, r3 -0x44 0x22 0x1c 0x00 - -# CHECK: bsrli r1, r2, 0 -0x64 0x22 0x00 0x00 - -# CHECK: bsrai r1, r2, 0 -0x64 0x22 0x02 0x00 - -# CHECK: bslli r1, r2, 0 -0x64 0x22 0x04 0x00 - -# CHECK: sra r1, r2 -0x90 0x22 0x00 0x01 - -# CHECK: srl r1, r2 -0x90 0x22 0x00 0x41 diff --git a/test/MC/Disassembler/MBlaze/mblaze_special.txt b/test/MC/Disassembler/MBlaze/mblaze_special.txt deleted file mode 100644 index a808cc9..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_special.txt +++ /dev/null @@ -1,105 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# Special instructions -################################################################################ - -# CHECK: mfs r0, rpc -0x94 0x00 0x80 0x00 - -# CHECK: msrclr r0, 0 -0x94 0x11 0x00 0x00 - -# CHECK: msrset r0, 0 -0x94 0x10 0x00 0x00 - -# CHECK: mts rpc, r0 -0x94 0x00 0xc0 0x00 - -# CHECK: wdc r0, r1 -0x90 0x00 0x08 0x64 - -# CHECK: wdc.clear r0, r1 -0x90 0x00 0x08 0x66 - -# CHECK: wdc.flush r0, r1 -0x90 0x00 0x08 0x74 - -# CHECK: wic r0, r1 -0x90 0x00 0x08 0x68 - -################################################################################ -# Special registers -################################################################################ - -# CHECK: mfs r1, rpc -0x94 0x20 0x80 0x00 - -# CHECK: mfs r1, rmsr -0x94 0x20 0x80 0x01 - -# CHECK: mfs r1, rear -0x94 0x20 0x80 0x03 - -# CHECK: mfs r1, resr -0x94 0x20 0x80 0x05 - -# CHECK: mfs r1, rfsr -0x94 0x20 0x80 0x07 - -# CHECK: mfs r1, rbtr -0x94 0x20 0x80 0x0b - -# CHECK: mfs r1, redr -0x94 0x20 0x80 0x0d - -# CHECK: mfs r1, rpid -0x94 0x20 0x90 0x00 - -# CHECK: mfs r1, rzpr -0x94 0x20 0x90 0x01 - -# CHECK: mfs r1, rtlbx -0x94 0x20 0x90 0x02 - -# CHECK: mfs r1, rtlbhi -0x94 0x20 0x90 0x04 - -# CHECK: mfs r1, rtlblo -0x94 0x20 0x90 0x03 - -# CHECK: mfs r1, rpvr0 -0x94 0x20 0xa0 0x00 - -# CHECK: mfs r1, rpvr1 -0x94 0x20 0xa0 0x01 - -# CHECK: mfs r1, rpvr2 -0x94 0x20 0xa0 0x02 - -# CHECK: mfs r1, rpvr3 -0x94 0x20 0xa0 0x03 - -# CHECK: mfs r1, rpvr4 -0x94 0x20 0xa0 0x04 - -# CHECK: mfs r1, rpvr5 -0x94 0x20 0xa0 0x05 - -# CHECK: mfs r1, rpvr6 -0x94 0x20 0xa0 0x06 - -# CHECK: mfs r1, rpvr7 -0x94 0x20 0xa0 0x07 - -# CHECK: mfs r1, rpvr8 -0x94 0x20 0xa0 0x08 - -# CHECK: mfs r1, rpvr9 -0x94 0x20 0xa0 0x09 - -# CHECK: mfs r1, rpvr10 -0x94 0x20 0xa0 0x0a - -# CHECK: mfs r1, rpvr11 -0x94 0x20 0xa0 0x0b diff --git a/test/MC/Disassembler/MBlaze/mblaze_typea.txt b/test/MC/Disassembler/MBlaze/mblaze_typea.txt deleted file mode 100644 index ce99950..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_typea.txt +++ /dev/null @@ -1,74 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# TYPE A instructions -################################################################################ - -# CHECK: add r1, r2, r3 -0x00 0x22 0x18 0x00 - -# CHECK: addc r1, r2, r3 -0x08 0x22 0x18 0x00 - -# CHECK: addk r1, r2, r3 -0x10 0x22 0x18 0x00 - -# CHECK: addkc r1, r2, r3 -0x18 0x22 0x18 0x00 - -# CHECK: and r1, r2, r3 -0x84 0x22 0x18 0x00 - -# CHECK: andn r1, r2, r3 -0x8c 0x22 0x18 0x00 - -# CHECK: cmp r1, r2, r3 -0x14 0x22 0x18 0x01 - -# CHECK: cmpu r1, r2, r3 -0x14 0x22 0x18 0x03 - -# CHECK: idiv r1, r2, r3 -0x48 0x22 0x18 0x00 - -# CHECK: idivu r1, r2, r3 -0x48 0x22 0x18 0x02 - -# CHECK: mul r1, r2, r3 -0x40 0x22 0x18 0x00 - -# CHECK: mulh r1, r2, r3 -0x40 0x22 0x18 0x01 - -# CHECK: mulhu r1, r2, r3 -0x40 0x22 0x18 0x03 - -# CHECK: mulhsu r1, r2, r3 -0x40 0x22 0x18 0x02 - -# CHECK: or r1, r2, r3 -0x80 0x22 0x18 0x00 - -# CHECK: rsub r1, r2, r3 -0x04 0x22 0x18 0x00 - -# CHECK: rsubc r1, r2, r3 -0x0c 0x22 0x18 0x00 - -# CHECK: rsubk r1, r2, r3 -0x14 0x22 0x18 0x00 - -# CHECK: rsubkc r1, r2, r3 -0x1c 0x22 0x18 0x00 - -# CHECK: sext16 r1, r2 -0x90 0x22 0x00 0x61 - -# CHECK: sext8 r1, r2 -0x90 0x22 0x00 0x60 - -# CHECK: xor r1, r2, r3 -0x88 0x22 0x18 0x00 - -# CHECK: or r0, r0, r0 -0x80 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/MBlaze/mblaze_typeb.txt b/test/MC/Disassembler/MBlaze/mblaze_typeb.txt deleted file mode 100644 index 99782ac..0000000 --- a/test/MC/Disassembler/MBlaze/mblaze_typeb.txt +++ /dev/null @@ -1,56 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s - -################################################################################ -# TYPE B instructions -################################################################################ - -# CHECK: addi r1, r2, 15 -0x20 0x22 0x00 0x0f - -# CHECK: addic r1, r2, 15 -0x28 0x22 0x00 0x0f - -# CHECK: addik r1, r2, 15 -0x30 0x22 0x00 0x0f - -# CHECK: addikc r1, r2, 15 -0x38 0x22 0x00 0x0f - -# CHECK: andi r1, r2, 15 -0xa4 0x22 0x00 0x0f - -# CHECK: andni r1, r2, 15 -0xac 0x22 0x00 0x0f - -# CHECK: muli r1, r2, 15 -0x60 0x22 0x00 0x0f - -# CHECK: ori r1, r2, 15 -0xa0 0x22 0x00 0x0f - -# CHECK: rsubi r1, r2, 15 -0x24 0x22 0x00 0x0f - -# CHECK: rsubic r1, r2, 15 -0x2c 0x22 0x00 0x0f - -# CHECK: rsubik r1, r2, 15 -0x34 0x22 0x00 0x0f - -# CHECK: rsubikc r1, r2, 15 -0x3c 0x22 0x00 0x0f - -# CHECK: rtbd r15, 15 -0xb6 0x4f 0x00 0x0f - -# CHECK: rted r15, 15 -0xb6 0x8f 0x00 0x0f - -# CHECK: rtid r15, 15 -0xb6 0x2f 0x00 0x0f - -# CHECK: rtsd r15, 15 -0xb6 0x0f 0x00 0x0f - -# CHECK: xori r1, r2, 15 -0xa8 0x22 0x00 0x0f diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index ef8bf71..6d02925 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -35,9 +35,15 @@ # CHECK: bc1f 1332 0x45 0x00 0x01 0x4c +# CHECK: bc1f $fcc7, 1332 +0x45 0x1c 0x01 0x4c + # CHECK: bc1t 1332 0x45 0x01 0x01 0x4c +# CHECK: bc1t $fcc7, 1332 +0x45 0x1d 0x01 0x4c + # CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4c @@ -260,6 +266,24 @@ # CHECK: mov.s $f6, $f7 0x46 0x00 0x39 0x86 +# CHECK: movf $3, $2, $fcc7 +0x00,0x5c,0x18,0x01 + +# CHECK: movf.d $f4, $f2, $fcc7 +0x46,0x3c,0x11,0x11 + +# CHECK: movf.s $f4, $f2, $fcc7 +0x46,0x1c,0x11,0x11 + +# CHECK: movt $3, $2, $fcc7 +0x00,0x5d,0x18,0x01 + +# CHECK: movt.d $f4, $f2, $fcc7 +0x46,0x3d,0x11,0x11 + +# CHECK: movt.s $f4, $f2, $fcc7 +0x46,0x1d,0x11,0x11 + # CHECK: msub $6, $7 0x70 0xc7 0x00 0x04 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index a0885a4..61e6fc8 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -35,9 +35,15 @@ # CHECK: bc1f 1332 0x4c 0x01 0x00 0x45 +# CHECK: bc1f $fcc7, 1332 +0x4c 0x01 0x1c 0x45 + # CHECK: bc1t 1332 0x4c 0x01 0x01 0x45 +# CHECK: bc1t $fcc7, 1332 +0x4c 0x01 0x1d 0x45 + # CHECK: beq $9, $6, 1332 0x4c 0x01 0x26 0x11 @@ -260,6 +266,30 @@ # CHECK: mov.s $f6, $f7 0x86 0x39 0x00 0x46 +# CHECK: move $7, $8 +0x21,0x38,0x00,0x01 + +# CHECK: move $3, $2 +0x25,0x18,0x40,0x00 + +# CHECK: movf $3, $2, $fcc7 +0x01,0x18,0x5c,0x00 + +# CHECK: movf.d $f4, $f2, $fcc7 +0x11,0x11,0x3c,0x46 + +# CHECK: movf.s $f4, $f2, $fcc7 +0x11,0x11,0x1c,0x46 + +# CHECK: movt $3, $2, $fcc7 +0x01,0x18,0x5d,0x00 + +# CHECK: movt.d $f4, $f2, $fcc7 +0x11,0x11,0x3d,0x46 + +# CHECK: movt.s $f4, $f2, $fcc7 +0x11,0x11,0x1d,0x46 + # CHECK: msub $6, $7 0x04 0x00 0xc7 0x70 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 991eaa6..48b6ad4 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -35,9 +35,15 @@ # CHECK: bc1f 1332 0x45 0x00 0x01 0x4c +# CHECK: bc1f $fcc7, 1332 +0x45 0x1c 0x01 0x4c + # CHECK: bc1t 1332 0x45 0x01 0x01 0x4c +# CHECK: bc1t $fcc7, 1332 +0x45 0x1d 0x01 0x4c + # CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4c diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index 10c2938..c62c695 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -35,9 +35,15 @@ # CHECK: bc1f 1332 0x4c 0x01 0x00 0x45 +# CHECK: bc1f $fcc7, 1332 +0x4c 0x01 0x1c 0x45 + # CHECK: bc1t 1332 0x4c 0x01 0x01 0x45 +# CHECK: bc1t $fcc7, 1332 +0x4c 0x01 0x1d 0x45 + # CHECK: beq $9, $6, 1332 0x4c 0x01 0x26 0x11 diff --git a/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/test/MC/Disassembler/SystemZ/insns-pcrel.txt index f9e7774..c565b6e 100644 --- a/test/MC/Disassembler/SystemZ/insns-pcrel.txt +++ b/test/MC/Disassembler/SystemZ/insns-pcrel.txt @@ -1298,3 +1298,35 @@ # 0x0000075a: # CHECK: cij %r0, 0, 15, 0x75a 0xec 0x0f 0x00 0x00 0x00 0x7e + +# 0x00000760: +# CHECK: brct %r0, 0x760 +0xa7 0x06 0x00 0x00 + +# 0x00000764: +# CHECK: brct %r1, 0x762 +0xa7 0x16 0xff 0xff + +# 0x00000768: +# CHECK: brct %r9, 0xffffffffffff0768 +0xa7 0x96 0x80 0x00 + +# 0x0000076c: +# CHECK: brct %r15, 0x1076a +0xa7 0xf6 0x7f 0xff + +# 0x00000770: +# CHECK: brctg %r0, 0x770 +0xa7 0x07 0x00 0x00 + +# 0x00000774: +# CHECK: brctg %r1, 0x772 +0xa7 0x17 0xff 0xff + +# 0x00000778: +# CHECK: brctg %r9, 0xffffffffffff0778 +0xa7 0x97 0x80 0x00 + +# 0x0000077c: +# CHECK: brctg %r15, 0x1077a +0xa7 0xf7 0x7f 0xff diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 56236f7..51860cc 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -1,5 +1,5 @@ # Test instructions that don't have PC-relative operands. -# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s # CHECK: adbr %f0, %f0 0xb3 0x1a 0x00 0x00 @@ -163,6 +163,21 @@ # CHECK: aghi %r15, 0 0xa7 0xfb 0x00 0x00 +# CHECK: aghik %r0, %r1, -32768 +0xec 0x01 0x80 0x00 0x00 0xd9 + +# CHECK: aghik %r2, %r3, -1 +0xec 0x23 0xff 0xff 0x00 0xd9 + +# CHECK: aghik %r4, %r5, 0 +0xec 0x45 0x00 0x00 0x00 0xd9 + +# CHECK: aghik %r6, %r7, 1 +0xec 0x67 0x00 0x01 0x00 0xd9 + +# CHECK: aghik %r8, %r15, 32767 +0xec 0x8f 0x7f 0xff 0x00 0xd9 + # CHECK: agr %r0, %r0 0xb9 0x08 0x00 0x00 @@ -175,6 +190,12 @@ # CHECK: agr %r7, %r8 0xb9 0x08 0x00 0x78 +# CHECK: agrk %r0, %r0, %r0 +0xb9 0xe8 0x00 0x00 + +# CHECK: agrk %r2, %r3, %r4 +0xb9 0xe8 0x40 0x23 + # CHECK: agsi -524288, 0 0xeb 0x00 0x00 0x00 0x80 0x7a @@ -262,6 +283,21 @@ # CHECK: ahi %r15, 0 0xa7 0xfa 0x00 0x00 +# CHECK: ahik %r0, %r1, -32768 +0xec 0x01 0x80 0x00 0x00 0xd8 + +# CHECK: ahik %r2, %r3, -1 +0xec 0x23 0xff 0xff 0x00 0xd8 + +# CHECK: ahik %r4, %r5, 0 +0xec 0x45 0x00 0x00 0x00 0xd8 + +# CHECK: ahik %r6, %r7, 1 +0xec 0x67 0x00 0x01 0x00 0xd8 + +# CHECK: ahik %r8, %r15, 32767 +0xec 0x8f 0x7f 0xff 0x00 0xd8 + # CHECK: ah %r0, 0 0x4a 0x00 0x00 0x00 @@ -469,6 +505,12 @@ # CHECK: algr %r7, %r8 0xb9 0x0a 0x00 0x78 +# CHECK: algrk %r0, %r0, %r0 +0xb9 0xea 0x00 0x00 + +# CHECK: algrk %r2, %r3, %r4 +0xb9 0xea 0x40 0x23 + # CHECK: alg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x0a @@ -499,6 +541,36 @@ # CHECK: alg %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x0a +# CHECK: alghsik %r0, %r1, -32768 +0xec 0x01 0x80 0x00 0x00 0xdb + +# CHECK: alghsik %r2, %r3, -1 +0xec 0x23 0xff 0xff 0x00 0xdb + +# CHECK: alghsik %r4, %r5, 0 +0xec 0x45 0x00 0x00 0x00 0xdb + +# CHECK: alghsik %r6, %r7, 1 +0xec 0x67 0x00 0x01 0x00 0xdb + +# CHECK: alghsik %r8, %r15, 32767 +0xec 0x8f 0x7f 0xff 0x00 0xdb + +# CHECK: alhsik %r0, %r1, -32768 +0xec 0x01 0x80 0x00 0x00 0xda + +# CHECK: alhsik %r2, %r3, -1 +0xec 0x23 0xff 0xff 0x00 0xda + +# CHECK: alhsik %r4, %r5, 0 +0xec 0x45 0x00 0x00 0x00 0xda + +# CHECK: alhsik %r6, %r7, 1 +0xec 0x67 0x00 0x01 0x00 0xda + +# CHECK: alhsik %r8, %r15, 32767 +0xec 0x8f 0x7f 0xff 0x00 0xda + # CHECK: alr %r0, %r0 0x1e 0x00 @@ -511,6 +583,12 @@ # CHECK: alr %r7, %r8 0x1e 0x78 +# CHECK: alrk %r0, %r0, %r0 +0xb9 0xfa 0x00 0x00 + +# CHECK: alrk %r2, %r3, %r4 +0xb9 0xfa 0x40 0x23 + # CHECK: al %r0, 0 0x5e 0x00 0x00 0x00 @@ -574,6 +652,12 @@ # CHECK: ar %r7, %r8 0x1a 0x78 +# CHECK: ark %r0, %r0, %r0 +0xb9 0xf8 0x00 0x00 + +# CHECK: ark %r2, %r3, %r4 +0xb9 0xf8 0x40 0x23 + # CHECK: asi -524288, 0 0xeb 0x00 0x00 0x00 0x80 0x6a @@ -3178,6 +3262,198 @@ # CHECK: lnxbr %f13, %f9 0xb3 0x41 0x00 0xd9 +# CHECK: loc %r7, 6399(%r8), 0 +0xeb 0x70 0x88 0xff 0x01 0xf2 + +# CHECK: loco %r7, 6399(%r8) +0xeb 0x71 0x88 0xff 0x01 0xf2 + +# CHECK: loch %r7, 6399(%r8) +0xeb 0x72 0x88 0xff 0x01 0xf2 + +# CHECK: locnle %r7, 6399(%r8) +0xeb 0x73 0x88 0xff 0x01 0xf2 + +# CHECK: locl %r7, 6399(%r8) +0xeb 0x74 0x88 0xff 0x01 0xf2 + +# CHECK: locnhe %r7, 6399(%r8) +0xeb 0x75 0x88 0xff 0x01 0xf2 + +# CHECK: loclh %r7, 6399(%r8) +0xeb 0x76 0x88 0xff 0x01 0xf2 + +# CHECK: locne %r7, 6399(%r8) +0xeb 0x77 0x88 0xff 0x01 0xf2 + +# CHECK: loce %r7, 6399(%r8) +0xeb 0x78 0x88 0xff 0x01 0xf2 + +# CHECK: locnlh %r7, 6399(%r8) +0xeb 0x79 0x88 0xff 0x01 0xf2 + +# CHECK: loche %r7, 6399(%r8) +0xeb 0x7a 0x88 0xff 0x01 0xf2 + +# CHECK: locnl %r7, 6399(%r8) +0xeb 0x7b 0x88 0xff 0x01 0xf2 + +# CHECK: locle %r7, 6399(%r8) +0xeb 0x7c 0x88 0xff 0x01 0xf2 + +# CHECK: locnh %r7, 6399(%r8) +0xeb 0x7d 0x88 0xff 0x01 0xf2 + +# CHECK: locno %r7, 6399(%r8) +0xeb 0x7e 0x88 0xff 0x01 0xf2 + +# CHECK: loc %r7, 6399(%r8), 15 +0xeb 0x7f 0x88 0xff 0x01 0xf2 + +# CHECK: locg %r7, 6399(%r8), 0 +0xeb 0x70 0x88 0xff 0x01 0xe2 + +# CHECK: locgo %r7, 6399(%r8) +0xeb 0x71 0x88 0xff 0x01 0xe2 + +# CHECK: locgh %r7, 6399(%r8) +0xeb 0x72 0x88 0xff 0x01 0xe2 + +# CHECK: locgnle %r7, 6399(%r8) +0xeb 0x73 0x88 0xff 0x01 0xe2 + +# CHECK: locgl %r7, 6399(%r8) +0xeb 0x74 0x88 0xff 0x01 0xe2 + +# CHECK: locgnhe %r7, 6399(%r8) +0xeb 0x75 0x88 0xff 0x01 0xe2 + +# CHECK: locglh %r7, 6399(%r8) +0xeb 0x76 0x88 0xff 0x01 0xe2 + +# CHECK: locgne %r7, 6399(%r8) +0xeb 0x77 0x88 0xff 0x01 0xe2 + +# CHECK: locge %r7, 6399(%r8) +0xeb 0x78 0x88 0xff 0x01 0xe2 + +# CHECK: locgnlh %r7, 6399(%r8) +0xeb 0x79 0x88 0xff 0x01 0xe2 + +# CHECK: locghe %r7, 6399(%r8) +0xeb 0x7a 0x88 0xff 0x01 0xe2 + +# CHECK: locgnl %r7, 6399(%r8) +0xeb 0x7b 0x88 0xff 0x01 0xe2 + +# CHECK: locgle %r7, 6399(%r8) +0xeb 0x7c 0x88 0xff 0x01 0xe2 + +# CHECK: locgnh %r7, 6399(%r8) +0xeb 0x7d 0x88 0xff 0x01 0xe2 + +# CHECK: locgno %r7, 6399(%r8) +0xeb 0x7e 0x88 0xff 0x01 0xe2 + +# CHECK: locg %r7, 6399(%r8), 15 +0xeb 0x7f 0x88 0xff 0x01 0xe2 + +# CHECK: locr %r11, %r3, 0 +0xb9 0xf2 0x00 0xb3 + +# CHECK: locro %r11, %r3 +0xb9 0xf2 0x10 0xb3 + +# CHECK: locrh %r11, %r3 +0xb9 0xf2 0x20 0xb3 + +# CHECK: locrnle %r11, %r3 +0xb9 0xf2 0x30 0xb3 + +# CHECK: locrl %r11, %r3 +0xb9 0xf2 0x40 0xb3 + +# CHECK: locrnhe %r11, %r3 +0xb9 0xf2 0x50 0xb3 + +# CHECK: locrlh %r11, %r3 +0xb9 0xf2 0x60 0xb3 + +# CHECK: locrne %r11, %r3 +0xb9 0xf2 0x70 0xb3 + +# CHECK: locre %r11, %r3 +0xb9 0xf2 0x80 0xb3 + +# CHECK: locrnlh %r11, %r3 +0xb9 0xf2 0x90 0xb3 + +# CHECK: locrhe %r11, %r3 +0xb9 0xf2 0xa0 0xb3 + +# CHECK: locrnl %r11, %r3 +0xb9 0xf2 0xb0 0xb3 + +# CHECK: locrle %r11, %r3 +0xb9 0xf2 0xc0 0xb3 + +# CHECK: locrnh %r11, %r3 +0xb9 0xf2 0xd0 0xb3 + +# CHECK: locrno %r11, %r3 +0xb9 0xf2 0xe0 0xb3 + +# CHECK: locr %r11, %r3, 15 +0xb9 0xf2 0xf0 0xb3 + +# CHECK: locgr %r11, %r3, 0 +0xb9 0xe2 0x00 0xb3 + +# CHECK: locgro %r11, %r3 +0xb9 0xe2 0x10 0xb3 + +# CHECK: locgrh %r11, %r3 +0xb9 0xe2 0x20 0xb3 + +# CHECK: locgrnle %r11, %r3 +0xb9 0xe2 0x30 0xb3 + +# CHECK: locgrl %r11, %r3 +0xb9 0xe2 0x40 0xb3 + +# CHECK: locgrnhe %r11, %r3 +0xb9 0xe2 0x50 0xb3 + +# CHECK: locgrlh %r11, %r3 +0xb9 0xe2 0x60 0xb3 + +# CHECK: locgrne %r11, %r3 +0xb9 0xe2 0x70 0xb3 + +# CHECK: locgre %r11, %r3 +0xb9 0xe2 0x80 0xb3 + +# CHECK: locgrnlh %r11, %r3 +0xb9 0xe2 0x90 0xb3 + +# CHECK: locgrhe %r11, %r3 +0xb9 0xe2 0xa0 0xb3 + +# CHECK: locgrnl %r11, %r3 +0xb9 0xe2 0xb0 0xb3 + +# CHECK: locgrle %r11, %r3 +0xb9 0xe2 0xc0 0xb3 + +# CHECK: locgrnh %r11, %r3 +0xb9 0xe2 0xd0 0xb3 + +# CHECK: locgrno %r11, %r3 +0xb9 0xe2 0xe0 0xb3 + +# CHECK: locgr %r11, %r3, 15 +0xb9 0xe2 0xf0 0xb3 + # CHECK: lpdbr %f0, %f9 0xb3 0x10 0x00 0x09 @@ -3337,6 +3613,168 @@ # CHECK: l %r15, 0 0x58 0xf0 0x00 0x00 +# CHECK: lt %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x12 + +# CHECK: lt %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x12 + +# CHECK: lt %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x12 + +# CHECK: lt %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x12 + +# CHECK: lt %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x12 + +# CHECK: lt %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x12 + +# CHECK: lt %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x12 + +# CHECK: lt %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x12 + +# CHECK: lt %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x12 + +# CHECK: lt %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x12 + +# CHECK: ltdbr %f0, %f9 +0xb3 0x12 0x00 0x09 + +# CHECK: ltdbr %f0, %f15 +0xb3 0x12 0x00 0x0f + +# CHECK: ltdbr %f15, %f0 +0xb3 0x12 0x00 0xf0 + +# CHECK: ltdbr %f15, %f9 +0xb3 0x12 0x00 0xf9 + +# CHECK: ltebr %f0, %f9 +0xb3 0x02 0x00 0x09 + +# CHECK: ltebr %f0, %f15 +0xb3 0x02 0x00 0x0f + +# CHECK: ltebr %f15, %f0 +0xb3 0x02 0x00 0xf0 + +# CHECK: ltebr %f15, %f9 +0xb3 0x02 0x00 0xf9 + +# CHECK: ltg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x02 + +# CHECK: ltg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x02 + +# CHECK: ltg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x02 + +# CHECK: ltg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x02 + +# CHECK: ltg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x02 + +# CHECK: ltg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x02 + +# CHECK: ltg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x02 + +# CHECK: ltg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x02 + +# CHECK: ltg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x02 + +# CHECK: ltg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x02 + +# CHECK: ltgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x32 + +# CHECK: ltgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x32 + +# CHECK: ltgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x32 + +# CHECK: ltgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x32 + +# CHECK: ltgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x32 + +# CHECK: ltgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x32 + +# CHECK: ltgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x32 + +# CHECK: ltgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x32 + +# CHECK: ltgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x32 + +# CHECK: ltgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x32 + +# CHECK: ltgfr %r0, %r9 +0xb9 0x12 0x00 0x09 + +# CHECK: ltgfr %r0, %r15 +0xb9 0x12 0x00 0x0f + +# CHECK: ltgfr %r15, %r0 +0xb9 0x12 0x00 0xf0 + +# CHECK: ltgfr %r15, %r9 +0xb9 0x12 0x00 0xf9 + +# CHECK: ltgr %r0, %r9 +0xb9 0x02 0x00 0x09 + +# CHECK: ltgr %r0, %r15 +0xb9 0x02 0x00 0x0f + +# CHECK: ltgr %r15, %r0 +0xb9 0x02 0x00 0xf0 + +# CHECK: ltgr %r15, %r9 +0xb9 0x02 0x00 0xf9 + +# CHECK: ltr %r0, %r9 +0x12 0x09 + +# CHECK: ltr %r0, %r15 +0x12 0x0f + +# CHECK: ltr %r15, %r0 +0x12 0xf0 + +# CHECK: ltr %r15, %r9 +0x12 0xf9 + +# CHECK: ltxbr %f0, %f9 +0xb3 0x42 0x00 0x09 + +# CHECK: ltxbr %f0, %f13 +0xb3 0x42 0x00 0x0d + +# CHECK: ltxbr %f13, %f0 +0xb3 0x42 0x00 0xd0 + +# CHECK: ltxbr %f13, %f9 +0xb3 0x42 0x00 0xd9 + # CHECK: lxr %f0, %f8 0xb3 0x65 0x00 0x08 @@ -4207,6 +4645,12 @@ # CHECK: ng %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x80 +# CHECK: ngrk %r0, %r0, %r0 +0xb9 0xe4 0x00 0x00 + +# CHECK: ngrk %r2, %r3, %r4 +0xb9 0xe4 0x40 0x23 + # CHECK: ng %r0, -1 0xe3 0x00 0x0f 0xff 0xff 0x80 @@ -4363,6 +4807,12 @@ # CHECK: nr %r7, %r8 0x14 0x78 +# CHECK: nrk %r0, %r0, %r0 +0xb9 0xf4 0x00 0x00 + +# CHECK: nrk %r2, %r3, %r4 +0xb9 0xf4 0x40 0x23 + # CHECK: n %r0, 0 0x54 0x00 0x00 0x00 @@ -4426,6 +4876,12 @@ # CHECK: ogr %r7, %r8 0xb9 0x81 0x00 0x78 +# CHECK: ogrk %r0, %r0, %r0 +0xb9 0xe6 0x00 0x00 + +# CHECK: ogrk %r2, %r3, %r4 +0xb9 0xe6 0x40 0x23 + # CHECK: og %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x81 @@ -4585,6 +5041,12 @@ # CHECK: or %r7, %r8 0x16 0x78 +# CHECK: ork %r0, %r0, %r0 +0xb9 0xf6 0x00 0x00 + +# CHECK: ork %r2, %r3, %r4 +0xb9 0xf6 0x40 0x23 + # CHECK: o %r0, 0 0x56 0x00 0x00 0x00 @@ -4642,11 +5104,11 @@ # CHECK: risbg %r0, %r0, 0, 0, 63 0xec 0x00 0x00 0x00 0x3f 0x55 -# CHECK: risbg %r0, %r0, 0, 63, 0 -0xec 0x00 0x00 0x3f 0x00 0x55 +# CHECK: risbg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x55 -# CHECK: risbg %r0, %r0, 63, 0, 0 -0xec 0x00 0x3f 0x00 0x00 0x55 +# CHECK: risbg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x55 # CHECK: risbg %r0, %r15, 0, 0, 0 0xec 0x0f 0x00 0x00 0x00 0x55 @@ -4657,6 +5119,111 @@ # CHECK: risbg %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x55 +# CHECK: risbhg %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x5d + +# CHECK: risbhg %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x5d + +# CHECK: risbhg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x5d + +# CHECK: risbhg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x5d + +# CHECK: risbhg %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x5d + +# CHECK: risbhg %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x5d + +# CHECK: risbhg %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x5d + +# CHECK: risblg %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x51 + +# CHECK: risblg %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x51 + +# CHECK: risblg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x51 + +# CHECK: risblg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x51 + +# CHECK: risblg %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x51 + +# CHECK: risblg %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x51 + +# CHECK: risblg %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x51 + +# CHECK: rnsbg %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x54 + +# CHECK: rnsbg %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x54 + +# CHECK: rnsbg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x54 + +# CHECK: rnsbg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x54 + +# CHECK: rnsbg %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x54 + +# CHECK: rnsbg %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x54 + +# CHECK: rnsbg %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x54 + +# CHECK: rosbg %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x56 + +# CHECK: rosbg %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x56 + +# CHECK: rosbg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x56 + +# CHECK: rosbg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x56 + +# CHECK: rosbg %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x56 + +# CHECK: rosbg %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x56 + +# CHECK: rosbg %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x56 + +# CHECK: rxsbg %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x57 + +# CHECK: rxsbg %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x57 + +# CHECK: rxsbg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x57 + +# CHECK: rxsbg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x57 + +# CHECK: rxsbg %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x57 + +# CHECK: rxsbg %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x57 + +# CHECK: rxsbg %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x57 + # CHECK: rllg %r0, %r0, 0 0xeb 0x00 0x00 0x00 0x00 0x1c @@ -4849,6 +5416,12 @@ # CHECK: sgr %r7, %r8 0xb9 0x09 0x00 0x78 +# CHECK: sgrk %r0, %r0, %r0 +0xb9 0xe9 0x00 0x00 + +# CHECK: sgrk %r2, %r3, %r4 +0xb9 0xe9 0x40 0x23 + # CHECK: sg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x09 @@ -5086,6 +5659,12 @@ # CHECK: slgr %r7, %r8 0xb9 0x0b 0x00 0x78 +# CHECK: slgrk %r0, %r0, %r0 +0xb9 0xeb 0x00 0x00 + +# CHECK: slgrk %r2, %r3, %r4 +0xb9 0xeb 0x40 0x23 + # CHECK: slg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x0b @@ -5152,6 +5731,42 @@ # CHECK: sllg %r0, %r0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x0d +# CHECK: sllk %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0xdf + +# CHECK: sllk %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0xdf + +# CHECK: sllk %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0xdf + +# CHECK: sllk %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0xdf + +# CHECK: sllk %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0xdf + +# CHECK: sllk %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0xdf + +# CHECK: sllk %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0xdf + +# CHECK: sllk %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0xdf + +# CHECK: sllk %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0xdf + +# CHECK: sllk %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0xdf + +# CHECK: sllk %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0xdf + +# CHECK: sllk %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0xdf + # CHECK: sll %r0, 0 0x89 0x00 0x00 0x00 @@ -5188,6 +5803,12 @@ # CHECK: slr %r7, %r8 0x1f 0x78 +# CHECK: slrk %r0, %r0, %r0 +0xb9 0xfb 0x00 0x00 + +# CHECK: slrk %r2, %r3, %r4 +0xb9 0xfb 0x40 0x23 + # CHECK: sl %r0, 0 0x5f 0x00 0x00 0x00 @@ -5353,6 +5974,42 @@ # CHECK: srag %r0, %r0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x0a +# CHECK: srak %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0xdc + +# CHECK: srak %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0xdc + +# CHECK: srak %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0xdc + +# CHECK: srak %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0xdc + +# CHECK: srak %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0xdc + +# CHECK: srak %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0xdc + +# CHECK: srak %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0xdc + +# CHECK: srak %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0xdc + +# CHECK: srak %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0xdc + +# CHECK: srak %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0xdc + +# CHECK: srak %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0xdc + +# CHECK: srak %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0xdc + # CHECK: sra %r0, 0 0x8a 0x00 0x00 0x00 @@ -5413,6 +6070,42 @@ # CHECK: srlg %r0, %r0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x0c +# CHECK: srlk %r0, %r0, 0 +0xeb 0x00 0x00 0x00 0x00 0xde + +# CHECK: srlk %r15, %r1, 0 +0xeb 0xf1 0x00 0x00 0x00 0xde + +# CHECK: srlk %r1, %r15, 0 +0xeb 0x1f 0x00 0x00 0x00 0xde + +# CHECK: srlk %r15, %r15, 0 +0xeb 0xff 0x00 0x00 0x00 0xde + +# CHECK: srlk %r0, %r0, -524288 +0xeb 0x00 0x00 0x00 0x80 0xde + +# CHECK: srlk %r0, %r0, -1 +0xeb 0x00 0x0f 0xff 0xff 0xde + +# CHECK: srlk %r0, %r0, 1 +0xeb 0x00 0x00 0x01 0x00 0xde + +# CHECK: srlk %r0, %r0, 524287 +0xeb 0x00 0x0f 0xff 0x7f 0xde + +# CHECK: srlk %r0, %r0, 0(%r1) +0xeb 0x00 0x10 0x00 0x00 0xde + +# CHECK: srlk %r0, %r0, 0(%r15) +0xeb 0x00 0xf0 0x00 0x00 0xde + +# CHECK: srlk %r0, %r0, 524287(%r1) +0xeb 0x00 0x1f 0xff 0x7f 0xde + +# CHECK: srlk %r0, %r0, 524287(%r15) +0xeb 0x00 0xff 0xff 0x7f 0xde + # CHECK: srl %r0, 0 0x88 0x00 0x00 0x00 @@ -5449,6 +6142,12 @@ # CHECK: sr %r7, %r8 0x1b 0x78 +# CHECK: srk %r0, %r0, %r0 +0xb9 0xf9 0x00 0x00 + +# CHECK: srk %r2, %r3, %r4 +0xb9 0xf9 0x40 0x23 + # CHECK: stc %r0, 0 0x42 0x00 0x00 0x00 @@ -5803,6 +6502,102 @@ # CHECK: st %r15, 0 0x50 0xf0 0x00 0x00 +# CHECK: stoc %r1, 2(%r3), 0 +0xeb 0x10 0x30 0x02 0x00 0xf3 + +# CHECK: stoco %r1, 2(%r3) +0xeb 0x11 0x30 0x02 0x00 0xf3 + +# CHECK: stoch %r1, 2(%r3) +0xeb 0x12 0x30 0x02 0x00 0xf3 + +# CHECK: stocnle %r1, 2(%r3) +0xeb 0x13 0x30 0x02 0x00 0xf3 + +# CHECK: stocl %r1, 2(%r3) +0xeb 0x14 0x30 0x02 0x00 0xf3 + +# CHECK: stocnhe %r1, 2(%r3) +0xeb 0x15 0x30 0x02 0x00 0xf3 + +# CHECK: stoclh %r1, 2(%r3) +0xeb 0x16 0x30 0x02 0x00 0xf3 + +# CHECK: stocne %r1, 2(%r3) +0xeb 0x17 0x30 0x02 0x00 0xf3 + +# CHECK: stoce %r1, 2(%r3) +0xeb 0x18 0x30 0x02 0x00 0xf3 + +# CHECK: stocnlh %r1, 2(%r3) +0xeb 0x19 0x30 0x02 0x00 0xf3 + +# CHECK: stoche %r1, 2(%r3) +0xeb 0x1a 0x30 0x02 0x00 0xf3 + +# CHECK: stocnl %r1, 2(%r3) +0xeb 0x1b 0x30 0x02 0x00 0xf3 + +# CHECK: stocle %r1, 2(%r3) +0xeb 0x1c 0x30 0x02 0x00 0xf3 + +# CHECK: stocnh %r1, 2(%r3) +0xeb 0x1d 0x30 0x02 0x00 0xf3 + +# CHECK: stocno %r1, 2(%r3) +0xeb 0x1e 0x30 0x02 0x00 0xf3 + +# CHECK: stoc %r1, 2(%r3), 15 +0xeb 0x1f 0x30 0x02 0x00 0xf3 + +# CHECK: stocg %r1, 2(%r3), 0 +0xeb 0x10 0x30 0x02 0x00 0xe3 + +# CHECK: stocgo %r1, 2(%r3) +0xeb 0x11 0x30 0x02 0x00 0xe3 + +# CHECK: stocgh %r1, 2(%r3) +0xeb 0x12 0x30 0x02 0x00 0xe3 + +# CHECK: stocgnle %r1, 2(%r3) +0xeb 0x13 0x30 0x02 0x00 0xe3 + +# CHECK: stocgl %r1, 2(%r3) +0xeb 0x14 0x30 0x02 0x00 0xe3 + +# CHECK: stocgnhe %r1, 2(%r3) +0xeb 0x15 0x30 0x02 0x00 0xe3 + +# CHECK: stocglh %r1, 2(%r3) +0xeb 0x16 0x30 0x02 0x00 0xe3 + +# CHECK: stocgne %r1, 2(%r3) +0xeb 0x17 0x30 0x02 0x00 0xe3 + +# CHECK: stocge %r1, 2(%r3) +0xeb 0x18 0x30 0x02 0x00 0xe3 + +# CHECK: stocgnlh %r1, 2(%r3) +0xeb 0x19 0x30 0x02 0x00 0xe3 + +# CHECK: stocghe %r1, 2(%r3) +0xeb 0x1a 0x30 0x02 0x00 0xe3 + +# CHECK: stocgnl %r1, 2(%r3) +0xeb 0x1b 0x30 0x02 0x00 0xe3 + +# CHECK: stocgle %r1, 2(%r3) +0xeb 0x1c 0x30 0x02 0x00 0xe3 + +# CHECK: stocgnh %r1, 2(%r3) +0xeb 0x1d 0x30 0x02 0x00 0xe3 + +# CHECK: stocgno %r1, 2(%r3) +0xeb 0x1e 0x30 0x02 0x00 0xe3 + +# CHECK: stocg %r1, 2(%r3), 15 +0xeb 0x1f 0x30 0x02 0x00 0xe3 + # CHECK: s %r0, 0 0x5b 0x00 0x00 0x00 @@ -5908,6 +6703,12 @@ # CHECK: xgr %r7, %r8 0xb9 0x82 0x00 0x78 +# CHECK: xgrk %r0, %r0, %r0 +0xb9 0xe7 0x00 0x00 + +# CHECK: xgrk %r2, %r3, %r4 +0xb9 0xe7 0x40 0x23 + # CHECK: xg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x82 @@ -6019,6 +6820,12 @@ # CHECK: xr %r7, %r8 0x17 0x78 +# CHECK: xrk %r0, %r0, %r0 +0xb9 0xf7 0x00 0x00 + +# CHECK: xrk %r2, %r3, %r4 +0xb9 0xf7 0x40 0x23 + # CHECK: x %r0, 0 0x57 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index 57e602f..6c0c239 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -12,70 +12,70 @@ # CHECK: movsq 0x48 0xa5 -# CHECK: pop FS +# CHECK: pop fs 0x0f 0xa1 -# CHECK: pop GS +# CHECK: pop gs 0x0f 0xa9 -# CHECK: in AL, DX +# CHECK: in al, dx 0xec # CHECK: nop 0x90 -# CHECK: xchg EAX, R8D +# CHECK: xchg eax, r8d 0x41 0x90 -# CHECK: xchg RAX, R8 +# CHECK: xchg rax, r8 0x49 0x90 -# CHECK: add AL, 0 +# CHECK: add al, 0 0x04 0x00 -# CHECK: add AX, 0 +# CHECK: add ax, 0 0x66 0x05 0x00 0x00 -# CHECK: add EAX, 0 +# CHECK: add eax, 0 0x05 0x00 0x00 0x00 0x00 -# CHECK: add RAX, 0 +# CHECK: add rax, 0 0x48 0x05 0x00 0x00 0x00 0x00 -# CHECK: adc AL, 0 +# CHECK: adc al, 0 0x14 0x00 -# CHECK: adc AX, 0 +# CHECK: adc ax, 0 0x66 0x15 0x00 0x00 -# CHECK: adc EAX, 0 +# CHECK: adc eax, 0 0x15 0x00 0x00 0x00 0x00 -# CHECK: adc RAX, 0 +# CHECK: adc rax, 0 0x48 0x15 0x00 0x00 0x00 0x00 -# CHECK: cmp AL, 0 +# CHECK: cmp al, 0 0x3c 0x00 -# CHECK: cmp AX, 0 +# CHECK: cmp ax, 0 0x66 0x3d 0x00 0x00 -# CHECK: cmp EAX, 0 +# CHECK: cmp eax, 0 0x3d 0x00 0x00 0x00 0x00 -# CHECK: cmp RAX, 0 +# CHECK: cmp rax, 0 0x48 0x3d 0x00 0x00 0x00 0x00 -# CHECK: test AL, 0 +# CHECK: test al, 0 0xa8 0x00 -# CHECK: test AX, 0 +# CHECK: test ax, 0 0x66 0xa9 0x00 0x00 -# CHECK: test EAX, 0 +# CHECK: test eax, 0 0xa9 0x00 0x00 0x00 0x00 -# CHECK: test RAX, 0 +# CHECK: test rax, 0 0x48 0xa9 0x00 0x00 0x00 0x00 # CHECK: sysret @@ -105,17 +105,17 @@ # CHECK: retf 0x66 0xcb -# CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0 +# CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0 0xc4 0xe2 0xfd 0x91 0x14 0x4f -# CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 +# CHECK: vpgatherdd xmm10, dword ptr [r15 + 2*xmm9], xmm8 0xc4 0x02 0x39 0x90 0x14 0x4f -# CHECK: xsave64 OPAQUE PTR [RAX] +# CHECK: xsave64 opaque ptr [rax] 0x48 0x0f 0xae 0x20 -# CHECK: xrstor64 OPAQUE PTR [RAX] +# CHECK: xrstor64 opaque ptr [rax] 0x48 0x0f 0xae 0x28 -# CHECK: xsaveopt64 OPAQUE PTR [RAX] +# CHECK: xsaveopt64 opaque ptr [rax] 0x48 0x0f 0xae 0x30 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 9827a18..940b1f7 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -756,7 +756,7 @@ # rdar://13493622 lldb doesn't print the x86 rep/repne prefix when disassembling # CHECK: repne -# CHECK-NEXT: movsd +# CHECK-NEXT: movsl 0xf2 0xa5 # CHECK: repne # CHECK-NEXT: movsq @@ -764,7 +764,35 @@ # CHECK: repne # CHECK-NEXT: movb $0, (%rax) 0xf2 0xc6 0x0 0x0 -# CHECK: rep + +# rdar://11019859 Support 2013 Haswell RTM instructions and HLE prefixes +# CHECK: xrelease # CHECK-NEXT: lock # CHECK-NEXT: incl (%rax) 0xf3 0xf0 0xff 0x00 + +# CHECK: xrelease +# CHECK-NEXT: xchgl %ebx, %eax +0xf3 0x93 +# CHECK: xrelease +# CHECK-NEXT: xchgl %ebx, (%rax) +0xf3 0x87 0x18 +# CHECK: xrelease +# CHECK-NEXT: movb %al, (%rbx) +0xf3 0x88 0x03 +# CHECK: xrelease +# CHECK-NEXT: movl %eax, (%rbx) +0xf3 0x89 0x03 +# CHECK: xrelease +# CHECK-NEXT: movb $1, (%rbx) +0xf3 0xc6 0x03 0x01 +# CHECK: xrelease +# CHECK-NEXT: movl $1, (%rbx) +0xf3 0xc7 0x03 0x01 0x00 0x00 0x00 + +# CHECK: xacquire +# CHECK-NEXT: xchgl %ebx, %eax +0xf2 0x93 +# CHECK: xacquire +# CHECK-NEXT: xchgl %ebx, (%rax) +0xf2 0x87 0x18 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index c285af7..bf1fa21 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -127,3 +127,33 @@ # CHECK: stac 0x0f 0x01 0xcb + +# CHECK: movabsb -6066930261531658096, %al +0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsb -6066930261531658096, %al +0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsw -6066930261531658096, %ax +0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsl -6066930261531658096, %eax +0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsq -6066930261531658096, %rax +0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsb %al, -6066930261531658096 +0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsb %al, -6066930261531658096 +0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsw %ax, -6066930261531658096 +0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsl %eax, -6066930261531658096 +0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabsq %rax, -6066930261531658096 +0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab |