diff options
Diffstat (limited to 'test/MC')
159 files changed, 3893 insertions, 301 deletions
diff --git a/test/MC/AArch64/arm64-elf-reloc-condbr.s b/test/MC/AArch64/arm64-elf-reloc-condbr.s index 9b70a20..3182045 100644 --- a/test/MC/AArch64/arm64-elf-reloc-condbr.s +++ b/test/MC/AArch64/arm64-elf-reloc-condbr.s @@ -4,7 +4,7 @@ b.eq somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] diff --git a/test/MC/AArch64/arm64-fp-encoding-error.s b/test/MC/AArch64/arm64-fp-encoding-error.s new file mode 100644 index 0000000..ad30127 --- /dev/null +++ b/test/MC/AArch64/arm64-fp-encoding-error.s @@ -0,0 +1,8 @@ +; RUN: not llvm-mc -triple arm64-apple-ios8.0 %s -o /dev/null 2>&1 | FileCheck %s + + fmov s0, #-0.0 +; CHECK: error: expected compatible register or floating-point constant + + fmov d0, #-0.0 +; CHECK: error: expected compatible register or floating-point constant + diff --git a/test/MC/AArch64/armv8.1a-lor.s b/test/MC/AArch64/armv8.1a-lor.s new file mode 100644 index 0000000..309cb32 --- /dev/null +++ b/test/MC/AArch64/armv8.1a-lor.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s + + +//------------------------------------------------------------------------------ +// Load acquire / store release +//------------------------------------------------------------------------------ + ldlarb w0,[x1] + ldlarh w0,[x1] + ldlar w0,[x1] + ldlar x0,[x1] +// CHECK: ldlarb w0, [x1] // encoding: [0x20,0x7c,0xdf,0x08] +// CHECK: ldlarh w0, [x1] // encoding: [0x20,0x7c,0xdf,0x48] +// CHECK: ldlar w0, [x1] // encoding: [0x20,0x7c,0xdf,0x88] +// CHECK: ldlar x0, [x1] // encoding: [0x20,0x7c,0xdf,0xc8] + stllrb w0,[x1] + stllrh w0,[x1] + stllr w0,[x1] + stllr x0,[x1] +// CHECK: stllrb w0, [x1] // encoding: [0x20,0x7c,0x9f,0x08] +// CHECK: stllrh w0, [x1] // encoding: [0x20,0x7c,0x9f,0x48] +// CHECK: stllr w0, [x1] // encoding: [0x20,0x7c,0x9f,0x88] +// CHECK: stllr x0, [x1] // encoding: [0x20,0x7c,0x9f,0xc8] + + msr LORSA_EL1, x0 + msr LOREA_EL1, x0 + msr LORN_EL1, x0 + msr LORC_EL1, x0 + mrs x0, LORID_EL1 +// CHECK: msr LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5] +// CHECK: msr LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5] +// CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5] +// CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5] +// CHECK: mrs x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5] diff --git a/test/MC/AArch64/armv8.1a-pan.s b/test/MC/AArch64/armv8.1a-pan.s new file mode 100644 index 0000000..2068c81 --- /dev/null +++ b/test/MC/AArch64/armv8.1a-pan.s @@ -0,0 +1,30 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t + + .text + + msr pan, #0 +// CHECK: msr PAN, #0 // encoding: [0x9f,0x40,0x00,0xd5] + msr pan, #1 +// CHECK: msr PAN, #1 // encoding: [0x9f,0x41,0x00,0xd5] + msr pan, x5 +// CHECK: msr PAN, x5 // encoding: [0x65,0x42,0x18,0xd5] + mrs x13, pan +// CHECK: mrs x13, PAN // encoding: [0x6d,0x42,0x38,0xd5] + + msr pan, #-1 + msr pan, #20 + msr pan, w0 + mrs w0, pan +// CHECK-ERROR: error: immediate must be an integer in range [0, 15]. +// CHECK-ERROR: msr pan, #-1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: immediate must be an integer in range [0, 15]. +// CHECK-ERROR: msr pan, #20 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: immediate must be an integer in range [0, 15]. +// CHECK-ERROR: msr pan, w0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mrs w0, pan +// CHECK-ERROR: ^ diff --git a/test/MC/AArch64/armv8.1a-rdma.s b/test/MC/AArch64/armv8.1a-rdma.s new file mode 100644 index 0000000..1de2a0f --- /dev/null +++ b/test/MC/AArch64/armv8.1a-rdma.s @@ -0,0 +1,154 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s + .text + + //AdvSIMD RDMA vector + sqrdmlah v0.4h, v1.4h, v2.4h + sqrdmlsh v0.4h, v1.4h, v2.4h + sqrdmlah v0.2s, v1.2s, v2.2s + sqrdmlsh v0.2s, v1.2s, v2.2s + sqrdmlah v0.4s, v1.4s, v2.4s + sqrdmlsh v0.4s, v1.4s, v2.4s + sqrdmlah v0.8h, v1.8h, v2.8h + sqrdmlsh v0.8h, v1.8h, v2.8h +// CHECK: sqrdmlah v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x42,0x2e] +// CHECK: sqrdmlsh v0.4h, v1.4h, v2.4h // encoding: [0x20,0x8c,0x42,0x2e] +// CHECK: sqrdmlah v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0x82,0x2e] +// CHECK: sqrdmlsh v0.2s, v1.2s, v2.2s // encoding: [0x20,0x8c,0x82,0x2e] +// CHECK: sqrdmlah v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0x82,0x6e] +// CHECK: sqrdmlsh v0.4s, v1.4s, v2.4s // encoding: [0x20,0x8c,0x82,0x6e] +// CHECK: sqrdmlah v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x42,0x6e] +// CHECK: sqrdmlsh v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e] + + sqrdmlah v0.2h, v1.2h, v2.2h + sqrdmlsh v0.2h, v1.2h, v2.2h + sqrdmlah v0.8s, v1.8s, v2.8s + sqrdmlsh v0.8s, v1.8s, v2.8s + sqrdmlah v0.2s, v1.4h, v2.8h + sqrdmlsh v0.4s, v1.8h, v2.2s +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlah v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlah v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlah v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlsh v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlsh v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlsh v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlsh v0.2h, v1.2h, v2.2h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid vector kind qualifier +// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah v0.2s, v1.4h, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlsh v0.4s, v1.8h, v2.2s +// CHECK-ERROR: ^ + + //AdvSIMD RDMA scalar + sqrdmlah h0, h1, h2 + sqrdmlsh h0, h1, h2 + sqrdmlah s0, s1, s2 + sqrdmlsh s0, s1, s2 +// CHECK: sqrdmlah h0, h1, h2 // encoding: [0x20,0x84,0x42,0x7e] +// CHECK: sqrdmlsh h0, h1, h2 // encoding: [0x20,0x8c,0x42,0x7e] +// CHECK: sqrdmlah s0, s1, s2 // encoding: [0x20,0x84,0x82,0x7e] +// CHECK: sqrdmlsh s0, s1, s2 // encoding: [0x20,0x8c,0x82,0x7e] + + //AdvSIMD RDMA vector by-element + sqrdmlah v0.4h, v1.4h, v2.h[3] + sqrdmlsh v0.4h, v1.4h, v2.h[3] + sqrdmlah v0.2s, v1.2s, v2.s[1] + sqrdmlsh v0.2s, v1.2s, v2.s[1] + sqrdmlah v0.8h, v1.8h, v2.h[3] + sqrdmlsh v0.8h, v1.8h, v2.h[3] + sqrdmlah v0.4s, v1.4s, v2.s[3] + sqrdmlsh v0.4s, v1.4s, v2.s[3] +// CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3] // encoding: [0x20,0xd0,0x72,0x2f] +// CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3] // encoding: [0x20,0xf0,0x72,0x2f] +// CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1] // encoding: [0x20,0xd0,0xa2,0x2f] +// CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1] // encoding: [0x20,0xf0,0xa2,0x2f] +// CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3] // encoding: [0x20,0xd0,0x72,0x6f] +// CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3] // encoding: [0x20,0xf0,0x72,0x6f] +// CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3] // encoding: [0x20,0xd8,0xa2,0x6f] +// CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3] // encoding: [0x20,0xf8,0xa2,0x6f] + + sqrdmlah v0.4s, v1.2s, v2.s[1] + sqrdmlsh v0.2s, v1.2d, v2.s[1] + sqrdmlah v0.8h, v1.8h, v2.s[3] + sqrdmlsh v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah v0.4s, v1.2s, v2.s[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlsh v0.2s, v1.2d, v2.s[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah v0.8h, v1.8h, v2.s[3] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: vector lane must be an integer in range [0, 7]. +// CHECK-ERROR: sqrdmlsh v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: ^ + + //AdvSIMD RDMA scalar by-element + sqrdmlah h0, h1, v2.h[3] + sqrdmlsh h0, h1, v2.h[3] + sqrdmlah s0, s1, v2.s[3] + sqrdmlsh s0, s1, v2.s[3] +// CHECK: sqrdmlah h0, h1, v2.h[3] // encoding: [0x20,0xd0,0x72,0x7f] +// CHECK: sqrdmlsh h0, h1, v2.h[3] // encoding: [0x20,0xf0,0x72,0x7f] +// CHECK: sqrdmlah s0, s1, v2.s[3] // encoding: [0x20,0xd8,0xa2,0x7f] +// CHECK: sqrdmlsh s0, s1, v2.s[3] // encoding: [0x20,0xf8,0xa2,0x7f] + + sqrdmlah b0, h1, v2.h[3] + sqrdmlah s0, d1, v2.s[3] + sqrdmlsh h0, h1, v2.s[3] + sqrdmlsh s0, s1, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah b0, h1, v2.h[3] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlah s0, d1, v2.s[3] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmlsh h0, h1, v2.s[3] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: vector lane must be an integer in range [0, 3]. +// CHECK-ERROR: sqrdmlsh s0, s1, v2.s[4] +// CHECK-ERROR: ^ diff --git a/test/MC/AArch64/armv8.1a-vhe.s b/test/MC/AArch64/armv8.1a-vhe.s new file mode 100644 index 0000000..2bee4e2 --- /dev/null +++ b/test/MC/AArch64/armv8.1a-vhe.s @@ -0,0 +1,61 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s + + +//------------------------------------------------------------------------------ +// Virtualization Host Extensions +//------------------------------------------------------------------------------ + msr TTBR1_EL2, x0 + msr CONTEXTIDR_EL2, x0 + msr CNTHV_TVAL_EL2, x0 + msr CNTHV_CVAL_EL2, x0 + msr CNTHV_CTL_EL2, x0 + msr SCTLR_EL12, x0 + msr CPACR_EL12, x0 + msr TTBR0_EL12, x0 + msr TTBR1_EL12, x0 + msr TCR_EL12, x0 + msr AFSR0_EL12, x0 + msr AFSR1_EL12, x0 + msr ESR_EL12, x0 + msr FAR_EL12, x0 + msr MAIR_EL12, x0 + msr AMAIR_EL12, x0 + msr VBAR_EL12, x0 + msr CONTEXTIDR_EL12, x0 + msr CNTKCTL_EL12, x0 + msr CNTP_TVAL_EL02, x0 + msr CNTP_CTL_EL02, x0 + msr CNTP_CVAL_EL02, x0 + msr CNTV_TVAL_EL02, x0 + msr CNTV_CTL_EL02, x0 + msr CNTV_CVAL_EL02, x0 + msr SPSR_EL12, x0 + msr ELR_EL12, x0 + +// CHECK: msr TTBR1_EL2, x0 // encoding: [0x20,0x20,0x1c,0xd5] +// CHECK: msr CONTEXTIDR_EL2, x0 // encoding: [0x20,0xd0,0x1c,0xd5] +// CHECK: msr CNTHV_TVAL_EL2, x0 // encoding: [0x00,0xe3,0x1c,0xd5] +// CHECK: msr CNTHV_CVAL_EL2, x0 // encoding: [0x40,0xe3,0x1c,0xd5] +// CHECK: msr CNTHV_CTL_EL2, x0 // encoding: [0x20,0xe3,0x1c,0xd5] +// CHECK: msr SCTLR_EL12, x0 // encoding: [0x00,0x10,0x1d,0xd5] +// CHECK: msr CPACR_EL12, x0 // encoding: [0x40,0x10,0x1d,0xd5] +// CHECK: msr TTBR0_EL12, x0 // encoding: [0x00,0x20,0x1d,0xd5] +// CHECK: msr TTBR1_EL12, x0 // encoding: [0x20,0x20,0x1d,0xd5] +// CHECK: msr TCR_EL12, x0 // encoding: [0x40,0x20,0x1d,0xd5] +// CHECK: msr AFSR0_EL12, x0 // encoding: [0x00,0x51,0x1d,0xd5] +// CHECK: msr AFSR1_EL12, x0 // encoding: [0x20,0x51,0x1d,0xd5] +// CHECK: msr ESR_EL12, x0 // encoding: [0x00,0x52,0x1d,0xd5] +// CHECK: msr FAR_EL12, x0 // encoding: [0x00,0x60,0x1d,0xd5] +// CHECK: msr MAIR_EL12, x0 // encoding: [0x00,0xa2,0x1d,0xd5] +// CHECK: msr AMAIR_EL12, x0 // encoding: [0x00,0xa3,0x1d,0xd5] +// CHECK: msr VBAR_EL12, x0 // encoding: [0x00,0xc0,0x1d,0xd5] +// CHECK: msr CONTEXTIDR_EL12, x0 // encoding: [0x20,0xd0,0x1d,0xd5] +// CHECK: msr CNTKCTL_EL12, x0 // encoding: [0x00,0xe1,0x1d,0xd5] +// CHECK: msr CNTP_TVAL_EL02, x0 // encoding: [0x00,0xe2,0x1d,0xd5] +// CHECK: msr CNTP_CTL_EL02, x0 // encoding: [0x20,0xe2,0x1d,0xd5] +// CHECK: msr CNTP_CVAL_EL02, x0 // encoding: [0x40,0xe2,0x1d,0xd5] +// CHECK: msr CNTV_TVAL_EL02, x0 // encoding: [0x00,0xe3,0x1d,0xd5] +// CHECK: msr CNTV_CTL_EL02, x0 // encoding: [0x20,0xe3,0x1d,0xd5] +// CHECK: msr CNTV_CVAL_EL02, x0 // encoding: [0x40,0xe3,0x1d,0xd5] +// CHECK: msr SPSR_EL12, x0 // encoding: [0x00,0x40,0x1d,0xd5] +// CHECK: msr ELR_EL12, x0 // encoding: [0x20,0x40,0x1d,0xd5] diff --git a/test/MC/AArch64/elf-extern.s b/test/MC/AArch64/elf-extern.s index dfa3fb0..14c26c1 100644 --- a/test/MC/AArch64/elf-extern.s +++ b/test/MC/AArch64/elf-extern.s @@ -27,7 +27,7 @@ check_extern: // @check_extern // CHECK: Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy // CHECK: } // CHECK: ] diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll index 8e4ae4c..d8a0b5b 100644 --- a/test/MC/AArch64/elf-globaladdress.ll +++ b/test/MC/AArch64/elf-globaladdress.ll @@ -40,7 +40,7 @@ define void @address() { ; OBJ: } ; OBJ: Relocations [ -; OBJ: Section (2) .rela.text { +; OBJ: Section {{.*}} .rela.text { ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16 diff --git a/test/MC/AArch64/elf-reloc-addsubimm.s b/test/MC/AArch64/elf-reloc-addsubimm.s index e37991b..58e9a6e 100644 --- a/test/MC/AArch64/elf-reloc-addsubimm.s +++ b/test/MC/AArch64/elf-reloc-addsubimm.s @@ -4,7 +4,7 @@ add x2, x3, #:lo12:some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-ldrlit.s b/test/MC/AArch64/elf-reloc-ldrlit.s index d4c3a4e..017d66c 100644 --- a/test/MC/AArch64/elf-reloc-ldrlit.s +++ b/test/MC/AArch64/elf-reloc-ldrlit.s @@ -7,7 +7,7 @@ prfm pldl3keep, some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-ldstunsimm.s b/test/MC/AArch64/elf-reloc-ldstunsimm.s index 371e7e5..e68937c 100644 --- a/test/MC/AArch64/elf-reloc-ldstunsimm.s +++ b/test/MC/AArch64/elf-reloc-ldstunsimm.s @@ -8,7 +8,7 @@ str q0, [sp, #:lo12:some_label] // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_LDST8_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LDST16_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LDST32_ABS_LO12_NC some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-movw.s b/test/MC/AArch64/elf-reloc-movw.s index 3331595..fda160f 100644 --- a/test/MC/AArch64/elf-reloc-movw.s +++ b/test/MC/AArch64/elf-reloc-movw.s @@ -23,7 +23,7 @@ movn x19, #:abs_g2_s:some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_MOVW_UABS_G0 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_MOVW_UABS_G0_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_MOVW_UABS_G1 some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-pcreladdressing.s b/test/MC/AArch64/elf-reloc-pcreladdressing.s index 093891d..30acb6d 100644 --- a/test/MC/AArch64/elf-reloc-pcreladdressing.s +++ b/test/MC/AArch64/elf-reloc-pcreladdressing.s @@ -8,7 +8,7 @@ ldr x0, [x5, #:got_lo12:some_label] // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-tstb.s b/test/MC/AArch64/elf-reloc-tstb.s index 25c9816..e6828e6 100644 --- a/test/MC/AArch64/elf-reloc-tstb.s +++ b/test/MC/AArch64/elf-reloc-tstb.s @@ -5,7 +5,7 @@ tbnz w3, #15, somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: } diff --git a/test/MC/AArch64/elf-reloc-uncondbrimm.s b/test/MC/AArch64/elf-reloc-uncondbrimm.s index 9ac66bd..ff852be 100644 --- a/test/MC/AArch64/elf-reloc-uncondbrimm.s +++ b/test/MC/AArch64/elf-reloc-uncondbrimm.s @@ -5,7 +5,7 @@ bl somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rela.text { +// OBJ-NEXT: Section {{.*}} .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0 // OBJ-NEXT: } diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s index 9e94a52..bac4f20 100644 --- a/test/MC/AArch64/tls-relocs.s +++ b/test/MC/AArch64/tls-relocs.s @@ -18,7 +18,7 @@ // CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF: Relocations [ -// CHECK-ELF-NEXT: Section (2) .rela.text { +// CHECK-ELF-NEXT: Section {{.*}} .rela.text { // CHECK-ELF-NEXT: 0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]] // CHECK-ELF-NEXT: 0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] diff --git a/test/MC/ARM/2010-11-30-reloc-movt.s b/test/MC/ARM/2010-11-30-reloc-movt.s index 9de88f0..dc6960b 100644 --- a/test/MC/ARM/2010-11-30-reloc-movt.s +++ b/test/MC/ARM/2010-11-30-reloc-movt.s @@ -34,6 +34,7 @@ barf: @ @barf // CHECK-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB // CHECK-NEXT: 0010: 0088BDE8 // CHECK-NEXT: ) +// CHECK: Name: .rel.text // CHECK: Relocations [ // CHECK-NEXT: 0x4 R_ARM_MOVW_ABS_NC a // CHECK-NEXT: 0x8 R_ARM_MOVT_ABS diff --git a/test/MC/ARM/arm-elf-symver.s b/test/MC/ARM/arm-elf-symver.s index 5fb1f6a..26d7655 100644 --- a/test/MC/ARM/arm-elf-symver.s +++ b/test/MC/ARM/arm-elf-symver.s @@ -23,7 +23,7 @@ defined3: global1: @ CHECK: Relocations [ -@ CHECK-NEXT: Section (2) .rel.text { +@ CHECK-NEXT: Section {{.*}} .rel.text { @ CHECK-NEXT: 0x0 R_ARM_ABS32 .text 0x0 @ CHECK-NEXT: 0x4 R_ARM_ABS32 bar2@zed 0x0 @ CHECK-NEXT: 0x8 R_ARM_ABS32 .text 0x0 @@ -93,7 +93,7 @@ global1: @ CHECK-NEXT: Binding: Local (0x0) @ CHECK-NEXT: Type: Section (0x3) @ CHECK-NEXT: Other: 0 -@ CHECK-NEXT: Section: .data (0x3) +@ CHECK-NEXT: Section: .data @ CHECK-NEXT: } @ CHECK-NEXT: Symbol { @ CHECK-NEXT: Name: .bss (0) @@ -102,7 +102,7 @@ global1: @ CHECK-NEXT: Binding: Local (0x0) @ CHECK-NEXT: Type: Section (0x3) @ CHECK-NEXT: Other: 0 -@ CHECK-NEXT: Section: .bss (0x4) +@ CHECK-NEXT: Section: .bss @ CHECK-NEXT: } @ CHECK-NEXT: Symbol { @ CHECK-NEXT: Name: g1@@zed diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s index f46057b6..005f27b 100644 --- a/test/MC/ARM/basic-arm-instructions-v8.1a.s +++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s @@ -43,28 +43,28 @@ vqrdmlah.s16 d0, d1, d2 //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 d0, d1, d2 //CHECK-V8: ^ vqrdmlah.s32 d0, d1, d2 //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 d0, d1, d2 //CHECK-V8: ^ vqrdmlah.s16 q0, q1, q2 //CHECK-V81aARM: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x54,0x0b,0x12,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 q0, q1, q2 //CHECK-V8: ^ vqrdmlah.s32 q2, q3, q0 //CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 q2, q3, q0 //CHECK-V8: ^ @@ -72,28 +72,28 @@ vqrdmlsh.s16 d7, d6, d5 //CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 d7, d6, d5 //CHECK-V8: ^ vqrdmlsh.s32 d0, d1, d2 //CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x12,0x0c,0x21,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 d0, d1, d2 //CHECK-V8: ^ vqrdmlsh.s16 q0, q1, q2 //CHECK-V81aARM: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 q0, q1, q2 //CHECK-V8: ^ vqrdmlsh.s32 q3, q4, q5 //CHECK-V81aARM: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x5a,0x6c,0x28,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x28,0xff,0x5a,0x6c] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 q3, q4, q5 //CHECK-V8: ^ @@ -119,28 +119,28 @@ vqrdmlah.s16 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x42,0x0e,0x91,0xf2] //CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlah.s32 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0x42,0x0e,0xa1,0xf2] //CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlah.s16 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x42,0x0e,0x92,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s16 q0, q1, d2[0] //CHECK-V8: ^ vqrdmlah.s32 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0x42,0x0e,0xa2,0xf3] //CHECK-V81aTHUMB: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0e] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlah.s32 q0, q1, d2[0] //CHECK-V8: ^ @@ -148,27 +148,59 @@ vqrdmlsh.s16 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x42,0x0f,0x91,0xf2] //CHECK-V81aTHUMB: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlsh.s32 d0, d1, d2[0] //CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0x42,0x0f,0xa1,0xf2] //CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 d0, d1, d2[0] //CHECK-V8: ^ vqrdmlsh.s16 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x42,0x0f,0x92,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s16 q0, q1, d2[0] //CHECK-V8: ^ vqrdmlsh.s32 q0, q1, d2[0] //CHECK-V81aARM: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0x42,0x0f,0xa2,0xf3] //CHECK-V81aTHUMB: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0f] -//CHECK-V8: error: instruction requires: v8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0] //CHECK-V8: ^ + + setpan #0 +//CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6] +//CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1] +//CHECK-V8: error: instruction requires: armv8.1a +//CHECK-V8: setpan #0 +//CHECK-V8: ^ + + setpan #1 +//CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6] +//CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1] +//CHECK-V8: error: instruction requires: armv8.1a +//CHECK-V8: setpan #1 +//CHECK-V8: ^ + setpan + setpan #-1 + setpan #2 +//CHECK-ERROR: error: too few operands for instruction +//CHECK-ERROR: setpan +//CHECK-ERROR: ^ +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR: setpan #-1 +//CHECK-ERROR: ^ +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR: setpan #2 +//CHECK-ERROR: ^ + + it eq + setpaneq #0 +//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified +//CHECK-THUMB-ERROR: setpaneq #0 +//CHECK-THUMB-ERROR: ^ diff --git a/test/MC/ARM/eh-compact-pr0.s b/test/MC/ARM/eh-compact-pr0.s index 1d825bf..9c0581a 100644 --- a/test/MC/ARM/eh-compact-pr0.s +++ b/test/MC/ARM/eh-compact-pr0.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s +@ RUN: | llvm-readobj -s -sd -sr > %t +@ RUN: FileCheck %s < %t +@ RUN: FileCheck --check-prefix=RELOC %s < %t @ Check the compact pr0 model @@ -63,10 +65,13 @@ func2: @ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker @ will keep __aeabi_unwind_cpp_pr0. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- @@ -92,13 +97,15 @@ func2: @ CHECK: 0000: 00000000 B0808480 |........| @ CHECK: ) @ CHECK: } -@ CHECK: ] @------------------------------------------------------------------------------- @ The first word should be relocated to .TEST2 section. Besides, there is @ another relocation entry for __aeabi_unwind_cpp_pr0, so that the linker @ will keep __aeabi_unwind_cpp_pr0. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: ] +@ RELOC: } diff --git a/test/MC/ARM/eh-directive-handlerdata.s b/test/MC/ARM/eh-directive-handlerdata.s index 793d357..980a5f0 100644 --- a/test/MC/ARM/eh-directive-handlerdata.s +++ b/test/MC/ARM/eh-directive-handlerdata.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s +@ RUN: | llvm-readobj -s -sd -sr > %t +@ RUN: FileCheck %s < %t +@ RUN: FileCheck --check-prefix=RELOC %s < %t @ Check the .handlerdata directive (without .personality directive) @@ -43,11 +45,14 @@ func1: @ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the @ linker can keep __aeabi_unwind_cpp_pr0. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 -@ CHECK: ] +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ RELOC: ] +@ RELOC: } @@ -100,8 +105,11 @@ func2: @ We should see a relocation entry to __aeabi_unwind_cpp_pr0, so that the @ linker can keep __aeabi_unwind_cpp_pr0. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 -@ CHECK: ] +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 +@ RELOC: ] +@ RELOC: } diff --git a/test/MC/ARM/eh-directive-personality.s b/test/MC/ARM/eh-directive-personality.s index f493722..84e62bd 100644 --- a/test/MC/ARM/eh-directive-personality.s +++ b/test/MC/ARM/eh-directive-personality.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s +@ RUN: | llvm-readobj -s -sd -sr > %t +@ RUN: FileCheck %s < %t +@ RUN: FileCheck --check-prefix=RELOC %s < %t @ Check the .personality directive. @@ -32,19 +34,28 @@ func1: @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.extab.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ RELOC: ] +@ RELOC: } + @ CHECK: Section { @ CHECK: Name: .ARM.exidx.TEST1 @ CHECK: SectionData ( @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- @@ -74,16 +85,25 @@ func2: @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.extab.TEST2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ RELOC: ] +@ RELOC: } + @ CHECK: Section { @ CHECK: Name: .ARM.exidx.TEST2 @ CHECK: SectionData ( @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST2 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 +@ RELOC: ] +@ RELOC: } diff --git a/test/MC/ARM/eh-directive-personalityindex.s b/test/MC/ARM/eh-directive-personalityindex.s index 5517227..6db9425 100644 --- a/test/MC/ARM/eh-directive-personalityindex.s +++ b/test/MC/ARM/eh-directive-personalityindex.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc -triple armv7-linux-eabi -filetype obj -o - %s \ -@ RUN: | llvm-readobj -s -sd -sr | FileCheck %s +@ RUN: | llvm-readobj -s -sd -sr > %t +@ RUN: FileCheck %s < %t +@ RUN: FileCheck --check-prefix=RELOC %s < %t .syntax unified .thumb @@ -23,13 +25,13 @@ pr0: @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .rel.ARM.exidx.pr0 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .pr0 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] -@ CHECK: } +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.pr0 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .pr0 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: ] +@ RELOC: } .section .pr0.nontrivial @@ -52,13 +54,13 @@ pr0_nontrivial: @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .rel.ARM.exidx.pr0.nontrivial -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .pr0.nontrivial 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 -@ CHECK: ] -@ CHECK: } +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.pr0.nontrivial +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .pr0.nontrivial 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: ] +@ RELOC: } .section .pr1 @@ -85,14 +87,14 @@ pr1: @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .rel.ARM.exidx.pr1 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .pr1 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0 -@ CHECK: ] -@ CHECK: } +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.pr1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .pr1 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0 +@ RELOC: ] +@ RELOC: } .section .pr1.nontrivial @@ -122,14 +124,14 @@ pr1_nontrivial: @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .rel.ARM.exidx.pr1.nontrivial -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .pr1.nontrivial 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0 -@ CHECK: ] -@ CHECK: } +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.pr1.nontrivial +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .pr1.nontrivial 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0 +@ RELOC: ] +@ RELOC: } .section .pr2 @@ -156,14 +158,14 @@ pr2: @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .rel.ARM.exidx.pr2 -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .pr2 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0 -@ CHECK: ] -@ CHECK: } +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.pr2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .pr2 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0 +@ RELOC: ] +@ RELOC: } .section .pr2.nontrivial .type pr2_nontrivial,%function @@ -191,12 +193,11 @@ pr2_nontrivial: @ CHECK: ) @ CHECK: } -@ CHECK: Section { -@ CHECK: Name: .rel.ARM.exidx.pr2.nontrivial -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .pr2.nontrivial 0x0 -@ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0 -@ CHECK: ] -@ CHECK: } - +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.pr2.nontrivial +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .pr2.nontrivial 0x0 +@ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0 +@ RELOC: ] +@ RELOC: } diff --git a/test/MC/ARM/eh-directive-section-multiple-func.s b/test/MC/ARM/eh-directive-section-multiple-func.s index 9f632b8..e7198a4 100644 --- a/test/MC/ARM/eh-directive-section-multiple-func.s +++ b/test/MC/ARM/eh-directive-section-multiple-func.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s +@ RUN: | llvm-readobj -s -sd -sr -t > %t +@ RUN: FileCheck %s < %t +@ RUN: FileCheck --check-prefix=RELOC %s < %t @ Check whether the section is switched back properly. @@ -69,10 +71,14 @@ func2: @ CHECK: 0000: 00000000 B0B0B000 00000000 B0B0B000 |................| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.extab.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ RELOC: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- @@ -89,18 +95,21 @@ func2: @ CHECK: 0000: 00000000 00000000 04000000 08000000 |................| @ CHECK: ) @ CHECK: } -@ CHECK: ] @------------------------------------------------------------------------------- @ The first word of each entry should be relocated to .TEST1 section. @ The second word of each entry should be relocated to @ .ARM.extab.TESET1 section. @------------------------------------------------------------------------------- -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 -@ CHECK: 0x8 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ RELOC: 0x8 R_ARM_PREL31 .TEST1 0x0 +@ RELOC: 0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- diff --git a/test/MC/ARM/eh-directive-section.s b/test/MC/ARM/eh-directive-section.s index 7c1f32e..671d106 100644 --- a/test/MC/ARM/eh-directive-section.s +++ b/test/MC/ARM/eh-directive-section.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s +@ RUN: | llvm-readobj -s -sd -sr -t > %t +@ RUN: FileCheck %s < %t +@ RUN: FileCheck --check-prefix=RELOC %s < %t @ Check the combination of .section, .fnstart, and .fnend directives. @@ -64,9 +66,13 @@ func2: @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.extab.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- @@ -89,10 +95,14 @@ func2: @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidx.TEST1 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- @@ -115,9 +125,13 @@ func2: @ CHECK: 0000: 00000000 B0B0B000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.extabTEST2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0 +@ RELOC: ] +@ RELOC: } @------------------------------------------------------------------------------- @@ -140,11 +154,14 @@ func2: @ CHECK: 0000: 00000000 00000000 |........| @ CHECK: ) @ CHECK: } -@ CHECK: ] -@ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 TEST2 0x0 -@ CHECK: 0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0 -@ CHECK: ] + +@ RELOC: Section { +@ RELOC: Name: .rel.ARM.exidxTEST2 +@ RELOC: Relocations [ +@ RELOC: 0x0 R_ARM_PREL31 TEST2 0x0 +@ RELOC: 0x4 R_ARM_PREL31 .ARM.extabTEST2 0x0 +@ RELOC: ] +@ RELOC: } diff --git a/test/MC/ARM/eh-link.s b/test/MC/ARM/eh-link.s new file mode 100644 index 0000000..0c44c0e --- /dev/null +++ b/test/MC/ARM/eh-link.s @@ -0,0 +1,90 @@ +@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \ +@ RUN: | llvm-readobj -s | FileCheck %s + +@ Test that the ARM_EXIDX sections point (Link) to the corresponding text +@ sections. + +@ FIXME: The section numbers are not important. If llvm-readobj printed the +@ name first we could use a FileCheck variable. + +@ CHECK: Section { +@ CHECK: Index: 6 +@ CHECK-NEXT: Name: .text +@ CHECK-NEXT: Type: SHT_PROGBITS +@ CHECK-NEXT: Flags [ +@ CHECK-NEXT: SHF_ALLOC +@ CHECK-NEXT: SHF_EXECINSTR +@ CHECK-NEXT: SHF_GROUP +@ CHECK-NEXT: ] +@ CHECK-NEXT: Address: 0x0 +@ CHECK-NEXT: Offset: 0x54 +@ CHECK-NEXT: Size: 4 +@ CHECK-NEXT: Link: 0 +@ CHECK-NEXT: Info: 0 +@ CHECK-NEXT: AddressAlignment: 1 +@ CHECK-NEXT: EntrySize: 0 +@ CHECK-NEXT: } +@ CHECK-NEXT: Section { +@ CHECK-NEXT: Index: 7 +@ CHECK-NEXT: Name: .ARM.exidx +@ CHECK-NEXT: Type: SHT_ARM_EXIDX +@ CHECK-NEXT: Flags [ +@ CHECK-NEXT: SHF_ALLOC +@ CHECK-NEXT: SHF_GROUP +@ CHECK-NEXT: SHF_LINK_ORDER +@ CHECK-NEXT: ] +@ CHECK-NEXT: Address: 0x0 +@ CHECK-NEXT: Offset: 0x58 +@ CHECK-NEXT: Size: 8 +@ CHECK-NEXT: Link: 6 +@ CHECK-NEXT: Info: 0 +@ CHECK-NEXT: AddressAlignment: 4 +@ CHECK-NEXT: EntrySize: 0 +@ CHECK-NEXT: } + +@ CHECK: Section { +@ CHECK: Index: 9 +@ CHECK-NEXT: Name: .text +@ CHECK-NEXT: Type: SHT_PROGBITS +@ CHECK-NEXT: Flags [ +@ CHECK-NEXT: SHF_ALLOC +@ CHECK-NEXT: SHF_EXECINSTR +@ CHECK-NEXT: SHF_GROUP +@ CHECK-NEXT: ] +@ CHECK-NEXT: Address: 0x0 +@ CHECK-NEXT: Offset: +@ CHECK-NEXT: Size: 4 +@ CHECK-NEXT: Link: 0 +@ CHECK-NEXT: Info: 0 +@ CHECK-NEXT: AddressAlignment: 1 +@ CHECK-NEXT: EntrySize: 0 +@ CHECK-NEXT: } +@ CHECK-NEXT: Section { +@ CHECK-NEXT: Index: 10 +@ CHECK-NEXT: Name: .ARM.exidx +@ CHECK-NEXT: Type: SHT_ARM_EXIDX +@ CHECK-NEXT: Flags [ +@ CHECK-NEXT: SHF_ALLOC +@ CHECK-NEXT: SHF_GROUP +@ CHECK-NEXT: SHF_LINK_ORDER +@ CHECK-NEXT: ] +@ CHECK-NEXT: Address: 0x0 +@ CHECK-NEXT: Offset: +@ CHECK-NEXT: Size: 8 +@ CHECK-NEXT: Link: 9 +@ CHECK-NEXT: Info: 0 +@ CHECK-NEXT: AddressAlignment: 4 +@ CHECK-NEXT: EntrySize: 0 +@ CHECK-NEXT: } + + .section .text,"axG",%progbits,f,comdat +f: + .fnstart + mov pc, lr + .fnend + + .section .text,"axG",%progbits,g,comdat +g: + .fnstart + mov pc, lr + .fnend diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s index 0080db4..1ff5da5 100644 --- a/test/MC/ARM/elf-movt.s +++ b/test/MC/ARM/elf-movt.s @@ -35,14 +35,14 @@ barf: @ @barf @ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3 @ OBJ-NEXT: ) @ OBJ-NEXT: } -@ OBJ-NEXT: Section { -@ OBJ-NEXT: Index: 2 -@ OBJ-NEXT: Name: .rel.text (1) +@ OBJ: Section { +@ OBJ: Index: +@ OBJ: Name: .rel.text @ OBJ-NEXT: Type: SHT_REL (0x9) @ OBJ-NEXT: Flags [ (0x0) @ OBJ-NEXT: ] @ OBJ-NEXT: Address: 0x0 -@ OBJ-NEXT: Offset: 0x22C +@ OBJ-NEXT: Offset: @ OBJ-NEXT: Size: 16 @ OBJ-NEXT: Link: 6 @ OBJ-NEXT: Info: 1 diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index 28be85b..7f3cc18 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -61,7 +61,7 @@ bb3: ; preds = %bb, %entry declare void @exit(i32) noreturn nounwind ; OBJ: Relocations [ -; OBJ: Section (2) .rel.text { +; OBJ: Section {{.*}} .rel.text { ; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals ; OBJ: } ; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll index 8b4feba..0ffb623 100644 --- a/test/MC/ARM/elf-reloc-02.ll +++ b/test/MC/ARM/elf-reloc-02.ll @@ -29,10 +29,10 @@ declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind define i32 @main() nounwind { entry: - %0 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind - %1 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind - %2 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind - %3 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind + %0 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind + %1 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind + %2 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind + %3 = tail call i32 (...) @write(i32 1, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind tail call void @exit(i32 55) noreturn nounwind unreachable } @@ -42,7 +42,7 @@ declare i32 @write(...) declare void @exit(i32) noreturn nounwind ;; OBJ: Relocations [ -;; OBJ: Section (2) .rel.text { +;; OBJ: Section {{.*}} .rel.text { ;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str ;; OBJ: } ;; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll index a0fdc3e..4beb91f 100644 --- a/test/MC/ARM/elf-reloc-03.ll +++ b/test/MC/ARM/elf-reloc-03.ll @@ -81,7 +81,7 @@ entry: %0 = load i32, i32* @startval, align 4 %1 = getelementptr inbounds [10 x i32 (...)*], [10 x i32 (...)*]* @vtable, i32 0, i32 %0 %2 = load i32 (...)*, i32 (...)** %1, align 4 - %3 = tail call i32 (...)* %2() nounwind + %3 = tail call i32 (...) %2() nounwind tail call void @exit(i32 %3) noreturn nounwind unreachable } @@ -89,7 +89,7 @@ entry: declare void @exit(i32) noreturn nounwind ;; OBJ: Relocations [ -;; OBJ: Section (2) .rel.text { +;; OBJ: Section {{.*}} .rel.text { ;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable ;; OBJ: } ;; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s index a0402bd..c4818b8 100644 --- a/test/MC/ARM/elf-reloc-condcall.s +++ b/test/MC/ARM/elf-reloc-condcall.s @@ -8,7 +8,7 @@ b some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (2) .rel.text { +// OBJ-NEXT: Section {{.*}} .rel.text { // OBJ-NEXT: 0x0 R_ARM_JUMP24 some_label 0x0 // OBJ-NEXT: 0x4 R_ARM_CALL some_label 0x0 // OBJ-NEXT: 0x8 R_ARM_CALL some_label 0x0 diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll index f502739..f35971a 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.ll +++ b/test/MC/ARM/elf-thumbfunc-reloc.ll @@ -29,10 +29,10 @@ entry: ; CHECK: ] ; CHECK: Relocations [ -; CHECK-NEXT: Section (2) .rel.text { +; CHECK-NEXT: Section {{.*}} .rel.text { ; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0 ; CHECK-NEXT: } -; CHECK-NEXT: Section (7) .rel.ARM.exidx { +; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx { ; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0 ; CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0 ; CHECK-NEXT: } diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s index ea7d507..dd380c3 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.s +++ b/test/MC/ARM/elf-thumbfunc-reloc.s @@ -22,7 +22,7 @@ ptr: @@ make sure an R_ARM_THM_CALL relocation is generated for the call to g @CHECK: Relocations [ -@CHECK-NEXT: Section (2) .rel.text { +@CHECK-NEXT: Section {{.*}} .rel.text { @CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0 @CHECK-NEXT: } diff --git a/test/MC/ARM/thumb1-relax-adr.s b/test/MC/ARM/thumb1-relax-adr.s new file mode 100644 index 0000000..80b93ec --- /dev/null +++ b/test/MC/ARM/thumb1-relax-adr.s @@ -0,0 +1,9 @@ +@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s + + .global func1 +_func1: + adr r0, _func2 +@ CHECK-ERROR: unsupported relocation on symbol + diff --git a/test/MC/ARM/thumb1-relax-bcc.s b/test/MC/ARM/thumb1-relax-bcc.s new file mode 100644 index 0000000..02fde2e --- /dev/null +++ b/test/MC/ARM/thumb1-relax-bcc.s @@ -0,0 +1,12 @@ +@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s +@ RUN: llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s + + .global func1 +_func1: + bne _func2 +@ CHECK-ERROR: unsupported relocation on symbol + +@ CHECK-ELF: 7f f4 fe af bne.w #-4 +@ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2 diff --git a/test/MC/ARM/thumb1-relax-br.s b/test/MC/ARM/thumb1-relax-br.s new file mode 100644 index 0000000..92a8275 --- /dev/null +++ b/test/MC/ARM/thumb1-relax-br.s @@ -0,0 +1,19 @@ +@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: llvm-mc -triple thumbv7m-none-macho -filetype=obj -o %t %s +@ RUN: llvm-objdump -d -r -triple thumbv7m-none-macho %t | FileCheck --check-prefix=CHECK-MACHO %s +@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o %t %s +@ RUN: llvm-objdump -d -r -triple thumbv7m-none-eabi %t | FileCheck --check-prefix=CHECK-ELF %s + + .global func1 +_func1: + @ There is no MachO relocation for Thumb1's unconditional branch, so + @ this is unrepresentable. FIXME: I think ELF could represent this. + b _func2 + +@ CHECK-ERROR: unsupported relocation on symbol + +@ CHECK-MACHO: ff f7 fe bf b.w #-4 +@ CHECK-MACHO-NEXT: ARM_THUMB_RELOC_BR22 + +@ CHECK-ELF: ff f7 fe bf b.w #-4 +@ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2 diff --git a/test/MC/ARM/thumb1-relax-ldrlit.s b/test/MC/ARM/thumb1-relax-ldrlit.s new file mode 100644 index 0000000..96c5aa0 --- /dev/null +++ b/test/MC/ARM/thumb1-relax-ldrlit.s @@ -0,0 +1,9 @@ +@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s + + .global func1 +_func1: + ldr r0, _func2 +@ CHECK-ERROR: unsupported relocation on symbol + diff --git a/test/MC/ARM/thumb2-bxj-v8.s b/test/MC/ARM/thumb2-bxj-v8.s new file mode 100644 index 0000000..4420b6f --- /dev/null +++ b/test/MC/ARM/thumb2-bxj-v8.s @@ -0,0 +1,11 @@ +@ RUN: not llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +@ RUN: not llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +@ RUN: not llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=ARM_MODE +@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s + +bxj r13 + +@ CHECK: bxj sp @ encoding: [0xcd,0xf3,0x00,0x8f] +@ UNDEF: error: r13 (SP) is an unpredictable operand to BXJ +@ ARM_MODE: error: instruction requires: arm-mode diff --git a/test/MC/ARM/thumb2-bxj.s b/test/MC/ARM/thumb2-bxj.s index e60d1a4..7687939 100644 --- a/test/MC/ARM/thumb2-bxj.s +++ b/test/MC/ARM/thumb2-bxj.s @@ -1,8 +1,8 @@ @ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s @ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF -@ RUN: not llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF bxj r2 diff --git a/test/MC/Disassembler/AArch64/arm64-advsimd.txt b/test/MC/Disassembler/AArch64/arm64-advsimd.txt index cceee67..ef125c8 100644 --- a/test/MC/Disassembler/AArch64/arm64-advsimd.txt +++ b/test/MC/Disassembler/AArch64/arm64-advsimd.txt @@ -169,6 +169,43 @@ # CHECK: ins.h v2[7], v15[3] # CHECK: ins.b v2[10], v15[5] +# INS/DUP (non-standard) +0x60 0x0c 0x08 0x4e +0x60 0x0c 0x0c 0x4e +0x60 0x0c 0x0c 0x0e +0x60 0x0c 0x0e 0x4e +0x60 0x0c 0x0e 0x0e +0x60 0x0c 0x0f 0x4e +0x60 0x0c 0x0f 0x0e + +# CHECK: dup.2d v0, x3 +# CHECK: dup.4s v0, w3 +# CHECK: dup.2s v0, w3 +# CHECK: dup.8h v0, w3 +# CHECK: dup.4h v0, w3 +# CHECK: dup.16b v0, w3 +# CHECK: dup.8b v0, w3 + +0xe2 0x75 0x18 0x6e +0xe2 0x35 0x0c 0x6e +0xe2 0x15 0x06 0x6e +0xe2 0x0d 0x03 0x6e + +0xe2 0x05 0x18 0x6e +0xe2 0x55 0x1c 0x6e +0xe2 0x35 0x1e 0x6e +0xe2 0x2d 0x15 0x6e + +# CHECK: ins.d v2[1], v15[1] +# CHECK: ins.s v2[1], v15[1] +# CHECK: ins.h v2[1], v15[1] +# CHECK: ins.b v2[1], v15[1] + +# CHECK: ins.d v2[1], v15[0] +# CHECK: ins.s v2[3], v15[2] +# CHECK: ins.h v2[7], v15[3] +# CHECK: ins.b v2[10], v15[5] + 0x00 0x1c 0x20 0x0e 0x00 0x1c 0x20 0x4e diff --git a/test/MC/Disassembler/AArch64/armv8.1a-lor.txt b/test/MC/Disassembler/AArch64/armv8.1a-lor.txt new file mode 100644 index 0000000..5f8e725 --- /dev/null +++ b/test/MC/Disassembler/AArch64/armv8.1a-lor.txt @@ -0,0 +1,28 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s + +0x20,0x7c,0xdf,0x08 +0x20,0x7c,0xdf,0x48 +0x20,0x7c,0xdf,0x88 +0x20,0x7c,0xdf,0xc8 +0x20,0x7c,0x9f,0x08 +0x20,0x7c,0x9f,0x48 +0x20,0x7c,0x9f,0x88 +0x20,0x7c,0x9f,0xc8 +# CHECK: ldlarb w0, [x1] +# CHECK: ldlarh w0, [x1] +# CHECK: ldlar w0, [x1] +# CHECK: ldlar x0, [x1] +# CHECK: stllrb w0, [x1] +# CHECK: stllrh w0, [x1] +# CHECK: stllr w0, [x1] +# CHECK: stllr x0, [x1] +0x00,0xa4,0x18,0xd5 +0x20,0xa4,0x18,0xd5 +0x40,0xa4,0x18,0xd5 +0x60,0xa4,0x18,0xd5 +0xe0,0xa4,0x38,0xd5 +# CHECK: msr LORSA_EL1, x0 +# CHECK: msr LOREA_EL1, x0 +# CHECK: msr LORN_EL1, x0 +# CHECK: msr LORC_EL1, x0 +# CHECK: mrs x0, LORID_EL1 diff --git a/test/MC/Disassembler/AArch64/armv8.1a-pan.txt b/test/MC/Disassembler/AArch64/armv8.1a-pan.txt new file mode 100644 index 0000000..2af5c2a --- /dev/null +++ b/test/MC/Disassembler/AArch64/armv8.1a-pan.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s + +0x9f,0x40,0x00,0xd5 +0x9f,0x41,0x00,0xd5 +0x65,0x42,0x18,0xd5 +0x6d,0x42,0x38,0xd5 +# CHECK: msr PAN, #0 +# CHECK: msr PAN, #1 +# CHECK: msr PAN, x5 +# CHECK: mrs x13, PAN diff --git a/test/MC/Disassembler/AArch64/armv8.1a-rdma.txt b/test/MC/Disassembler/AArch64/armv8.1a-rdma.txt new file mode 100644 index 0000000..5e1272f --- /dev/null +++ b/test/MC/Disassembler/AArch64/armv8.1a-rdma.txt @@ -0,0 +1,129 @@ +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s + +[0x20,0x84,0x02,0x2e] # sqrdmlah v0.8b, v1.8b, v2.8b +[0x20,0x8c,0x02,0x2e] # sqrdmlsh v0.8b, v1.8b, v2.8b +[0x20,0x84,0xc2,0x2e] # sqrdmlah v0.1d, v1.1d, v2.1d +[0x20,0x8c,0xc2,0x2e] # sqrdmlsh v0.1d, v1.1d, v2.1d +[0x20,0x84,0x02,0x6e] # sqrdmlah v0.16b, v1.16b, v2.16b +[0x20,0x8c,0x02,0x6e] # sqrdmlsh v0.16b, v1.16b, v2.16b +[0x20,0x84,0xc2,0x6e] # sqrdmlah v0.2d, v1.2d, v2.2d +[0x20,0x8c,0xc2,0x6e] # sqrdmlsh v0.2d, v1.2d, v2.2d +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x84,0x02,0x2e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x8c,0x02,0x2e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x84,0xc2,0x2e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x8c,0xc2,0x2e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x84,0x02,0x6e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x8c,0x02,0x6e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x84,0xc2,0x6e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x8c,0xc2,0x6e] + +[0x20,0x84,0x02,0x7e] # sqrdmlah b0, b1, b2 +[0x20,0x8c,0x02,0x7e] # sqrdmlsh b0, b1, b2 +[0x20,0x84,0xc2,0x7e] # sqrdmlah d0, d1, d2 +[0x20,0x8c,0xc2,0x7e] # sqrdmlsh d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x84,0x02,0x7e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x8c,0x02,0x7e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x84,0xc2,0x7e] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0x8c,0xc2,0x7e] + +[0x20,0xd0,0x32,0x2f] # sqrdmlah v0.8b, v1.8b, v2.b[3] +[0x20,0xf0,0x32,0x2f] # sqrdmlsh v0.8b, v1.8b, v2.b[3] +[0x20,0xd0,0xe2,0x2f] # sqrdmlah v0.1d, v1.1d, v2.d[1] +[0x20,0xf0,0xe2,0x2f] # sqrdmlsh v0.1d, v1.1d, v2.d[1] +[0x20,0xd0,0x32,0x6f] # sqrdmlah v0.16b, v1.16b, v2.b[3] +[0x20,0xf0,0x32,0x6f] # sqrdmlsh v0.16b, v1.16b, v2.b[3] +[0x20,0xd8,0xe2,0x6f] # sqrdmlah v0.2d, v1.2d, v2.d[3] +[0x20,0xf8,0xe2,0x6f] # sqrdmlsh v0.2d, v1.2d, v2.d[3] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xd0,0x32,0x2f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xf0,0x32,0x2f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xd0,0xe2,0x2f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xf0,0xe2,0x2f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xd0,0x32,0x6f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xf0,0x32,0x6f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xd8,0xe2,0x6f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xf8,0xe2,0x6f] + +[0x20,0xd0,0x32,0x7f] # sqrdmlah b0, b1, v2.b[3] +[0x20,0xf0,0x32,0x7f] # sqrdmlsh b0, b1, v2.b[3] +[0x20,0xd8,0xe2,0x7f] # sqrdmlah d0, d1, v2.d[3] +[0x20,0xf8,0xe2,0x7f] # sqrdmlsh d0, d1, v2.d[3] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xd0,0x32,0x7f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xf0,0x32,0x7f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xd8,0xe2,0x7f] +# CHECK: warning: invalid instruction encoding +# CHECK: [0x20,0xf8,0xe2,0x7f] + +[0x20,0x84,0x42,0x2e] +[0x20,0x8c,0x42,0x2e] +[0x20,0x84,0x82,0x2e] +[0x20,0x8c,0x82,0x2e] +[0x20,0x84,0x42,0x6e] +[0x20,0x8c,0x42,0x6e] +[0x20,0x84,0x82,0x6e] +[0x20,0x8c,0x82,0x6e] +# CHECK: sqrdmlah v0.4h, v1.4h, v2.4h +# CHECK: sqrdmlsh v0.4h, v1.4h, v2.4h +# CHECK: sqrdmlah v0.2s, v1.2s, v2.2s +# CHECK: sqrdmlsh v0.2s, v1.2s, v2.2s +# CHECK: sqrdmlah v0.8h, v1.8h, v2.8h +# CHECK: sqrdmlsh v0.8h, v1.8h, v2.8h +# CHECK: sqrdmlah v0.4s, v1.4s, v2.4s +# CHECK: sqrdmlsh v0.4s, v1.4s, v2.4s + +[0x20,0x84,0x42,0x7e] +[0x20,0x8c,0x42,0x7e] +[0x20,0x84,0x82,0x7e] +[0x20,0x8c,0x82,0x7e] +# CHECK: sqrdmlah h0, h1, h2 +# CHECK: sqrdmlsh h0, h1, h2 +# CHECK: sqrdmlah s0, s1, s2 +# CHECK: sqrdmlsh s0, s1, s2 + +0x20,0xd0,0x72,0x2f +0x20,0xf0,0x72,0x2f +0x20,0xd0,0xa2,0x2f +0x20,0xf0,0xa2,0x2f +0x20,0xd0,0x72,0x6f +0x20,0xf0,0x72,0x6f +0x20,0xd8,0xa2,0x6f +0x20,0xf8,0xa2,0x6f +# CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3] +# CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3] +# CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1] +# CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1] +# CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3] +# CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3] +# CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3] +# CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3] + +0x20,0xd0,0x72,0x7f +0x20,0xf0,0x72,0x7f +0x20,0xd8,0xa2,0x7f +0x20,0xf8,0xa2,0x7f +# CHECK: sqrdmlah h0, h1, v2.h[3] +# CHECK: sqrdmlsh h0, h1, v2.h[3] +# CHECK: sqrdmlah s0, s1, v2.s[3] +# CHECK: sqrdmlsh s0, s1, v2.s[3] diff --git a/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt b/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt new file mode 100644 index 0000000..e4bf59c --- /dev/null +++ b/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt @@ -0,0 +1,56 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s + +0x20,0x20,0x1c,0xd5 +0x20,0xd0,0x1c,0xd5 +0x00,0xe3,0x1c,0xd5 +0x40,0xe3,0x1c,0xd5 +0x20,0xe3,0x1c,0xd5 +0x00,0x10,0x1d,0xd5 +0x40,0x10,0x1d,0xd5 +0x00,0x20,0x1d,0xd5 +0x20,0x20,0x1d,0xd5 +0x40,0x20,0x1d,0xd5 +0x00,0x51,0x1d,0xd5 +0x20,0x51,0x1d,0xd5 +0x00,0x52,0x1d,0xd5 +0x00,0x60,0x1d,0xd5 +0x00,0xa2,0x1d,0xd5 +0x00,0xa3,0x1d,0xd5 +0x00,0xc0,0x1d,0xd5 +0x20,0xd0,0x1d,0xd5 +0x00,0xe1,0x1d,0xd5 +0x00,0xe2,0x1d,0xd5 +0x20,0xe2,0x1d,0xd5 +0x40,0xe2,0x1d,0xd5 +0x00,0xe3,0x1d,0xd5 +0x20,0xe3,0x1d,0xd5 +0x40,0xe3,0x1d,0xd5 +0x00,0x40,0x1d,0xd5 +0x20,0x40,0x1d,0xd5 +# CHECK: msr TTBR1_EL2, x0 +# CHECK: msr CONTEXTIDR_EL2, x0 +# CHECK: msr CNTHV_TVAL_EL2, x0 +# CHECK: msr CNTHV_CVAL_EL2, x0 +# CHECK: msr CNTHV_CTL_EL2, x0 +# CHECK: msr SCTLR_EL12, x0 +# CHECK: msr CPACR_EL12, x0 +# CHECK: msr TTBR0_EL12, x0 +# CHECK: msr TTBR1_EL12, x0 +# CHECK: msr TCR_EL12, x0 +# CHECK: msr AFSR0_EL12, x0 +# CHECK: msr AFSR1_EL12, x0 +# CHECK: msr ESR_EL12, x0 +# CHECK: msr FAR_EL12, x0 +# CHECK: msr MAIR_EL12, x0 +# CHECK: msr AMAIR_EL12, x0 +# CHECK: msr VBAR_EL12, x0 +# CHECK: msr CONTEXTIDR_EL12, x0 +# CHECK: msr CNTKCTL_EL12, x0 +# CHECK: msr CNTP_TVAL_EL02, x0 +# CHECK: msr CNTP_CTL_EL02, x0 +# CHECK: msr CNTP_CVAL_EL02, x0 +# CHECK: msr CNTV_TVAL_EL02, x0 +# CHECK: msr CNTV_CTL_EL02, x0 +# CHECK: msr CNTV_CVAL_EL02, x0 +# CHECK: msr SPSR_EL12, x0 +# CHECK: msr ELR_EL12, x0 diff --git a/test/MC/Disassembler/ARM/armv8.1a.txt b/test/MC/Disassembler/ARM/armv8.1a.txt index de0c89e..929643b 100644 --- a/test/MC/Disassembler/ARM/armv8.1a.txt +++ b/test/MC/Disassembler/ARM/armv8.1a.txt @@ -34,3 +34,19 @@ # CHECK-V8: [0x42,0x0f,0x92,0xf3] # CHECK-V8: warning: invalid instruction encoding # CHECK-V8: [0x42,0x0f,0xa1,0xf2] + +# The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN +# uses the encoding for the invalid NV predicate operand. This test checks that +# the disassembler is correctly disambiguating and decoding these instructions. + +[0x00 0x00 0x10 0xf1] +# CHECK: setpan #0 + +[0x00 0x02 0x10 0xf1] +# CHECK: setpan #1 + +[0x00 0x00 0x10 0xe1] +# CHECK: tst r0, r0 + +[0x00 0x02 0x10 0xe1] +# CHECK: tst r0, r0, lsl #4 diff --git a/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/test/MC/Disassembler/ARM/thumb-v8.1a.txt index 10fea46..3de8c27 100644 --- a/test/MC/Disassembler/ARM/thumb-v8.1a.txt +++ b/test/MC/Disassembler/ARM/thumb-v8.1a.txt @@ -96,3 +96,15 @@ # CHECK-V8: warning: invalid instruction encoding # CHECK-V8: [0xa2,0xff,0x42,0x0f] # CHECK-V8: ^ + +[0x10,0xb6] +# CHECK-V81a: setpan #0 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x10,0xb6] +# CHECK-V8: ^ + +[0x18,0xb6] +# CHECK-V81a: setpan #1 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x18,0xb6] +# CHECK-V8: ^ diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt index e99d49b..f9cdb51 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -328,6 +328,18 @@ # CHECK: divwu. 2, 3, 4 0x7c 0x43 0x23 0x97 +# CHECK: divwe 2, 3, 4 +0x7c 0x43 0x23 0x56 + +# CHECK: divwe. 2, 3, 4 +0x7c 0x43 0x23 0x57 + +# CHECK: divweu 2, 3, 4 +0x7c 0x43 0x23 0x16 + +# CHECK: divweu. 2, 3, 4 +0x7c 0x43 0x23 0x17 + # CHECK: mulld 2, 3, 4 0x7c 0x43 0x21 0xd2 @@ -358,6 +370,18 @@ # CHECK: divdu. 2, 3, 4 0x7c 0x43 0x23 0x93 +# CHECK: divde 2, 3, 4 +0x7c 0x43 0x23 0x52 + +# CHECK: divde. 2, 3, 4 +0x7c 0x43 0x23 0x53 + +# CHECK: divdeu 2, 3, 4 +0x7c 0x43 0x23 0x12 + +# CHECK: divdeu. 2, 3, 4 +0x7c 0x43 0x23 0x13 + # CHECK: cmpdi 2, 3, 128 0x2d 0x23 0x00 0x80 @@ -499,6 +523,9 @@ # CHECK: popcntd 2, 3 0x7c 0x62 0x03 0xf4 +# CHECK: bpermd 2, 3, 4 +0x7c 0x62 0x21 0xf8 + # CHECK: cmpb 7, 21, 4 0x7e 0xa7 0x23 0xf8 diff --git a/test/MC/Disassembler/PowerPC/vsx.txt b/test/MC/Disassembler/PowerPC/vsx.txt index 5e65482..1b91b34 100644 --- a/test/MC/Disassembler/PowerPC/vsx.txt +++ b/test/MC/Disassembler/PowerPC/vsx.txt @@ -459,3 +459,17 @@ # CHECK: xxpermdi 7, 63, 63, 2 0xf0 0xff 0xfa 0x56 +# CHECK: mfvsrd 3, 0 +0x7c 0x03 0x00 0x66 + +# CHECK: mfvsrwz 5, 0 +0x7c 0x05 0x00 0xe6 + +# CHECK: mtvsrd 0, 3 +0x7c 0x03 0x01 0x66 + +# CHECK: mtvsrwa 0, 3 +0x7c 0x03 0x01 0xa6 + +# CHECK: mtvsrwz 0, 3 +0x7c 0x03 0x01 0xe6 diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 54a3c5b..9d3f2b0 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -2503,6 +2503,15 @@ # CHECK: ear %r15, %a15 0xb2 0x4f 0x00 0xff +# CHECK: etnd %r0 +0xb2 0xec 0x00 0x00 + +# CHECK: etnd %r15 +0xb2 0xec 0x00 0xf0 + +# CHECK: etnd %r7 +0xb2 0xec 0x00 0x70 + # CHECK: fidbr %f0, 0, %f0 0xb3 0x5f 0x00 0x00 @@ -6034,6 +6043,36 @@ # CHECK: ny %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x54 +# CHECK: ntstg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x25 + +# CHECK: ntstg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x25 + +# CHECK: ntstg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x25 + +# CHECK: ntstg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x25 + +# CHECK: ntstg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x25 + # CHECK: oc 0(1), 0 0xd6 0x00 0x00 0x00 0x00 0x00 @@ -6334,6 +6373,33 @@ # CHECK: pfd 15, 0 0xe3 0xf0 0x00 0x00 0x00 0x36 +# CHECK: popcnt %r0, %r0 +0xb9 0xe1 0x00 0x00 + +# CHECK: popcnt %r0, %r15 +0xb9 0xe1 0x00 0x0f + +# CHECK: popcnt %r15, %r0 +0xb9 0xe1 0x00 0xf0 + +# CHECK: popcnt %r7, %r8 +0xb9 0xe1 0x00 0x78 + +# CHECK: ppa %r0, %r0, 0 +0xb2 0xe8 0x00 0x00 + +# CHECK: ppa %r0, %r0, 15 +0xb2 0xe8 0xf0 0x00 + +# CHECK: ppa %r0, %r15, 0 +0xb2 0xe8 0x00 0x0f + +# CHECK: ppa %r4, %r6, 7 +0xb2 0xe8 0x70 0x46 + +# CHECK: ppa %r15, %r0, 0 +0xb2 0xe8 0x00 0xf0 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -6355,6 +6421,27 @@ # CHECK: risbg %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x55 +# CHECK: risbgn %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x59 + +# CHECK: risbgn %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x59 + +# CHECK: risbgn %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x59 + +# CHECK: risbgn %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x59 + +# CHECK: risbgn %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x59 + +# CHECK: risbgn %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x59 + +# CHECK: risbgn %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x59 + # CHECK: risbhg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x5d @@ -8029,6 +8116,93 @@ # CHECK: sy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5b +# CHECK: tabort 0 +0xb2 0xfc 0x00 0x00 + +# CHECK: tabort 0(%r1) +0xb2 0xfc 0x10 0x00 + +# CHECK: tabort 0(%r15) +0xb2 0xfc 0xf0 0x00 + +# CHECK: tabort 4095 +0xb2 0xfc 0x0f 0xff + +# CHECK: tabort 4095(%r1) +0xb2 0xfc 0x1f 0xff + +# CHECK: tabort 4095(%r15) +0xb2 0xfc 0xff 0xff + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 4095, 0 +0xe5 0x60 0x0f 0xff 0x00 0x00 + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 0, 1 +0xe5 0x60 0x00 0x00 0x00 0x01 + +# CHECK: tbegin 0, 32767 +0xe5 0x60 0x00 0x00 0x7f 0xff + +# CHECK: tbegin 0, 32768 +0xe5 0x60 0x00 0x00 0x80 0x00 + +# CHECK: tbegin 0, 65535 +0xe5 0x60 0x00 0x00 0xff 0xff + +# CHECK: tbegin 0(%r1), 42 +0xe5 0x60 0x10 0x00 0x00 0x2a + +# CHECK: tbegin 0(%r15), 42 +0xe5 0x60 0xf0 0x00 0x00 0x2a + +# CHECK: tbegin 4095(%r1), 42 +0xe5 0x60 0x1f 0xff 0x00 0x2a + +# CHECK: tbegin 4095(%r15), 42 +0xe5 0x60 0xff 0xff 0x00 0x2a + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 4095, 0 +0xe5 0x61 0x0f 0xff 0x00 0x00 + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 0, 1 +0xe5 0x61 0x00 0x00 0x00 0x01 + +# CHECK: tbeginc 0, 32767 +0xe5 0x61 0x00 0x00 0x7f 0xff + +# CHECK: tbeginc 0, 32768 +0xe5 0x61 0x00 0x00 0x80 0x00 + +# CHECK: tbeginc 0, 65535 +0xe5 0x61 0x00 0x00 0xff 0xff + +# CHECK: tbeginc 0(%r1), 42 +0xe5 0x61 0x10 0x00 0x00 0x2a + +# CHECK: tbeginc 0(%r15), 42 +0xe5 0x61 0xf0 0x00 0x00 0x2a + +# CHECK: tbeginc 4095(%r1), 42 +0xe5 0x61 0x1f 0xff 0x00 0x2a + +# CHECK: tbeginc 4095(%r15), 42 +0xe5 0x61 0xff 0xff 0x00 0x2a + +# CHECK: tend +0xb2 0xf8 0x00 0x00 + # CHECK: tm 0, 0 0x91 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/X86/x86-16.txt b/test/MC/Disassembler/X86/x86-16.txt index 93974d4..c6844cd 100644 --- a/test/MC/Disassembler/X86/x86-16.txt +++ b/test/MC/Disassembler/X86/x86-16.txt @@ -30,7 +30,7 @@ # CHECK: movl %eax, -16(%ebp) 0x67 0x66 0x89 0x45 0xf0 -# CHECK: testb %bl, %cl +# CHECK: testb %cl, %bl 0x84 0xcb # CHECK: cmpl %eax, %ebx diff --git a/test/MC/ELF/alias.s b/test/MC/ELF/alias.s index 78df737..0ab6dd4 100644 --- a/test/MC/ELF/alias.s +++ b/test/MC/ELF/alias.s @@ -24,6 +24,15 @@ bar5 = bar4 bar6 = bar5 bar6: +// Test that indirect local aliases do not appear as symbols. +.data +.Llocal: + +.text +leaq .Llocal1(%rip), %rdi +.Llocal1 = .Llocal2 +.Llocal2 = .Llocal + // CHECK: Symbols [ // CHECK-NEXT: Symbol { // CHECK-NEXT: Name: (0) diff --git a/test/MC/ELF/basic-elf-32.s b/test/MC/ELF/basic-elf-32.s index e12fc52..16266af 100644 --- a/test/MC/ELF/basic-elf-32.s +++ b/test/MC/ELF/basic-elf-32.s @@ -45,7 +45,7 @@ main: # @main // CHECK: Name: .rel.text // CHECK: Relocations [ -// CHECK: Section (2) .rel.text { +// CHECK: Section {{.*}} .rel.text { // CHECK: 0x6 R_386_32 .L.str1 // CHECK: 0xB R_386_PC32 puts // CHECK: 0x12 R_386_32 .L.str2 diff --git a/test/MC/ELF/basic-elf-64.s b/test/MC/ELF/basic-elf-64.s index a77f3e6..d99125e 100644 --- a/test/MC/ELF/basic-elf-64.s +++ b/test/MC/ELF/basic-elf-64.s @@ -45,7 +45,7 @@ main: # @main // CHECK: Name: .rela.text // CHECK: Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK: 0x5 R_X86_64_32 .rodata.str1.1 0x0 // CHECK: 0xA R_X86_64_PC32 puts 0xFFFFFFFFFFFFFFFC // CHECK: 0xF R_X86_64_32 .rodata.str1.1 0x6 diff --git a/test/MC/ELF/cfi-adjust-cfa-offset.s b/test/MC/ELF/cfi-adjust-cfa-offset.s index 200f897..bbaa785 100644 --- a/test/MC/ELF/cfi-adjust-cfa-offset.s +++ b/test/MC/ELF/cfi-adjust-cfa-offset.s @@ -53,7 +53,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x3C8 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 72 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-advance-loc2.s b/test/MC/ELF/cfi-advance-loc2.s index 98caa01..be14a43 100644 --- a/test/MC/ELF/cfi-advance-loc2.s +++ b/test/MC/ELF/cfi-advance-loc2.s @@ -38,7 +38,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x490 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-def-cfa-offset.s b/test/MC/ELF/cfi-def-cfa-offset.s index 59f7400..d84ab82 100644 --- a/test/MC/ELF/cfi-def-cfa-offset.s +++ b/test/MC/ELF/cfi-def-cfa-offset.s @@ -40,7 +40,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x398 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-def-cfa-register.s b/test/MC/ELF/cfi-def-cfa-register.s index 178ba32..1efe0b2 100644 --- a/test/MC/ELF/cfi-def-cfa-register.s +++ b/test/MC/ELF/cfi-def-cfa-register.s @@ -35,7 +35,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-def-cfa.s b/test/MC/ELF/cfi-def-cfa.s index dfb0d4b..5e185d5 100644 --- a/test/MC/ELF/cfi-def-cfa.s +++ b/test/MC/ELF/cfi-def-cfa.s @@ -35,7 +35,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-escape.s b/test/MC/ELF/cfi-escape.s index 5394ee4..5c427d6 100644 --- a/test/MC/ELF/cfi-escape.s +++ b/test/MC/ELF/cfi-escape.s @@ -36,7 +36,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-offset.s b/test/MC/ELF/cfi-offset.s index a65b4fc..ad73b50 100644 --- a/test/MC/ELF/cfi-offset.s +++ b/test/MC/ELF/cfi-offset.s @@ -35,7 +35,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-register.s b/test/MC/ELF/cfi-register.s index 9441770..48fd879 100644 --- a/test/MC/ELF/cfi-register.s +++ b/test/MC/ELF/cfi-register.s @@ -36,7 +36,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-rel-offset.s b/test/MC/ELF/cfi-rel-offset.s index 0dc69c8..15e1f9e 100644 --- a/test/MC/ELF/cfi-rel-offset.s +++ b/test/MC/ELF/cfi-rel-offset.s @@ -44,7 +44,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x3A0 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-rel-offset2.s b/test/MC/ELF/cfi-rel-offset2.s index 360e7b0..53c2075 100644 --- a/test/MC/ELF/cfi-rel-offset2.s +++ b/test/MC/ELF/cfi-rel-offset2.s @@ -35,7 +35,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-remember.s b/test/MC/ELF/cfi-remember.s index 3a38948..d9de0ff 100644 --- a/test/MC/ELF/cfi-remember.s +++ b/test/MC/ELF/cfi-remember.s @@ -38,7 +38,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-restore.s b/test/MC/ELF/cfi-restore.s index e225797..19e1624 100644 --- a/test/MC/ELF/cfi-restore.s +++ b/test/MC/ELF/cfi-restore.s @@ -36,7 +36,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-same-value.s b/test/MC/ELF/cfi-same-value.s index 2d37f4d..53da4dc 100644 --- a/test/MC/ELF/cfi-same-value.s +++ b/test/MC/ELF/cfi-same-value.s @@ -36,7 +36,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-undefined.s b/test/MC/ELF/cfi-undefined.s index 568b315..7afeea6 100644 --- a/test/MC/ELF/cfi-undefined.s +++ b/test/MC/ELF/cfi-undefined.s @@ -36,7 +36,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-window-save.s b/test/MC/ELF/cfi-window-save.s index b083901..00fd37f 100644 --- a/test/MC/ELF/cfi-window-save.s +++ b/test/MC/ELF/cfi-window-save.s @@ -38,7 +38,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi-zero-addr-delta.s b/test/MC/ELF/cfi-zero-addr-delta.s index 8662839..85aa3e1 100644 --- a/test/MC/ELF/cfi-zero-addr-delta.s +++ b/test/MC/ELF/cfi-zero-addr-delta.s @@ -43,7 +43,7 @@ f: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x398 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/cfi.s b/test/MC/ELF/cfi.s index 21be615..dc61dca 100644 --- a/test/MC/ELF/cfi.s +++ b/test/MC/ELF/cfi.s @@ -355,7 +355,7 @@ f37: // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0xE70 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 1752 // CHECK-NEXT: Link: 7 // CHECK-NEXT: Info: 4 diff --git a/test/MC/ELF/common.s b/test/MC/ELF/common.s index bd96564..b7e6ba0 100644 --- a/test/MC/ELF/common.s +++ b/test/MC/ELF/common.s @@ -45,7 +45,7 @@ // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Object // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: Section: .bss // CHECK-NEXT: } diff --git a/test/MC/ELF/compression.s b/test/MC/ELF/compression.s index 07b689e..5560ba7 100644 --- a/test/MC/ELF/compression.s +++ b/test/MC/ELF/compression.s @@ -10,7 +10,6 @@ // Check for the 'ZLIB' file magic at the start of the section only // CHECK-NEXT: ZLIB // CHECK-NOT: ZLIB -// CHECK: Contents of // Don't compress small sections, such as this simple debug_abbrev example // CHECK: Contents of section .debug_abbrev: diff --git a/test/MC/ELF/debug-line.s b/test/MC/ELF/debug-line.s index 38ef828..072265c 100644 --- a/test/MC/ELF/debug-line.s +++ b/test/MC/ELF/debug-line.s @@ -17,7 +17,7 @@ // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 57 // CHECK-NEXT: Link: 0 // CHECK-NEXT: Info: 0 diff --git a/test/MC/ELF/ifunc-reloc.s b/test/MC/ELF/ifunc-reloc.s index 0195463..6f1d79b 100644 --- a/test/MC/ELF/ifunc-reloc.s +++ b/test/MC/ELF/ifunc-reloc.s @@ -10,7 +10,7 @@ alias: callq sym // CHECK: Relocations [ -// CHECK-NEXT: Section (2) .rela.text { +// CHECK-NEXT: Section {{.*}} .rela.text { // CHECK-NEXT: 0x1 R_X86_64_PC32 sym 0xFFFFFFFFFFFFFFFC // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/ELF/local-reloc.s b/test/MC/ELF/local-reloc.s index 19b9509..ce0b674 100644 --- a/test/MC/ELF/local-reloc.s +++ b/test/MC/ELF/local-reloc.s @@ -7,7 +7,7 @@ foo: // CHECK: Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}} // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/ELF/merge.s b/test/MC/ELF/merge.s index d6e0b7c..e787728 100644 --- a/test/MC/ELF/merge.s +++ b/test/MC/ELF/merge.s @@ -21,7 +21,7 @@ zed: foo: // CHECK: Relocations [ -// CHECK-NEXT: Section (2) .rela.text { +// CHECK-NEXT: Section {{.*}} .rela.text { // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PC32 .Lfoo 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .sec1 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .Lfoo 0x{{[^ ]+}} diff --git a/test/MC/ELF/pr19582.s b/test/MC/ELF/pr19582.s new file mode 100644 index 0000000..304cacb --- /dev/null +++ b/test/MC/ELF/pr19582.s @@ -0,0 +1,8 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s + +a: + .section foo + c = b +b: + // CHECK: 0x0 R_X86_64_PC32 .text 0x0 + .long a - c diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s index b998ea5..2af6add 100644 --- a/test/MC/ELF/relocation-386.s +++ b/test/MC/ELF/relocation-386.s @@ -4,7 +4,7 @@ // correctly point to the section or the symbol. // CHECK: Relocations [ -// CHECK-NEXT: Section (2) .rel.text { +// CHECK-NEXT: Section {{.*}} .rel.text { // CHECK-NEXT: 0x2 R_386_GOTOFF .Lfoo 0x0 // CHECK-NEXT: 0x{{[^ ]+}} R_386_PLT32 bar2 0x0 // CHECK-NEXT: 0x{{[^ ]+}} R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 @@ -79,7 +79,7 @@ // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: TLS // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: zedsec (0x5) +// CHECK-NEXT: Section: zedsec // CHECK-NEXT: } // Symbol 7 is section 4 // CHECK: Symbol { @@ -89,7 +89,7 @@ // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Section // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: Section: .bss // CHECK-NEXT: } .text diff --git a/test/MC/ELF/relocation-pc.s b/test/MC/ELF/relocation-pc.s index 0ce3201..a8783a7 100644 --- a/test/MC/ELF/relocation-pc.s +++ b/test/MC/ELF/relocation-pc.s @@ -13,13 +13,13 @@ // CHECK-NEXT: } // CHECK: Section { -// CHECK: Index: 2 -// CHECK-NEXT: Name: .rela.text +// CHECK: Index: +// CHECK: Name: .rela.text // CHECK-NEXT: Type: SHT_RELA // CHECK-NEXT: Flags [ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x2E8 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 48 // CHECK-NEXT: Link: 6 // CHECK-NEXT: Info: 1 diff --git a/test/MC/ELF/rename.s b/test/MC/ELF/rename.s index 5364dde..a7f9638 100644 --- a/test/MC/ELF/rename.s +++ b/test/MC/ELF/rename.s @@ -15,33 +15,14 @@ defined3: .global defined1 -// Section 1 is .text // CHECK: Section { -// CHECK: Index: 1 -// CHECK-NEXT: Name: .text -// CHECK-NEXT: Type: SHT_PROGBITS -// CHECK-NEXT: Flags [ -// CHECK-NEXT: SHF_ALLOC -// CHECK-NEXT: SHF_EXECINSTR -// CHECK-NEXT: ] -// CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x40 -// CHECK-NEXT: Size: 4 -// CHECK-NEXT: Link: 0 -// CHECK-NEXT: Info: 0 -// CHECK-NEXT: AddressAlignment: 4 -// CHECK-NEXT: EntrySize: 0 -// CHECK-NEXT: Relocations [ -// CHECK-NEXT: ] -// CHECK-NEXT: } -// CHECK-NEXT: Section { -// CHECK-NEXT: Index: 2 -// CHECK-NEXT: Name: .rela.text (1) +// CHECK: Index: +// CHECK: Name: .rela.text // CHECK-NEXT: Type: SHT_RELA (0x4) // CHECK-NEXT: Flags [ (0x0) // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 -// CHECK-NEXT: Offset: 0x320 +// CHECK-NEXT: Offset: // CHECK-NEXT: Size: 24 // CHECK-NEXT: Link: 6 // CHECK-NEXT: Info: 1 @@ -51,15 +32,3 @@ defined3: // CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 // CHECK-NEXT: ] // CHECK-NEXT: } - - -// Symbol 2 is section 1 -// CHECK: Symbol { -// CHECK: Name: .text (0) -// CHECK-NEXT: Value: 0x0 -// CHECK-NEXT: Size: 0 -// CHECK-NEXT: Binding: Local -// CHECK-NEXT: Type: Section -// CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) -// CHECK-NEXT: } diff --git a/test/MC/ELF/section-sym2.s b/test/MC/ELF/section-sym2.s index acdb7d9..f62e3f9 100644 --- a/test/MC/ELF/section-sym2.s +++ b/test/MC/ELF/section-sym2.s @@ -6,7 +6,7 @@ mov .rodata, %rsi .section .rodata // CHECK:Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK: Relocation { // CHECK: Offset: 0x4 // CHECK: Type: R_X86_64_32S (11) diff --git a/test/MC/ELF/section-unique-err1.s b/test/MC/ELF/section-unique-err1.s new file mode 100644 index 0000000..3a997d1 --- /dev/null +++ b/test/MC/ELF/section-unique-err1.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s + +// CHECK: error: expected absolute expression + + .section .text,"ax",@progbits,unique, "abc" diff --git a/test/MC/ELF/section-unique-err2.s b/test/MC/ELF/section-unique-err2.s new file mode 100644 index 0000000..7b7cd5f --- /dev/null +++ b/test/MC/ELF/section-unique-err2.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s + +// CHECK: error: unique id must be positive + + .section .text,"ax",@progbits,unique, -1 diff --git a/test/MC/ELF/section-unique-err3.s b/test/MC/ELF/section-unique-err3.s new file mode 100644 index 0000000..bbccd24 --- /dev/null +++ b/test/MC/ELF/section-unique-err3.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s + +// CHECK: error: unique id is too large + + .section .text,"ax",@progbits,unique, 4294967295 diff --git a/test/MC/ELF/section-unique-err4.s b/test/MC/ELF/section-unique-err4.s new file mode 100644 index 0000000..3c82682 --- /dev/null +++ b/test/MC/ELF/section-unique-err4.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s + +// CHECK: error: expected commma + + .section .text,"ax",@progbits,unique 1 diff --git a/test/MC/ELF/section-unique.s b/test/MC/ELF/section-unique.s index b482af3..3fe7271 100644 --- a/test/MC/ELF/section-unique.s +++ b/test/MC/ELF/section-unique.s @@ -1,22 +1,22 @@ // RUN: llvm-mc -triple x86_64-pc-linux-gnu %s -o - | FileCheck %s // RUN: llvm-mc -triple x86_64-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -t | FileCheck %s --check-prefix=OBJ - .section .text,"ax",@progbits,unique + .section .text,"ax",@progbits,unique, 4294967293 .globl f f: nop - .section .text,"ax",@progbits,unique + .section .text,"ax",@progbits,unique, 4294967294 .globl g g: nop // test that f and g are in different sections. -// CHECK: .section .text,"ax",@progbits,unique +// CHECK: .section .text,"ax",@progbits,unique,4294967293 // CHECK: f: -// CHECK: .section .text,"ax",@progbits,unique +// CHECK: .section .text,"ax",@progbits,unique,4294967294 // CHECK: g: // OBJ: Symbol { diff --git a/test/MC/ELF/symver-msvc.s b/test/MC/ELF/symver-msvc.s index d6730ca..a726ff3 100644 --- a/test/MC/ELF/symver-msvc.s +++ b/test/MC/ELF/symver-msvc.s @@ -11,7 +11,7 @@ // CHECK: Relocations [ -// CHECK-NEXT: Section (2) .rela.text { +// CHECK-NEXT: Section {{.*}} .rela.text { // CHECK-NEXT: 0x0 R_X86_64_32 ??_R0?AVexception@std@@@8 0x0 // CHECK-NEXT: 0x4 R_X86_64_32 @??_R0?AVinvalid_argument@std@@@8 0x0 // CHECK-NEXT: 0x8 R_X86_64_32 __imp_??_R0?AVlogic_error@std@@@8 0x0 diff --git a/test/MC/ELF/symver.s b/test/MC/ELF/symver.s index 6e5825f..80d71fd 100644 --- a/test/MC/ELF/symver.s +++ b/test/MC/ELF/symver.s @@ -22,7 +22,7 @@ defined3: global1: // CHECK: Relocations [ -// CHECK-NEXT: Section (2) .rela.text { +// CHECK-NEXT: Section {{.*}} .rela.text { // CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 // CHECK-NEXT: 0x4 R_X86_64_32 bar2@zed 0x0 // CHECK-NEXT: 0x8 R_X86_64_32 .text 0x0 diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s index 79865cd..940827b 100644 --- a/test/MC/ELF/tls.s +++ b/test/MC/ELF/tls.s @@ -19,7 +19,7 @@ foobar: // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: TLS // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .zed (0x5) +// CHECK-NEXT: Section: .zed // CHECK-NEXT: } // CHECK: Symbol { diff --git a/test/MC/ELF/weak-diff2.s b/test/MC/ELF/weak-diff2.s new file mode 100644 index 0000000..daf64a4 --- /dev/null +++ b/test/MC/ELF/weak-diff2.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t 2>&1 | FileCheck %s + +// CHECK: error: Cannot represent a subtraction with a weak symbol + +.weak f +f: + nop +g: + nop +.quad g - f diff --git a/test/MC/ELF/weakref.s b/test/MC/ELF/weakref.s index 2288264..9485e49 100644 --- a/test/MC/ELF/weakref.s +++ b/test/MC/ELF/weakref.s @@ -131,7 +131,7 @@ bar15: // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Section // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .data (0x3) +// CHECK-NEXT: Section: .data // CHECK-NEXT: } // CHECK-NEXT: Symbol { // CHECK-NEXT: Name: .bss @@ -140,7 +140,7 @@ bar15: // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Section // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: Section: .bss // CHECK-NEXT: } // CHECK-NEXT: Symbol { // CHECK-NEXT: Name: bar10 diff --git a/test/MC/Hexagon/inst_select.ll b/test/MC/Hexagon/inst_select.ll index 7e88c65..29a2db0 100644 --- a/test/MC/Hexagon/inst_select.ll +++ b/test/MC/Hexagon/inst_select.ll @@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c) ret i32 %1 } -; CHECK: 0000 00400085 004201f4 00c09f52 +; CHECK: 0000 00400085 00600174 00608274 00c09f52 diff --git a/test/MC/MachO/ARM/aliased-symbols.s b/test/MC/MachO/ARM/aliased-symbols.s index e87b81c..cc2e200 100644 --- a/test/MC/MachO/ARM/aliased-symbols.s +++ b/test/MC/MachO/ARM/aliased-symbols.s @@ -45,9 +45,9 @@ Ltmp0: // CHECK-NEXT: Value: 0x[[DEFINED_EARLY]] // CHECK-NEXT: } - // defined_late was defined. Just after defined_early. + // alias_to_late was an alias to defined_late. But we can resolve it. // CHECK: Symbol { -// CHECK-NEXT: Name: defined_late +// CHECK-NEXT: Name: alias_to_late // CHECK-NEXT: Type: Section (0xE) // CHECK-NEXT: Section: __data (0x2) // CHECK-NEXT: RefType: UndefinedNonLazy (0x0) @@ -56,9 +56,9 @@ Ltmp0: // CHECK-NEXT: Value: 0x[[DEFINED_LATE:[0-9A-F]+]] // CHECK-NEXT: } - // alias_to_late was an alias to defined_late. But we can resolve it. + // defined_late was defined. Just after defined_early. // CHECK: Symbol { -// CHECK-NEXT: Name: alias_to_late +// CHECK-NEXT: Name: defined_late // CHECK-NEXT: Type: Section (0xE) // CHECK-NEXT: Section: __data (0x2) // CHECK-NEXT: RefType: UndefinedNonLazy (0x0) @@ -72,7 +72,7 @@ Ltmp0: // CHECK: Symbol { // CHECK-NEXT: Name: alias_to_local (42) // CHECK-NEXT: Type: Section (0xE) -// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: Section: __data (0x2) // CHECK-NEXT: RefType: UndefinedNonLazy (0x0) // CHECK-NEXT: Flags [ (0x0) // CHECK-NEXT: ] diff --git a/test/MC/Mips/elf-tls.s b/test/MC/Mips/elf-tls.s index d32a699..d50f62c 100644 --- a/test/MC/Mips/elf-tls.s +++ b/test/MC/Mips/elf-tls.s @@ -3,7 +3,7 @@ // Check that the appropriate relocations were created. // CHECK: Relocations [ -// CHECK: Section (2) .rel.text { +// CHECK: Section {{.*}} .rel.text { // CHECK: R_MIPS_TLS_LDM // CHECK: R_MIPS_TLS_DTPREL_HI16 // CHECK: R_MIPS_TLS_DTPREL_LO16 diff --git a/test/MC/Mips/insn-directive.s b/test/MC/Mips/insn-directive.s new file mode 100644 index 0000000..760a273 --- /dev/null +++ b/test/MC/Mips/insn-directive.s @@ -0,0 +1,98 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | FileCheck %s --check-prefix=ASM + +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-readobj -symbols - | FileCheck %s --check-prefix=OBJ + + .set micromips + + .global f_mm_insn_data + .type f_mm_insn_data, @function +f_mm_insn_data: + .insn + .word 0x00e73910 # add $7, $7, $7 + + .global f_mm_insn_instr + .type f_mm_insn_instr, @function +f_mm_insn_instr: + .insn + add $7, $7, $7 + + .global o_mm_insn_data + .type o_mm_insn_data, @object +o_mm_insn_data: + .insn + .word 0x00e73910 # add $7, $7, $7 + + .global o_mm_insn_instr + .type o_mm_insn_instr, @object +o_mm_insn_instr: + .insn + add $7, $7, $7 + + .set nomicromips + + .global f_normal_insn_data + .type f_normal_insn_data, @function +f_normal_insn_data: + .insn + .word 0x00e73820 # add $7, $7, $7 + + .global f_normal_insn_instr + .type f_normal_insn_instr, @function +f_normal_insn_instr: + .insn + add $7, $7, $7 + + .global o_normal_insn_data + .type o_normal_insn_data, @object +o_normal_insn_data: + .insn + .word 0x00e73820 # add $7, $7, $7 + + .global o_normal_insn_instr + .type o_normal_insn_instr, @object +o_normal_insn_instr: + .insn + add $7, $7, $7 + +# Verify that .insn causes the currently saved labels to be cleared by checking +# that foo doesn't get marked. + .set nomicromips +foo: + .insn + .word 0x00e73820 # add $7, $7, $7 + + .set micromips +bar: + add $7, $7, $7 + +# ASM: .insn + +# OBJ: Symbols [ +# OBJ: Name: foo +# OBJ: Other: 0 + +# OBJ: Name: f_mm_insn_data +# OBJ: Other: 128 + +# OBJ: Name: f_mm_insn_instr +# OBJ: Other: 128 + +# OBJ: Name: f_normal_insn_data +# OBJ: Other: 0 + +# OBJ: Name: f_normal_insn_instr +# OBJ: Other: 0 + +# OBJ: Name: o_mm_insn_data +# OBJ: Other: 128 + +# OBJ: Name: o_mm_insn_instr +# OBJ: Other: 128 + +# OBJ: Name: o_normal_insn_data +# OBJ: Other: 0 + +# OBJ: Name: o_normal_insn_instr +# OBJ: Other: 0 +# OBJ: ] diff --git a/test/MC/Mips/micromips-alias.s b/test/MC/Mips/micromips-alias.s index c0bf4b3..256b3b6 100644 --- a/test/MC/Mips/micromips-alias.s +++ b/test/MC/Mips/micromips-alias.s @@ -14,3 +14,15 @@ f: nop .globl bar bar = f + +# CHECK: Name: foo +# CHECK: Other: 128 + .type o,@object + .set micromips +o: + .insn + .word 0x00000000 + .set nomicromips + + .globl foo +foo = o diff --git a/test/MC/Mips/mips-expansions-bad.s b/test/MC/Mips/mips-expansions-bad.s index 8d85169..d9bac20 100644 --- a/test/MC/Mips/mips-expansions-bad.s +++ b/test/MC/Mips/mips-expansions-bad.s @@ -1,6 +1,8 @@ # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 # RUN: FileCheck %s < %t1 - .text - li $5, 0x100000000 # CHECK: :[[@LINE]]:9: error: instruction requires a 64-bit architecture - dli $5, 1 # CHECK: :[[@LINE]]:9: error: instruction requires a 64-bit architecture + .text + li $5, 0x100000000 + # CHECK: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture + dli $5, 1 + # CHECK: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s index bdc76fb..490b814 100644 --- a/test/MC/Mips/mips-expansions.s +++ b/test/MC/Mips/mips-expansions.s @@ -50,6 +50,17 @@ # CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] # CHECK: sw $10, 57920($1) # encoding: [0x40,0xe2,0x2a,0xac] +# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] +# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-NOT: move $8, $8 # encoding: [0x21,0x40,0x00,0x01] +# CHECK: lw $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d] +# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c] +# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-NOT: move $1, $1 # encoding: [0x21,0x08,0x20,0x00] +# CHECK: sw $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac] +# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 + # CHECK: lui $1, %hi(symbol) # CHECK: ldc1 $f0, %lo(symbol)($1) # CHECK: lui $1, %hi(symbol) @@ -77,5 +88,8 @@ lw $t2, 655483($a0) sw $t2, 123456($t1) + lw $8, symbol + sw $8, symbol + ldc1 $f0, symbol sdc1 $f0, symbol diff --git a/test/MC/Mips/mips-jump-delay-slots.s b/test/MC/Mips/mips-jump-delay-slots.s index 49f6c15..c52416f 100644 --- a/test/MC/Mips/mips-jump-delay-slots.s +++ b/test/MC/Mips/mips-jump-delay-slots.s @@ -68,9 +68,15 @@ # CHECK: beql $9, $6, 1332 # CHECK-NOT: nop beql $9,$6,1332 + # CHECK: beql $9, $zero, 1332 + # CHECK-NOT: nop + beqzl $9,1332 # CHECK: bnel $9, $6, 1332 # CHECK-NOT: nop bnel $9,$6,1332 + # CHECK: bnel $9, $zero, 1332 + # CHECK-NOT: nop + bnezl $9,1332 # CHECK: bgezl $6, 1332 # CHECK-NOT: nop bgezl $6,1332 diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s index d18f6f5..e2feeac 100644 --- a/test/MC/Mips/mips1/valid.s +++ b/test/MC/Mips/mips1/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -41,6 +41,11 @@ div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) lh $11,-8556($s5) @@ -117,3 +122,5 @@ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index 6ee6512..93fdbaf 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -57,6 +57,11 @@ ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) @@ -166,3 +171,5 @@ trunc.w.s $f28,$f30 xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s index 6d55079..954631d 100644 --- a/test/MC/Mips/mips3/valid.s +++ b/test/MC/Mips/mips3/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -109,6 +109,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) ld $sp,-28645($s1) @@ -229,3 +234,5 @@ trunc.w.s $f28,$f30 xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index ba75d77..3765044 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -66,6 +66,11 @@ eret floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) @@ -196,3 +201,5 @@ trunc.w.s $f28,$f30 xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index 61be290..ee7af3f 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -72,6 +72,11 @@ eret floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -235,3 +240,5 @@ xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] + +1: diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s index ff6589d..0a4e5b1 100644 --- a/test/MC/Mips/mips32r3/valid.s +++ b/test/MC/Mips/mips32r3/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -72,6 +72,11 @@ eret floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -235,3 +240,5 @@ xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] + +1: diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s index 408d0cc..036b908 100644 --- a/test/MC/Mips/mips32r5/valid.s +++ b/test/MC/Mips/mips32r5/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -72,6 +72,11 @@ eret floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -235,3 +240,5 @@ xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] + +1: diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 7033d4a..2c3a5b2 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -12,7 +12,7 @@ # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 2> %t0 | FileCheck %s # RUN: FileCheck %s -check-prefix=WARNING < %t0 - +a: .set noat # FIXME: Add the instructions carried forward from older ISA's and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] @@ -146,6 +146,11 @@ rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -176,3 +181,5 @@ tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index 7fcf781..a23990c 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -113,6 +113,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) ld $sp,-28645($s1) @@ -258,3 +263,5 @@ trunc.w.s $f28,$f30 xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index 4b1282e..094c07f 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -113,6 +113,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) ld $sp,-28645($s1) @@ -260,3 +265,5 @@ trunc.w.s $f28,$f30 xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index d900ab7..1a65152 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -118,6 +118,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] lb $24,-14515($10) lbu $8,30195($v1) ld $sp,-28645($s1) @@ -277,3 +282,5 @@ trunc.w.s $f28,$f30 xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 7193451..61b1d6d 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -131,6 +131,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -304,3 +309,5 @@ xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] wsbh $k1,$9 + +1: diff --git a/test/MC/Mips/mips64r3/valid.s b/test/MC/Mips/mips64r3/valid.s index 3a3f7ad..bfd16d3 100644 --- a/test/MC/Mips/mips64r3/valid.s +++ b/test/MC/Mips/mips64r3/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -131,6 +131,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -304,3 +309,5 @@ xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] wsbh $k1,$9 + +1: diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s index 5ba102d..22c5093 100644 --- a/test/MC/Mips/mips64r5/valid.s +++ b/test/MC/Mips/mips64r5/valid.s @@ -1,7 +1,7 @@ # Instructions that are valid # # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s - +a: .set noat abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 @@ -131,6 +131,11 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -304,3 +309,5 @@ xor $s2,$a0,$s8 xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] wsbh $k1,$9 + +1: diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 600cb48..31a0d7f 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -12,7 +12,7 @@ # # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s # RUN: FileCheck %s -check-prefix=WARNING < %t0 - +a: .set noat # FIXME: Add the instructions carried forward from older ISA's and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] @@ -165,6 +165,11 @@ rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] + j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j a # CHECK: j a # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 + j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] @@ -199,3 +204,5 @@ tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] + +1: diff --git a/test/MC/Mips/set-defined-symbol.s b/test/MC/Mips/set-defined-symbol.s new file mode 100644 index 0000000..54db45d --- /dev/null +++ b/test/MC/Mips/set-defined-symbol.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-objdump -d -r -arch=mips - | FileCheck %s + + .global foo + .weak bar + .set bar, b + .set foo, b + .set foo, a +a: + nop +# CHECK-NOT: a: +# CHECK: foo: + +b: + nop +# CHECK-NOT: b: +# CHECK-NOT: foo: +# CHECK: bar: diff --git a/test/MC/Mips/sort-relocation-table.s b/test/MC/Mips/sort-relocation-table.s new file mode 100644 index 0000000..590f8fd --- /dev/null +++ b/test/MC/Mips/sort-relocation-table.s @@ -0,0 +1,125 @@ +# RUN: llvm-mc -filetype=obj -arch mipsel %s | llvm-readobj -r | FileCheck %s + +# Test the order of records in the relocation table. +# *HI16 and local *GOT16 relocations should be immediately followed by the +# corresponding *LO16 relocation against the same symbol. +# +# We try to implement the same semantics as gas, ie. to order the relocation +# table the same way as gas. +# +# gnu as command line: +# mips-linux-gnu-as -EL sort-relocation-table.s -o sort-relocation-table.o +# +# TODO: Add mips16 and micromips tests. +# Note: offsets are part of expected output, so it's simpler to add new test +# cases at the bottom of the file. + +# CHECK: Relocations [ +# CHECK-NEXT: { + +# Put HI before LO. +addiu $2,$2,%lo(sym1) +lui $2,%hi(sym1) + +# CHECK-NEXT: 0x4 R_MIPS_HI16 sym1 +# CHECK-NEXT: 0x0 R_MIPS_LO16 sym1 + +# When searching for a matching LO, ignore LOs against a different symbol. +addiu $2,$2,%lo(sym2) +lui $2,%hi(sym2) +addiu $2,$2,%lo(sym2_d) + +# CHECK-NEXT: 0xC R_MIPS_HI16 sym2 +# CHECK-NEXT: 0x8 R_MIPS_LO16 sym2 +# CHECK-NEXT: 0x10 R_MIPS_LO16 sym2_d + +# Match HI with 2nd LO because it has higher offset (than the 1st LO). +addiu $2,$2,%lo(sym3) +addiu $2,$2,%lo(sym3) +lui $2,%hi(sym3) + +# CHECK-NEXT: 0x14 R_MIPS_LO16 sym3 +# CHECK-NEXT: 0x1C R_MIPS_HI16 sym3 +# CHECK-NEXT: 0x18 R_MIPS_LO16 sym3 + +# HI is already followed by a matching LO, so don't look further, ie. ignore the +# "free" LO with higher offset. +lui $2,%hi(sym4) +addiu $2,$2,%lo(sym4) +addiu $2,$2,%lo(sym4) + +# CHECK-NEXT: 0x20 R_MIPS_HI16 sym4 +# CHECK-NEXT: 0x24 R_MIPS_LO16 sym4 +# CHECK-NEXT: 0x28 R_MIPS_LO16 sym4 + +# Match 2nd HI with 2nd LO, since it's the one with highest offset among the +# "free" ones. +addiu $2,$2,%lo(sym5) +addiu $2,$2,%lo(sym5) +lui $2,%hi(sym5) +addiu $2,$2,%lo(sym5) +lui $2,%hi(sym5) + +# CHECK-NEXT: 0x2C R_MIPS_LO16 sym5 +# CHECK-NEXT: 0x3C R_MIPS_HI16 sym5 +# CHECK-NEXT: 0x30 R_MIPS_LO16 sym5 +# CHECK-NEXT: 0x34 R_MIPS_HI16 sym5 +# CHECK-NEXT: 0x38 R_MIPS_LO16 sym5 + +# When more HIs are matched with one LO, sort them in descending order of +# offset. +addiu $2,$2,%lo(sym6) +lui $2,%hi(sym6) +lui $2,%hi(sym6) + +# CHECK-NEXT: 0x48 R_MIPS_HI16 sym6 +# CHECK-NEXT: 0x44 R_MIPS_HI16 sym6 +# CHECK-NEXT: 0x40 R_MIPS_LO16 sym6 + +# sym7 is a local symbol, so GOT relocation against it needs a matching LO. +sym7: +addiu $2,$2,%lo(sym7) +lui $2,%got(sym7) + +# CHECK-NEXT: 0x50 R_MIPS_GOT16 sym7 +# CHECK-NEXT: 0x4C R_MIPS_LO16 sym7 + +# sym8 is not a local symbol, don't look for a matching LO for GOT. +.global sym8 +addiu $2,$2,%lo(sym8) +lui $2,%got(sym8) + +# CHECK-NEXT: 0x54 R_MIPS_LO16 sym8 +# CHECK-NEXT: 0x58 R_MIPS_GOT16 sym8 + +# A small combination of previous checks. +symc1: +addiu $2,$2,%lo(symc1) +addiu $2,$2,%lo(symc1) +addiu $2,$2,%lo(symc1) +lui $2,%hi(symc1) +lui $2,%got(symc1) +addiu $2,$2,%lo(symc2) +lui $2,%hi(symc1) +lui $2,%hi(symc1) +lui $2,%got(symc2) +lui $2,%hi(symc1) +addiu $2,$2,%lo(symc1) +addiu $2,$2,%lo(symc2) +lui $2,%hi(symc1) +lui $2,%hi(symc1) + +# CHECK-NEXT: 0x78 R_MIPS_HI16 symc1 +# CHECK-NEXT: 0x74 R_MIPS_HI16 symc1 +# CHECK-NEXT: 0x6C R_MIPS_GOT16 symc1 +# CHECK-NEXT: 0x68 R_MIPS_HI16 symc1 +# CHECK-NEXT: 0x5C R_MIPS_LO16 symc1 +# CHECK-NEXT: 0x8C R_MIPS_HI16 symc1 +# CHECK-NEXT: 0x60 R_MIPS_LO16 symc1 +# CHECK-NEXT: 0x90 R_MIPS_HI16 symc1 +# CHECK-NEXT: 0x64 R_MIPS_LO16 symc1 +# CHECK-NEXT: 0x70 R_MIPS_LO16 symc2 +# CHECK-NEXT: 0x7C R_MIPS_GOT16 symc2 +# CHECK-NEXT: 0x80 R_MIPS_HI16 symc1 +# CHECK-NEXT: 0x84 R_MIPS_LO16 symc1 +# CHECK-NEXT: 0x88 R_MIPS_LO16 symc2 diff --git a/test/MC/Mips/xgot.s b/test/MC/Mips/xgot.s index 3084806..3380a85 100644 --- a/test/MC/Mips/xgot.s +++ b/test/MC/Mips/xgot.s @@ -9,8 +9,8 @@ // CHECK: 0x14 R_MIPS_GOT_HI16 ext_1 // CHECK: 0x1C R_MIPS_GOT_LO16 ext_1 // CHECK: 0x24 R_MIPS_CALL_HI16 printf -// CHECK: 0x2C R_MIPS_GOT16 $.str // CHECK: 0x30 R_MIPS_CALL_LO16 printf +// CHECK: 0x2C R_MIPS_GOT16 $.str // CHECK: 0x38 R_MIPS_LO16 $.str // CHECK: ] diff --git a/test/MC/PowerPC/ppc-reloc.s b/test/MC/PowerPC/ppc-reloc.s index e7dd1e2..999d33e 100644 --- a/test/MC/PowerPC/ppc-reloc.s +++ b/test/MC/PowerPC/ppc-reloc.s @@ -12,7 +12,7 @@ foo: .size foo, . - foo # CHECK: Relocations [ -# CHECK-NEXT: Section (2) .rela.text { +# CHECK-NEXT: Section {{.*}} .rela.text { # CHECK-NEXT: 0x0 R_PPC_PLTREL24 printf 0x0 # CHECK-NEXT: 0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC # CHECK-NEXT: } diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index d2ac669..05fde62 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -420,12 +420,20 @@ divwu. 2, 3, 4 # FIXME: divwuo 2, 3, 4 # FIXME: divwuo. 2, 3, 4 -# FIXME: divwe 2, 3, 4 -# FIXME: divwe. 2, 3, 4 +# CHECK-BE: divwe 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x56] +# CHECK-LE: divwe 2, 3, 4 # encoding: [0x56,0x23,0x43,0x7c] + divwe 2, 3, 4 +# CHECK-BE: divwe. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x57] +# CHECK-LE: divwe. 2, 3, 4 # encoding: [0x57,0x23,0x43,0x7c] + divwe. 2, 3, 4 # FIXME: divweo 2, 3, 4 # FIXME: divweo. 2, 3, 4 -# FIXME: divweu 2, 3, 4 -# FIXME: divweu. 2, 3, 4 +# CHECK-BE: divweu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x16] +# CHECK-LE: divweu 2, 3, 4 # encoding: [0x16,0x23,0x43,0x7c] + divweu 2, 3, 4 +# CHECK-BE: divweu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x17] +# CHECK-LE: divweu. 2, 3, 4 # encoding: [0x17,0x23,0x43,0x7c] + divweu. 2, 3, 4 # FIXME: divweuo 2, 3, 4 # FIXME: divweuo. 2, 3, 4 @@ -466,12 +474,20 @@ divdu. 2, 3, 4 # FIXME: divduo 2, 3, 4 # FIXME: divduo. 2, 3, 4 -# FIXME: divde 2, 3, 4 -# FIXME: divde. 2, 3, 4 +# CHECK-BE: divde 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x52] +# CHECK-LE: divde 2, 3, 4 # encoding: [0x52,0x23,0x43,0x7c] + divde 2, 3, 4 +# CHECK-BE: divde. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x53] +# CHECK-LE: divde. 2, 3, 4 # encoding: [0x53,0x23,0x43,0x7c] + divde. 2, 3, 4 # FIXME: divdeo 2, 3, 4 # FIXME: divdeo. 2, 3, 4 -# FIXME: divdeu 2, 3, 4 -# FIXME: divdeu. 2, 3, 4 +# CHECK-BE: divdeu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x12] +# CHECK-LE: divdeu 2, 3, 4 # encoding: [0x12,0x23,0x43,0x7c] + divdeu 2, 3, 4 +# CHECK-BE: divdeu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x13] +# CHECK-LE: divdeu. 2, 3, 4 # encoding: [0x13,0x23,0x43,0x7c] + divdeu. 2, 3, 4 # FIXME: divdeuo 2, 3, 4 # FIXME: divdeuo. 2, 3, 4 @@ -644,7 +660,9 @@ # CHECK-BE: popcntd 2, 3 # encoding: [0x7c,0x62,0x03,0xf4] # CHECK-LE: popcntd 2, 3 # encoding: [0xf4,0x03,0x62,0x7c] popcntd 2, 3 -# FIXME: bpermd 2, 3, 4 +# CHECK-BE: bpermd 2, 3, 4 # encoding: [0x7c,0x62,0x21,0xf8] +# CHECK-LE: bpermd 2, 3, 4 # encoding: [0xf8,0x21,0x62,0x7c] + bpermd 2, 3, 4 # Fixed-point rotate and shift instructions @@ -703,6 +721,33 @@ # CHECK-LE: rldimi. 2, 3, 4, 5 # encoding: [0x4d,0x21,0x62,0x78] rldimi. 2, 3, 4, 5 +# Aliases that take bit masks... + +# CHECK-BE: rlwinm 0, 0, 30, 31, 31 # encoding: [0x54,0x00,0xf7,0xfe] + rlwinm 0, 0, 30, 1 +# CHECK-BE: rlwinm. 0, 0, 30, 31, 31 # encoding: [0x54,0x00,0xf7,0xff] + rlwinm. 0, 0, 30, 1 +# CHECK-BE: rlwinm 0, 0, 30, 31, 0 # encoding: [0x54,0x00,0xf7,0xc0] + rlwinm 0, 0, 30, 2147483649 +# CHECK-BE: rlwinm. 0, 0, 30, 31, 0 # encoding: [0x54,0x00,0xf7,0xc1] + rlwinm. 0, 0, 30, 2147483649 +# CHECK-BE: rlwimi 0, 0, 30, 31, 31 # encoding: [0x50,0x00,0xf7,0xfe] + rlwimi 0, 0, 30, 1 +# CHECK-BE: rlwimi. 0, 0, 30, 31, 31 # encoding: [0x50,0x00,0xf7,0xff] + rlwimi. 0, 0, 30, 1 +# CHECK-BE: rlwimi 0, 0, 30, 31, 0 # encoding: [0x50,0x00,0xf7,0xc0] + rlwimi 0, 0, 30, 2147483649 +# CHECK-BE: rlwimi. 0, 0, 30, 31, 0 # encoding: [0x50,0x00,0xf7,0xc1] + rlwimi. 0, 0, 30, 2147483649 +# CHECK-BE: rlwnm 0, 0, 30, 31, 31 # encoding: [0x5c,0x00,0xf7,0xfe] + rlwnm 0, 0, 30, 1 +# CHECK-BE: rlwnm. 0, 0, 30, 31, 31 # encoding: [0x5c,0x00,0xf7,0xff] + rlwnm. 0, 0, 30, 1 +# CHECK-BE: rlwnm 0, 0, 30, 31, 0 # encoding: [0x5c,0x00,0xf7,0xc0] + rlwnm 0, 0, 30, 2147483649 +# CHECK-BE: rlwnm. 0, 0, 30, 31, 0 # encoding: [0x5c,0x00,0xf7,0xc1] + rlwnm. 0, 0, 30, 2147483649 + # CHECK-BE: slw 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x30] # CHECK-LE: slw 2, 3, 4 # encoding: [0x30,0x20,0x62,0x7c] slw 2, 3, 4 diff --git a/test/MC/PowerPC/tls-gd-obj.s b/test/MC/PowerPC/tls-gd-obj.s index 63d47ee..fb4ab8b 100644 --- a/test/MC/PowerPC/tls-gd-obj.s +++ b/test/MC/PowerPC/tls-gd-obj.s @@ -47,7 +47,7 @@ a: // for the call to __tls_get_addr. // // CHECK: Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSGD a diff --git a/test/MC/PowerPC/tls-ie-obj.s b/test/MC/PowerPC/tls-ie-obj.s index c8c5d91..f7de644 100644 --- a/test/MC/PowerPC/tls-ie-obj.s +++ b/test/MC/PowerPC/tls-ie-obj.s @@ -36,7 +36,7 @@ main: # @main // accessing external variable a. // // CHECK: Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLS a diff --git a/test/MC/PowerPC/tls-ld-obj.s b/test/MC/PowerPC/tls-ld-obj.s index b0c4a7a..1fa371d 100644 --- a/test/MC/PowerPC/tls-ld-obj.s +++ b/test/MC/PowerPC/tls-ld-obj.s @@ -50,7 +50,7 @@ a: // __tls_get_addr. // // CHECK: Relocations [ -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a // CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSLD a diff --git a/test/MC/PowerPC/vsx.s b/test/MC/PowerPC/vsx.s index 4a0053d..c317c37 100644 --- a/test/MC/PowerPC/vsx.s +++ b/test/MC/PowerPC/vsx.s @@ -454,3 +454,20 @@ # CHECK-BE: xxpermdi 7, 63, 63, 2 # encoding: [0xf0,0xff,0xfa,0x56] # CHECK-LE: xxpermdi 7, 63, 63, 2 # encoding: [0x56,0xfa,0xff,0xf0] xxswapd 7, 63 + +# Move to/from VSR +# CHECK-BE: mfvsrd 3, 0 # encoding: [0x7c,0x03,0x00,0x66] +# CHECK-LE: mfvsrd 3, 0 # encoding: [0x66,0x00,0x03,0x7c] + mfvsrd 3, 0 +# CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6] +# CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c] + mfvsrwz 5, 0 +# CHECK-BE: mtvsrd 0, 3 # encoding: [0x7c,0x03,0x01,0x66] +# CHECK-LE: mtvsrd 0, 3 # encoding: [0x66,0x01,0x03,0x7c] + mtvsrd 0, 3 +# CHECK-BE: mtvsrwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6] +# CHECK-LE: mtvsrwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c] + mtvsrwa 0, 3 +# CHECK-BE: mtvsrwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6] +# CHECK-LE: mtvsrwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c] + mtvsrwz 0, 3 diff --git a/test/MC/R600/ds-err.s b/test/MC/R600/ds-err.s new file mode 100644 index 0000000..52c2740 --- /dev/null +++ b/test/MC/R600/ds-err.s @@ -0,0 +1,23 @@ +// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s + +// offset too big +// CHECK: invalid operand for instruction +ds_add_u32 v2, v4 offset:1000000000 + +// offset0 twice +// CHECK: error: not a valid operand. +ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 + +// offset1 twice +// CHECK: error: not a valid operand. +ds_write2_b32 v2, v4, v6 offset1:4 offset1:8 + +// offset0 too big +// CHECK: invalid operand for instruction +ds_write2_b32 v2, v4, v6 offset0:1000000000 + +// offset1 too big +// CHECK: invalid operand for instruction +ds_write2_b32 v2, v4, v6 offset1:1000000000 + diff --git a/test/MC/R600/ds.s b/test/MC/R600/ds.s new file mode 100644 index 0000000..ad63229 --- /dev/null +++ b/test/MC/R600/ds.s @@ -0,0 +1,337 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Checks for 16-bit Offsets +//===----------------------------------------------------------------------===// + +ds_add_u32 v2, v4 offset:16 +// CHECK: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] + +//===----------------------------------------------------------------------===// +// Checks for 2 8-bit Offsets +//===----------------------------------------------------------------------===// + +ds_write2_b32 v2, v4, v6 offset0:4 +// CHECK: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 +// CHECK: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_write2_b32 v2, v4, v6 offset1:8 +// CHECK: ds_write2_b32 v2, v4, v6 offset1:8 ; encoding: [0x00,0x08,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_read2_b32 v[8:9], v2 offset0:4 +// CHECK: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08] + +ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 +// CHECK: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08] + +ds_read2_b32 v[8:9], v2 offset1:8 +// CHECK: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08] +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +ds_add_u32 v2, v4 +// CHECK: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] + +ds_sub_u32 v2, v4 +// CHECK: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00] + +ds_rsub_u32 v2, v4 +// CHECK: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00] + +ds_inc_u32 v2, v4 +// CHECK: ds_inc_u32 v2, v4 ; encoding: [0x00,0x00,0x0c,0xd8,0x02,0x04,0x00,0x00] + +ds_dec_u32 v2, v4 +// CHECK: ds_dec_u32 v2, v4 ; encoding: [0x00,0x00,0x10,0xd8,0x02,0x04,0x00,0x00] + +ds_min_i32 v2, v4 +// CHECK: ds_min_i32 v2, v4 ; encoding: [0x00,0x00,0x14,0xd8,0x02,0x04,0x00,0x00] + +ds_max_i32 v2, v4 +// CHECK: ds_max_i32 v2, v4 ; encoding: [0x00,0x00,0x18,0xd8,0x02,0x04,0x00,0x00] + +ds_min_u32 v2, v4 +// CHECK: ds_min_u32 v2, v4 ; encoding: [0x00,0x00,0x1c,0xd8,0x02,0x04,0x00,0x00] + +ds_max_u32 v2, v4 +// CHECK: ds_max_u32 v2, v4 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x00,0x00] + +ds_and_b32 v2, v4 +// CHECK: ds_and_b32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00] + +ds_or_b32 v2, v4 +// CHECK: ds_or_b32 v2, v4 ; encoding: [0x00,0x00,0x28,0xd8,0x02,0x04,0x00,0x00] + +ds_xor_b32 v2, v4 +// CHECK: ds_xor_b32 v2, v4 ; encoding: [0x00,0x00,0x2c,0xd8,0x02,0x04,0x00,0x00] + +ds_mskor_b32 v2, v4, v6 +// CHECK: ds_mskor_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x30,0xd8,0x02,0x04,0x06,0x00] + +ds_write_b32 v2, v4 +// CHECK: ds_write_b32 v2, v4 ; encoding: [0x00,0x00,0x34,0xd8,0x02,0x04,0x00,0x00] + +ds_write2_b32 v2, v4, v6 +// CHECK: ds_write2_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_write2st64_b32 v2, v4, v6 +// CHECK: ds_write2st64_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x06,0x00] + +ds_cmpst_b32 v2, v4, v6 +// CHECK: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x06,0x00] + +ds_cmpst_f32 v2, v4, v6 +// CHECK: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x06,0x00] + +ds_min_f32 v2, v4, v6 +// CHECK: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x06,0x00] + +ds_max_f32 v2, v4, v6 +// CHECK: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x06,0x00] + +ds_gws_init v2 gds +// CHECK: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_sema_v v2 gds +// CHECK: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_sema_br v2 gds +// CHECK: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_sema_p v2 gds +// CHECK: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x72,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_barrier v2 gds +// CHECK: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00] + +ds_write_b8 v2, v4 +// CHECK: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00] + +ds_write_b16 v2, v4 +// CHECK: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00] + +ds_add_rtn_u32 v8, v2, v4 +// CHECK: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08] + +ds_sub_rtn_u32 v8, v2, v4 +// CHECK: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08] + +ds_rsub_rtn_u32 v8, v2, v4 +// CHECK: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x88,0xd8,0x02,0x04,0x00,0x08] + +ds_inc_rtn_u32 v8, v2, v4 +// CHECK: ds_inc_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x8c,0xd8,0x02,0x04,0x00,0x08] + +ds_dec_rtn_u32 v8, v2, v4 +// CHECK: ds_dec_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x90,0xd8,0x02,0x04,0x00,0x08] + +ds_min_rtn_i32 v8, v2, v4 +// CHECK: ds_min_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x94,0xd8,0x02,0x04,0x00,0x08] + +ds_max_rtn_i32 v8, v2, v4 +// CHECK: ds_max_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x98,0xd8,0x02,0x04,0x00,0x08] + +ds_min_rtn_u32 v8, v2, v4 +// CHECK: ds_min_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x9c,0xd8,0x02,0x04,0x00,0x08] + +ds_max_rtn_u32 v8, v2, v4 +// CHECK: ds_max_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0xa0,0xd8,0x02,0x04,0x00,0x08] + +ds_and_rtn_b32 v8, v2, v4 +// CHECK: ds_and_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xa4,0xd8,0x02,0x04,0x00,0x08] + +ds_or_rtn_b32 v8, v2, v4 +// CHECK: ds_or_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xa8,0xd8,0x02,0x04,0x00,0x08] + +ds_xor_rtn_b32 v8, v2, v4 +// CHECK: ds_xor_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xac,0xd8,0x02,0x04,0x00,0x08] + +ds_mskor_rtn_b32 v8, v2, v4, v6 +// CHECK: ds_mskor_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xb0,0xd8,0x02,0x04,0x06,0x08] + +ds_wrxchg_rtn_b32 v8, v2, v4 +// CHECK: ds_wrxchg_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xb4,0xd8,0x02,0x04,0x00,0x08] + +ds_wrxchg2_rtn_b32 v[8:9], v2, v4, v6 +// CHECK: ds_wrxchg2_rtn_b32 v[8:9], v2, v4, v6 ; encoding: [0x00,0x00,0xb8,0xd8,0x02,0x04,0x06,0x08] + +ds_wrxchg2st64_rtn_b32 v[8:9] v2, v4, v6 +// CHECK: ds_wrxchg2st64_rtn_b32 v[8:9], v2, v4, v6 ; encoding: [0x00,0x00,0xbc,0xd8,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_b32 v8, v2, v4, v6 +// CHECK: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc0,0xd8,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_f32 v8, v2, v4, v6 +// CHECK: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc4,0xd8,0x02,0x04,0x06,0x08] + +ds_min_rtn_f32 v8, v2, v4, v6 +// CHECK: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x06,0x08] + +ds_max_rtn_f32 v8, v2, v4, v6 +// CHECK: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x06,0x08] + +ds_swizzle_b32 v8, v2 +// CHECK: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08] + +ds_read_b32 v8, v2 +// CHECK: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08] + +ds_read2_b32 v[8:9], v2 +// CHECK: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08] + +ds_read2st64_b32 v[8:9], v2 +// CHECK: ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xe0,0xd8,0x02,0x00,0x00,0x08] + +ds_read_i8 v8, v2 +// CHECK: ds_read_i8 v8, v2 ; encoding: [0x00,0x00,0xe4,0xd8,0x02,0x00,0x00,0x08] + +ds_read_u8 v8, v2 +// CHECK: ds_read_u8 v8, v2 ; encoding: [0x00,0x00,0xe8,0xd8,0x02,0x00,0x00,0x08] + +ds_read_i16 v8, v2 +// CHECK: ds_read_i16 v8, v2 ; encoding: [0x00,0x00,0xec,0xd8,0x02,0x00,0x00,0x08] + +ds_read_u16 v8, v2 +// CHECK: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08] + +ds_consume v8 +// CHECK: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08] + +ds_append v8 +// CHECK: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08] + +ds_ordered_count v8, v2 gds +// CHECK: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08] + +ds_add_u64 v2, v[4:5] +// CHECK: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00] + +ds_sub_u64 v2, v[4:5] +// CHECK: ds_sub_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x04,0xd9,0x02,0x04,0x00,0x00] + +ds_rsub_u64 v2, v[4:5] +// CHECK: ds_rsub_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x08,0xd9,0x02,0x04,0x00,0x00] + +ds_inc_u64 v2, v[4:5] +// CHECK: ds_inc_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x0c,0xd9,0x02,0x04,0x00,0x00] + +ds_dec_u64 v2, v[4:5] +// CHECK: ds_dec_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x10,0xd9,0x02,0x04,0x00,0x00] + +ds_min_i64 v2, v[4:5] +// CHECK: ds_min_i64 v2, v[4:5] ; encoding: [0x00,0x00,0x14,0xd9,0x02,0x04,0x00,0x00] + +ds_max_i64 v2, v[4:5] +// CHECK: ds_max_i64 v2, v[4:5] ; encoding: [0x00,0x00,0x18,0xd9,0x02,0x04,0x00,0x00] + +ds_min_u64 v2, v[4:5] +// CHECK: ds_min_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x1c,0xd9,0x02,0x04,0x00,0x00] + +ds_max_u64 v2, v[4:5] +// CHECK: ds_max_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x20,0xd9,0x02,0x04,0x00,0x00] + +ds_and_b64 v2, v[4:5] +// CHECK: ds_and_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x24,0xd9,0x02,0x04,0x00,0x00] + +ds_or_b64 v2, v[4:5] +// CHECK: ds_or_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x28,0xd9,0x02,0x04,0x00,0x00] + +ds_xor_b64 v2, v[4:5] +// CHECK: ds_xor_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x2c,0xd9,0x02,0x04,0x00,0x00] + +ds_mskor_b64 v2, v[4:5], v[6:7] +// CHECK: ds_mskor_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x30,0xd9,0x02,0x04,0x06,0x00] + +ds_write_b64 v2, v[4:5] +// CHECK: ds_write_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x34,0xd9,0x02,0x04,0x00,0x00] + +ds_write2_b64 v2, v[4:5], v[6:7] +// CHECK: ds_write2_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x38,0xd9,0x02,0x04,0x06,0x00] + +ds_write2st64_b64 v2, v[4:5], v[6:7] +// CHECK: ds_write2st64_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x3c,0xd9,0x02,0x04,0x06,0x00] + +ds_cmpst_b64 v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x40,0xd9,0x02,0x04,0x06,0x00] + +ds_cmpst_f64 v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_f64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x44,0xd9,0x02,0x04,0x06,0x00] + +ds_min_f64 v2, v[4:5] +// CHECK: ds_min_f64 v2, v[4:5] ; encoding: [0x00,0x00,0x48,0xd9,0x02,0x04,0x00,0x00] + +ds_max_f64 v2, v[4:5] +// CHECK: ds_max_f64 v2, v[4:5] ; encoding: [0x00,0x00,0x4c,0xd9,0x02,0x04,0x00,0x00] + +ds_add_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_add_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x80,0xd9,0x02,0x04,0x00,0x08] + +ds_sub_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_sub_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x84,0xd9,0x02,0x04,0x00,0x08] + +ds_rsub_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_rsub_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x88,0xd9,0x02,0x04,0x00,0x08] + +ds_inc_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_inc_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x8c,0xd9,0x02,0x04,0x00,0x08] + +ds_dec_rtn_u64 v[8:9] v2, v[4:5] +// CHECK: ds_dec_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x90,0xd9,0x02,0x04,0x00,0x08] + +ds_min_rtn_i64 v[8:9], v2, v[4:5] +// CHECK: ds_min_rtn_i64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x94,0xd9,0x02,0x04,0x00,0x08] + +ds_max_rtn_i64 v[8:9], v2, v[4:5] +// CHECK: ds_max_rtn_i64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x98,0xd9,0x02,0x04,0x00,0x08] + +ds_min_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_min_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x9c,0xd9,0x02,0x04,0x00,0x08] + +ds_max_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_max_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa0,0xd9,0x02,0x04,0x00,0x08] + +ds_and_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_and_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa4,0xd9,0x02,0x04,0x00,0x08] + +ds_or_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_or_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa8,0xd9,0x02,0x04,0x00,0x08] + +ds_xor_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_xor_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xac,0xd9,0x02,0x04,0x00,0x08] + +ds_mskor_rtn_b64 v[8:9], v2, v[4:5], v[6:7] +// CHECK: ds_mskor_rtn_b64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xb0,0xd9,0x02,0x04,0x06,0x08] + +ds_wrxchg_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_wrxchg_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xb4,0xd9,0x02,0x04,0x00,0x08] + +ds_wrxchg2_rtn_b64 v[8:11], v2, v[4:5], v[6:7] +// CHECK: ds_wrxchg2_rtn_b64 v[8:11], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xb8,0xd9,0x02,0x04,0x06,0x08] + +ds_wrxchg2st64_rtn_b64 v[8:11], v2, v[4:5], v[6:7] +// CHECK: ds_wrxchg2st64_rtn_b64 v[8:11], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xbc,0xd9,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_b64 v[8:9], v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_rtn_b64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xc0,0xd9,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_f64 v[8:9], v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_rtn_f64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xc4,0xd9,0x02,0x04,0x06,0x08] + +ds_min_rtn_f64 v[8:9], v2, v[4:5] +// CHECK: ds_min_rtn_f64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xc8,0xd9,0x02,0x04,0x00,0x08] + +ds_max_rtn_f64 v[8:9], v2, v[4:5] +// CHECK: ds_max_rtn_f64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xcc,0xd9,0x02,0x04,0x00,0x08] + +ds_read_b64 v[8:9], v2 +// CHECK: ds_read_b64 v[8:9], v2 ; encoding: [0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x08] + +ds_read2_b64 v[8:11], v2 +// CHECK: ds_read2_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xdc,0xd9,0x02,0x00,0x00,0x08] + +ds_read2st64_b64 v[8:11], v2 +// CHECK: ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xe0,0xd9,0x02,0x00,0x00,0x08] diff --git a/test/MC/R600/mubuf.s b/test/MC/R600/mubuf.s new file mode 100644 index 0000000..78d365a --- /dev/null +++ b/test/MC/R600/mubuf.s @@ -0,0 +1,352 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Test for different operand combinations +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// load - immediate offset only +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, s[4:7], s1 +// CHECK: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 glc +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 slc +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x41,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 tfe +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x81,0x01] + +buffer_load_dword v1, s[4:7], s1 tfe glc +// CHECK: buffer_load_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x30,0xe0,0x00,0x01,0x81,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01] + +buffer_load_dword v1, s[4:7], s1 glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - vgpr offset +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v2, s[4:7], s1 offen +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen tfe glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - vgpr index +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v2, s[4:7], s1 idxen +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen tfe glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - vgpr index and offset +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - addr64 +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - immediate offset only +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, s[4:7], s1 +// CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 glc +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 slc +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x41,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 tfe +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01] + +buffer_store_dword v1, s[4:7], s1 tfe glc +// CHECK: buffer_store_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01] + +buffer_store_dword v1, s[4:7], s1 glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - vgpr offset +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v2, s[4:7], s1 offen +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen tfe glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - vgpr index +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v2, s[4:7], s1 idxen +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen tfe glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - vgpr index and offset +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - addr64 +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +buffer_load_format_x v1, s[4:7], s1 +// CHECK: buffer_load_format_x v1, s[4:7], s1 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_format_xy v[1:2], s[4:7], s1 +// CHECK: buffer_load_format_xy v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x04,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_format_xyz v[1:3], s[4:7], s1 +// CHECK: buffer_load_format_xyz v[1:3], s[4:7], s1 ; encoding: [0x00,0x00,0x08,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_format_xyzw v[1:4], s[4:7], s1 +// CHECK: buffer_load_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x0c,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_x v1, s[4:7], s1 +// CHECK: buffer_store_format_x v1, s[4:7], s1 ; encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_xy v[1:2], s[4:7], s1 +// CHECK: buffer_store_format_xy v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x14,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_xyz v[1:3], s[4:7], s1 +// CHECK: buffer_store_format_xyz v[1:3], s[4:7], s1 ; encoding: [0x00,0x00,0x18,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_xyzw v[1:4], s[4:7], s1 +// CHECK: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_ubyte v1, s[4:7], s1 +// CHECK: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_sbyte v1, s[4:7], s1 +// CHECK: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_ushort v1, s[4:7], s1 +// CHECK: buffer_load_ushort v1, s[4:7], s1 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_sshort v1, s[4:7], s1 +// CHECK: buffer_load_sshort v1, s[4:7], s1 ; encoding: [0x00,0x00,0x2c,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 +// CHECK: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dwordx2 v[1:2], s[4:7], s1 +// CHECK: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dwordx4 v[1:4], s[4:7], s1 +// CHECK: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_byte v1, s[4:7], s1 +// CHECK: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_short v1, s[4:7], s1 +// CHECK: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1 s[4:7], s1 +// CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dwordx2 v[1:2], s[4:7], s1 +// CHECK: buffer_store_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x74,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dwordx4 v[1:4], s[4:7], s1 +// CHECK: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x01,0x01] + +// TODO: Atomics diff --git a/test/MC/R600/smrd.s b/test/MC/R600/smrd.s new file mode 100644 index 0000000..b67abf7 --- /dev/null +++ b/test/MC/R600/smrd.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +s_load_dword s1, s[2:3], 1 +// CHECK: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0] + +s_load_dword s1, s[2:3], s4 +// CHECK: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0] + +s_load_dwordx2 s[2:3], s[2:3], 1 +// CHECK: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0] + +s_load_dwordx2 s[2:3], s[2:3], s4 +// CHECK: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0] + +s_load_dwordx4 s[4:7], s[2:3], 1 +// CHECK: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0] + +s_load_dwordx4 s[4:7], s[2:3], s4 +// CHECK: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0] + +s_load_dwordx8 s[8:15], s[2:3], 1 +// CHECK: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0] + +s_load_dwordx8 s[8:15], s[2:3], s4 +// CHECK: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0] + +s_load_dwordx16 s[16:31], s[2:3], 1 +// CHECK: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1] + +s_load_dwordx16 s[16:31], s[2:3], s4 +// CHECK: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1] diff --git a/test/MC/R600/sop1-err.s b/test/MC/R600/sop1-err.s new file mode 100644 index 0000000..f892356 --- /dev/null +++ b/test/MC/R600/sop1-err.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s + +s_mov_b32 v1, s2 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s1, v0 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s[1:2], s0 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s0, s[1:2] +// CHECK: error: invalid operand for instruction + +s_mov_b32 s220, s0 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s0, s220 +// CHECK: error: invalid operand for instruction + +s_mov_b64 s1, s[0:1] +// CHECK: error: invalid operand for instruction + +s_mov_b64 s[0:1], s1 +// CHECK: error: invalid operand for instruction + +// Immediate greater than 32-bits +s_mov_b32 s1, 0xfffffffff +// CHECK: error: invalid immediate: only 32-bit values are legal + +// Immediate greater than 32-bits +s_mov_b64 s[0:1], 0xfffffffff +// CHECK: error: invalid immediate: only 32-bit values are legal + +// Out of range register +s_mov_b32 s diff --git a/test/MC/R600/sop1.s b/test/MC/R600/sop1.s new file mode 100644 index 0000000..92ca73f --- /dev/null +++ b/test/MC/R600/sop1.s @@ -0,0 +1,177 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +s_mov_b32 s1, s2 +// CHECK: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe] + +s_mov_b32 s1, 1 +// CHECK: s_mov_b32 s1, 1 ; encoding: [0x81,0x03,0x81,0xbe] + +s_mov_b32 s1, 100 +// CHECK: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x03,0x81,0xbe,0x64,0x00,0x00,0x00] + +s_mov_b64 s[2:3], s[4:5] +// CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe] + +s_mov_b64 s[2:3], 0xffffffffffffffff +// CHECK: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x04,0x82,0xbe] + +s_cmov_b32 s1, 200 +// CHECK: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00] + +s_cmov_b32 s1, 1.0 +// CHECK: s_cmov_b32 s1, 1.0 ; encoding: [0xf2,0x05,0x81,0xbe] + +//s_cmov_b64 s[2:3], 1.0 +//CHECK-FIXME: s_cmov_b64 s[2:3], 1.0 ; encoding: [0xf2,0x05,0x82,0xb3] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +s_mov_b32 s1, s2 +// CHECK: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe] + +s_mov_b64 s[2:3], s[4:5] +// CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe] + +s_cmov_b32 s1, s2 +// CHECK: s_cmov_b32 s1, s2 ; encoding: [0x02,0x05,0x81,0xbe] + +s_cmov_b64 s[2:3], s[4:5] +// CHECK: s_cmov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x06,0x82,0xbe] + +s_not_b32 s1, s2 +// CHECK: s_not_b32 s1, s2 ; encoding: [0x02,0x07,0x81,0xbe] + +s_not_b64 s[2:3], s[4:5] +// CHECK: s_not_b64 s[2:3], s[4:5] ; encoding: [0x04,0x08,0x82,0xbe] + +s_wqm_b32 s1, s2 +// CHECK: s_wqm_b32 s1, s2 ; encoding: [0x02,0x09,0x81,0xbe] + +s_wqm_b64 s[2:3], s[4:5] +// CHECK: s_wqm_b64 s[2:3], s[4:5] ; encoding: [0x04,0x0a,0x82,0xbe] + +s_brev_b32 s1, s2 +// CHECK: s_brev_b32 s1, s2 ; encoding: [0x02,0x0b,0x81,0xbe] + +s_brev_b64 s[2:3], s[4:5] +// CHECK: s_brev_b64 s[2:3], s[4:5] ; encoding: [0x04,0x0c,0x82,0xbe] + +s_bcnt0_i32_b32 s1, s2 +// CHECK: s_bcnt0_i32_b32 s1, s2 ; encoding: [0x02,0x0d,0x81,0xbe] + +s_bcnt0_i32_b64 s1, s[2:3] +// CHECK: s_bcnt0_i32_b64 s1, s[2:3] ; encoding: [0x02,0x0e,0x81,0xbe] + +s_bcnt1_i32_b32 s1, s2 +// CHECK: s_bcnt1_i32_b32 s1, s2 ; encoding: [0x02,0x0f,0x81,0xbe] + +s_bcnt1_i32_b64 s1, s[2:3] +// CHECK: s_bcnt1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x10,0x81,0xbe] + +s_ff0_i32_b32 s1, s2 +// CHECK: s_ff0_i32_b32 s1, s2 ; encoding: [0x02,0x11,0x81,0xbe] + +s_ff0_i32_b64 s1, s[2:3] +// CHECK: s_ff0_i32_b64 s1, s[2:3] ; encoding: [0x02,0x12,0x81,0xbe] + +s_ff1_i32_b32 s1, s2 +// CHECK: s_ff1_i32_b32 s1, s2 ; encoding: [0x02,0x13,0x81,0xbe] + +s_ff1_i32_b64 s1, s[2:3] +// CHECK: s_ff1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x14,0x81,0xbe] + +s_flbit_i32_b32 s1, s2 +// CHECK: s_flbit_i32_b32 s1, s2 ; encoding: [0x02,0x15,0x81,0xbe] + +s_flbit_i32_b64 s1, s[2:3] +// CHECK: s_flbit_i32_b64 s1, s[2:3] ; encoding: [0x02,0x16,0x81,0xbe] + +s_flbit_i32 s1, s2 +// CHECK: s_flbit_i32 s1, s2 ; encoding: [0x02,0x17,0x81,0xbe] + +s_flbit_i32_i64 s1, s[2:3] +// CHECK: s_flbit_i32_i64 s1, s[2:3] ; encoding: [0x02,0x18,0x81,0xbe] + +s_sext_i32_i8 s1, s2 +// CHECK: s_sext_i32_i8 s1, s2 ; encoding: [0x02,0x19,0x81,0xbe] + +s_sext_i32_i16 s1, s2 +// CHECK: s_sext_i32_i16 s1, s2 ; encoding: [0x02,0x1a,0x81,0xbe] + +s_bitset0_b32 s1, s2 +// CHECK: s_bitset0_b32 s1, s2 ; encoding: [0x02,0x1b,0x81,0xbe] + +s_bitset0_b64 s[2:3], s[4:5] +// CHECK: s_bitset0_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1c,0x82,0xbe] + +s_bitset1_b32 s1, s2 +// CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe] + +s_bitset1_b64 s[2:3], s[4:5] +// CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe] + +s_getpc_b64 s[2:3] +// CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe] + +s_setpc_b64 s[2:3], s[4:5] +// CHECK: s_setpc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x20,0x82,0xbe] + +s_swappc_b64 s[2:3], s[4:5] +// CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe] + +s_rfe_b64 s[2:3], s[4:5] +// CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe] + +s_and_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x24,0x82,0xbe] + +s_or_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_or_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x25,0x82,0xbe] + +s_xor_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_xor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x26,0x82,0xbe] + +s_andn2_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_andn2_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x27,0x82,0xbe] + +s_orn2_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_orn2_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x28,0x82,0xbe] + +s_nand_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_nand_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x29,0x82,0xbe] + +s_nor_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_nor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2a,0x82,0xbe] + +s_xnor_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_xnor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2b,0x82,0xbe] + +s_quadmask_b32 s1, s2 +// CHECK: s_quadmask_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe] + +s_quadmask_b64 s[2:3], s[4:5] +// CHECK: s_quadmask_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe] + +s_movrels_b32 s1, s2 +// CHECK: s_movrels_b32 s1, s2 ; encoding: [0x02,0x2e,0x81,0xbe] + +s_movrels_b64 s[2:3], s[4:5] +// CHECK: s_movrels_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2f,0x82,0xbe] + +s_movreld_b32 s1, s2 +// CHECK: s_movreld_b32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe] + +s_movreld_b64 s[2:3], s[4:5] +// CHECK: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe] + +s_cbranch_join s[4:5] +// CHECK: s_cbranch_join s[4:5] ; encoding: [0x04,0x32,0x80,0xbe] + +s_abs_i32 s1, s2 +// CHECK: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe] + +s_mov_fed_b32 s1, s2 +// CHECK: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe] diff --git a/test/MC/R600/sop2.s b/test/MC/R600/sop2.s new file mode 100644 index 0000000..9a7a1c0 --- /dev/null +++ b/test/MC/R600/sop2.s @@ -0,0 +1,131 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +// CHECK: s_add_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x80] +s_add_u32 s1, s2, s3 + +// CHECK: s_sub_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x80] +s_sub_u32 s1, s2, s3 + +// CHECK: s_add_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x81] +s_add_i32 s1, s2, s3 + +// CHECK: s_sub_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x81] +s_sub_i32 s1, s2, s3 + +// CHECK: s_addc_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x82] +s_addc_u32 s1, s2, s3 + +// CHECK: s_subb_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x82] +s_subb_u32 s1, s2, s3 + +// CHECK: s_min_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x83] +s_min_i32 s1, s2, s3 + +// CHECK: s_min_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x83] +s_min_u32 s1, s2, s3 + +// CHECK: s_max_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x84] +s_max_i32 s1, s2, s3 + +// CHECK: s_max_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x84] +s_max_u32 s1, s2, s3 + +// CHECK: s_cselect_b32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x85] +s_cselect_b32 s1, s2, s3 + +// CHECK: s_cselect_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x85] +s_cselect_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87] +s_and_b32 s2, s4, s6 + +// CHECK: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87] +s_and_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x88] +s_or_b32 s2, s4, s6 + +// CHECK: s_or_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x88] +s_or_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_xor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89] +s_xor_b32 s2, s4, s6 + +// CHECK: s_xor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x89] +s_xor_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8a] +s_andn2_b32 s2, s4, s6 + +// CHECK: s_andn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8a] +s_andn2_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_orn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8b] +s_orn2_b32 s2, s4, s6 + +// CHECK: s_orn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8b] +s_orn2_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_nand_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8c] +s_nand_b32 s2, s4, s6 + +// CHECK: s_nand_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8c] +s_nand_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_nor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8d] +s_nor_b32 s2, s4, s6 + +// CHECK: s_nor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8d] +s_nor_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_xnor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8e] +s_xnor_b32 s2, s4, s6 + +// CHECK: s_xnor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8e] +s_xnor_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_lshl_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8f] +s_lshl_b32 s2, s4, s6 + +// CHECK: s_lshl_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x8f] +s_lshl_b64 s[2:3], s[4:5], s6 + +// CHECK: s_lshr_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90] +s_lshr_b32 s2, s4, s6 + +// CHECK: s_lshr_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x90] +s_lshr_b64 s[2:3], s[4:5], s6 + +// CHECK: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x91] +s_ashr_i32 s2, s4, s6 + +// CHECK: s_ashr_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x91] +s_ashr_i64 s[2:3], s[4:5], s6 + +// CHECK: s_bfm_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92] +s_bfm_b32 s2, s4, s6 + +// CHECK: s_bfm_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x92] +s_bfm_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93] +s_mul_i32 s2, s4, s6 + +// CHECK: s_bfe_u32 s2, s4, s6 ; encoding: [0x04,0x06,0x82,0x93] +s_bfe_u32 s2, s4, s6 + +// CHECK: s_bfe_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x94] +s_bfe_i32 s2, s4, s6 + +// CHECK: s_bfe_u64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x94] +s_bfe_u64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_bfe_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x02,0x95] +s_bfe_i64 s[2:3], s[4:5], s6 + +// CHECK: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x95] +s_cbranch_g_fork s[4:5], s[6:7] + +// CHECK: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96] +s_absdiff_i32 s2, s4, s6 diff --git a/test/MC/R600/sopc.s b/test/MC/R600/sopc.s new file mode 100644 index 0000000..0899c1a --- /dev/null +++ b/test/MC/R600/sopc.s @@ -0,0 +1,9 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +s_cmp_eq_i32 s1, s2 +// CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf] diff --git a/test/MC/R600/sopk.s b/test/MC/R600/sopk.s new file mode 100644 index 0000000..6c27aac --- /dev/null +++ b/test/MC/R600/sopk.s @@ -0,0 +1,66 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +s_movk_i32 s2, 0x6 +// CHECK: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0] + +s_cmovk_i32 s2, 0x6 +// CHECK: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1] + +s_cmpk_eq_i32 s2, 0x6 +// CHECK: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1] + +s_cmpk_lg_i32 s2, 0x6 +// CHECK: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2] + +s_cmpk_gt_i32 s2, 0x6 +// CHECK: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2] + +s_cmpk_ge_i32 s2, 0x6 +// CHECK: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3] + +s_cmpk_lt_i32 s2, 0x6 +// CHECK: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3] + +s_cmpk_le_i32 s2, 0x6 +// CHECK: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4] + +s_cmpk_eq_u32 s2, 0x6 +// CHECK: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4] + +s_cmpk_lg_u32 s2, 0x6 +// CHECK: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5] + +s_cmpk_gt_u32 s2, 0x6 +// CHECK: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5] + +s_cmpk_ge_u32 s2, 0x6 +// CHECK: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6] + +s_cmpk_lt_u32 s2, 0x6 +// CHECK: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6] + +s_cmpk_le_u32 s2, 0x6 +// CHECK: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7] + +s_addk_i32 s2, 0x6 +// CHECK: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7] + +s_mulk_i32 s2, 0x6 +// CHECK: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8] + +s_cbranch_i_fork s[2:3], 0x6 +// CHECK: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8] + +s_getreg_b32 s2, 0x6 +// CHECK: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] + +s_setreg_b32 s2, 0x6 +// CHECK: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9] + +s_setreg_imm32_b32 0xff, 0x6 +// CHECK: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] diff --git a/test/MC/R600/sopp.s b/test/MC/R600/sopp.s index 0f186b1..b072c16 100644 --- a/test/MC/R600/sopp.s +++ b/test/MC/R600/sopp.s @@ -1,4 +1,16 @@ -// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Edge Cases +//===----------------------------------------------------------------------===// + +s_nop 0 // CHECK: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf] +s_nop 0xffff // CHECK: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// s_nop 1 // CHECK: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf] s_endpgm // CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] diff --git a/test/MC/R600/vop1.s b/test/MC/R600/vop1.s new file mode 100644 index 0000000..9c9a6b2 --- /dev/null +++ b/test/MC/R600/vop1.s @@ -0,0 +1,182 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +// CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] +v_nop + +// CHECK: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e] +v_mov_b32 v1, v2 + +// CHECK: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e] +v_readfirstlane_b32 s1, v2 + +// CHECK: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e] +v_cvt_i32_f64 v1, v[2:3] + +// CHECK: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e] +v_cvt_f64_i32 v[1:2], v2 + +// CHECK: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e] +v_cvt_f32_i32 v1, v2 + +// CHECK: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e] +v_cvt_f32_u32 v1, v2 + +// CHECK: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e +v_cvt_u32_f32 v1, v2 + +// CHECK: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e] +v_cvt_i32_f32 v1, v2 + +// CHECK: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e] +v_mov_fed_b32 v1, v2 + +// CHECK: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e] +v_cvt_f16_f32 v1, v2 + +// CHECK: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e] +v_cvt_f32_f16 v1, v2 + +// CHECK: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e] +v_cvt_rpi_i32_f32 v1, v2 + +// CHECK: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e] +v_cvt_flr_i32_f32 v1, v2 + +// CHECK: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e] +v_cvt_off_f32_i4_e32 v1, v2 + +// CHECK: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e] +v_cvt_f32_f64 v1, v[2:3] + +// CHECK: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e] +v_cvt_f64_f32 v[1:2], v2 + +// CHECK: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e] +v_cvt_f32_ubyte0 v1, v2 + +// CHECK: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e] +v_cvt_f32_ubyte1_e32 v1, v2 + +// CHECK: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e] +v_cvt_f32_ubyte2 v1, v2 + +// CHECK: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e] +v_cvt_f32_ubyte3 v1, v2 + +// CHECK: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e] +v_cvt_u32_f64 v1, v[2:3] + +// CHECK: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e] +v_cvt_f64_u32 v[1:2], v2 + +// CHECK: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e] +v_fract_f32 v1, v2 + +// CHECK: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e] +v_trunc_f32 v1, v2 + +// CHECK: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e] +v_ceil_f32 v1, v2 + +// CHECK: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e] +v_rndne_f32 v1, v2 + +// CHECK: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e] +v_floor_f32_e32 v1, v2 + +// CHECK: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e] +v_exp_f32 v1, v2 + +// CHECK: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e] +v_log_clamp_f32 v1, v2 + +// CHECK: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e] +v_log_f32 v1, v2 + +// CHECK: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e] +v_rcp_clamp_f32 v1, v2 + +// CHECK: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e] +v_rcp_legacy_f32 v1, v2 + +// CHECK: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e] +v_rcp_f32 v1, v2 + +// CHECK: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e] +v_rcp_iflag_f32 v1, v2 + +// CHECK: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e] +v_rsq_clamp_f32 v1, v2 + +// CHECK: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e] +v_rsq_legacy_f32 v1, v2 + +// CHECK: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e] +v_rsq_f32_e32 v1, v2 + +// CHECK: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e] +v_rcp_f64 v[1:2], v[2:3] + +// CHECK: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e] +v_rcp_clamp_f64 v[1:2], v[2:3] + +// CHECK: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e] +v_rsq_f64 v[1:2], v[2:3] + +// CHECK: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e] +v_rsq_clamp_f64 v[1:2], v[2:3] + +// CHECK: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e] +v_sqrt_f32 v1, v2 + +// CHECK: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e] +v_sqrt_f64 v[1:2], v[2:3] + +// CHECK: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e] +v_sin_f32 v1, v2 + +// CHECK: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e] +v_cos_f32 v1, v2 + +// CHECK: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e] +v_not_b32 v1, v2 + +// CHECK: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] +v_bfrev_b32 v1, v2 + +// CHECK: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e] +v_ffbh_u32 v1, v2 + +// CHECK: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e] +v_ffbl_b32 v1, v2 + +// CHECK: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e] +v_ffbh_i32_e32 v1, v2 + +// CHECK: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e] +v_frexp_exp_i32_f64 v1, v[2:3] + +// CHECK: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e] +v_frexp_mant_f64 v[1:2], v[2:3] + +// CHECK: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e] +v_fract_f64 v[1:2], v[2:3] + +// CHECK: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e] +v_frexp_exp_i32_f32 v1, v2 + +// CHECK: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e] +v_frexp_mant_f32 v1, v2 + +// CHECK: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e] +v_clrexcp + +// CHECK: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e] +v_movreld_b32 v1, v2 + +// CHECK: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e] +v_movrels_b32 v1, v2 + +// CHECK: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e] +v_movrelsd_b32 v1, v2 diff --git a/test/MC/R600/vop2-err.s b/test/MC/R600/vop2-err.s new file mode 100644 index 0000000..a113100 --- /dev/null +++ b/test/MC/R600/vop2-err.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s + +//===----------------------------------------------------------------------===// +// Generic checks +//===----------------------------------------------------------------------===// + +v_mul_i32_i24 v1, v2, 100 +// CHECK: error: invalid operand for instruction + +//===----------------------------------------------------------------------===// +// _e32 checks +//===----------------------------------------------------------------------===// + +// Immediate src1 +v_mul_i32_i24_e32 v1, v2, 100 +// CHECK: error: invalid operand for instruction + +// sgpr src1 +v_mul_i32_i24_e32 v1, v2, s3 +// CHECK: error: invalid operand for instruction + +//===----------------------------------------------------------------------===// +// _e64 checks +//===----------------------------------------------------------------------===// + +// Immediate src0 +v_mul_i32_i24_e64 v1, 100, v3 +// CHECK: error: invalid operand for instruction + +// Immediate src1 +v_mul_i32_i24_e64 v1, v2, 100 +// CHECK: error: invalid operand for instruction + +// TODO: Constant bus restrictions diff --git a/test/MC/R600/vop2.s b/test/MC/R600/vop2.s new file mode 100644 index 0000000..6780088 --- /dev/null +++ b/test/MC/R600/vop2.s @@ -0,0 +1,242 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Generic Checks for floating-point instructions (These have modifiers). +//===----------------------------------------------------------------------===// + +// TODO: 64-bit encoding of instructions with modifiers + +// _e32 suffix +// CHECK: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06] +v_add_f32_e32 v1, v2, v3 + +// src0 inline immediate +// CHECK: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06] +v_add_f32 v1, 1.0, v3 + +// src0 negative inline immediate +// CHECK: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06] +v_add_f32 v1, -1.0, v3 + +// src0 literal +// CHECK: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42] +v_add_f32 v1, 100.0, v3 + +// src0 negative literal +// CHECK: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2] +v_add_f32 v1, -100.0, v3 + +//===----------------------------------------------------------------------===// +// Generic Checks for integer instructions (These don't have modifiers). +//===----------------------------------------------------------------------===// + +// _e32 suffix +// CHECK: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12] +v_mul_i32_i24_e32 v1, v2, v3 + +// _e64 suffix +// CHECK: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00] +v_mul_i32_i24_e64 v1, v2, v3 + +// src0 inline +// CHECK: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12] +v_mul_i32_i24 v1, 3, v3 + +// src0 negative inline +// CHECK: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12] +v_mul_i32_i24 v1, -3, v3 + +// src1 inline +// CHECK: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00] +v_mul_i32_i24 v1, v2, 3 + +// src1 negative inline +// CHECK: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00] +v_mul_i32_i24 v1, v2, -3 + +// src0 literal +// CHECK: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00] +v_mul_i32_i24 v1, 100, v3 + +// src1 negative literal +// CHECK: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff] +v_mul_i32_i24 v1, -100, v3 + +//===----------------------------------------------------------------------===// +// Checks for legal operands +//===----------------------------------------------------------------------===// + +// src0 sgpr +// CHECK: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12] +v_mul_i32_i24 v1, s2, v3 + +// src1 sgpr +// CHECK: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00] +v_mul_i32_i24 v1, v2, s3 + +// src0, src1 same sgpr +// CHECK: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00] +v_mul_i32_i24 v1, s2, s2 + +// src0 sgpr, src1 inline +// CHECK: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00] +v_mul_i32_i24 v1, s2, 3 + +// src0 inline src1 sgpr +// CHECK: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00] +v_mul_i32_i24 v1, 3, s3 + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// CHECK: v_cndmask_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x00] +v_cndmask_b32 v1, v2, v3 + +// CHECK: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02] +v_readlane_b32 s1, v2, s3 + +// CHECK: v_writelane_b32 v1, s2, s3 ; encoding: [0x02,0x06,0x02,0x04] +v_writelane_b32 v1, s2, s3 + +// CHECK: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06] +v_add_f32 v1, v2, v3 + +// CHECK: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08] +v_sub_f32 v1, v2, v3 + +// CHECK: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a] +v_subrev_f32 v1, v2, v3 + +// CHECK: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c] +v_mac_legacy_f32 v1, v2, v3 + +// CHECK: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e] +v_mul_legacy_f32_e32 v1, v2, v3 + +// CHECK: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10] +v_mul_f32 v1, v2, v3 + +// CHECK: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12] +v_mul_i32_i24 v1, v2, v3 + +// CHECK: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14] +v_mul_hi_i32_i24 v1, v2, v3 + +// CHECK: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16] +v_mul_u32_u24 v1, v2, v3 + +// CHECK: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18] +v_mul_hi_u32_u24 v1, v2, v3 + +// CHECK: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a] +v_min_legacy_f32_e32 v1, v2, v3 + +// CHECK: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c] +v_max_legacy_f32 v1, v2, v3 + +// CHECK: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e] +v_min_f32_e32 v1, v2, v3 + +// CHECK: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20] +v_max_f32 v1, v2 v3 + +// CHECK: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22] +v_min_i32 v1, v2, v3 + +// CHECK: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24] +v_max_i32 v1, v2, v3 + +// CHECK: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26] +v_min_u32 v1, v2, v3 + +// CHECK: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28] +v_max_u32 v1, v2, v3 + +// CHECK: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a] +v_lshr_b32 v1, v2, v3 + +// CHECK: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c] +v_lshrrev_b32 v1, v2, v3 + +// CHECK: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e] +v_ashr_i32 v1, v2, v3 + +// CHECK: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30] +v_ashrrev_i32 v1, v2, v3 + +// CHECK: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32] +v_lshl_b32_e32 v1, v2, v3 + +// CHECK: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34] +v_lshlrev_b32 v1, v2, v3 + +// CHECK: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36] +v_and_b32 v1, v2, v3 + +// CHECK: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38] +v_or_b32 v1, v2, v3 + +// CHECK: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a] +v_xor_b32 v1, v2, v3 + +// CHECK: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c] +v_bfm_b32 v1, v2, v3 + +// CHECK: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e] +v_mac_f32 v1, v2, v3 + +// CHECK: v_madmk_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42] +v_madmk_f32 v1, v2, v3, 64.0 + +// CHECK: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42] +v_madak_f32 v1, v2, v3, 64.0 + +// CHECK: v_bcnt_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44] +v_bcnt_u32_b32 v1, v2, v3 + +// CHECK: v_mbcnt_lo_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46] +v_mbcnt_lo_u32_b32 v1, v2, v3 + +// CHECK: v_mbcnt_hi_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x48] +v_mbcnt_hi_u32_b32_e32 v1, v2, v3 + +// CHECK: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a] +v_add_i32 v1, v2, v3 + +// CHECK: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] +v_sub_i32_e32 v1, v2, v3 + +// CHECK: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] +v_subrev_i32 v1, v2, v3 + +// CHECK : v_addc_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50] +v_addc_u32 v1, v2, v3 + +// CHECK: v_subb_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52] +v_subb_u32 v1, v2, v3 + +// CHECK: v_subbrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54] +v_subbrev_u32 v1, v2, v3 + +// CHECK: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] +v_ldexp_f32 v1, v2, v3 + +// CHECK: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58] +v_cvt_pkaccum_u8_f32 v1, v2, v3 + +// CHECK: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a] +v_cvt_pknorm_i16_f32 v1, v2, v3 + +// CHECK: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c] +v_cvt_pknorm_u16_f32 v1, v2, v3 + +// CHECK: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e] +v_cvt_pkrtz_f16_f32 v1, v2, v3 + +// CHECK: v_cvt_pk_u16_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60] +v_cvt_pk_u16_u32_e32 v1, v2, v3 + +// CHECK: v_cvt_pk_i16_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62] +v_cvt_pk_i16_i32 v1, v2, v3 diff --git a/test/MC/R600/vop3.s b/test/MC/R600/vop3.s new file mode 100644 index 0000000..7d1ba0b --- /dev/null +++ b/test/MC/R600/vop3.s @@ -0,0 +1,138 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// VOPC Instructions +//===----------------------------------------------------------------------===// + +// +// Modifier tests: +// + +v_cmp_lt_f32 s[2:3] -v4, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], -v4, v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x20] + +v_cmp_lt_f32 s[2:3] v4, -v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x40] + +v_cmp_lt_f32 s[2:3] -v4, -v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], -v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x60] + +v_cmp_lt_f32 s[2:3] |v4|, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], |v4|, v6 ; encoding: [0x02,0x01,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3] v4, |v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, |v6| ; encoding: [0x02,0x02,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3] |v4|, |v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], |v4|, |v6| ; encoding: [0x02,0x03,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3] -|v4|, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], -|v4|, v6 ; encoding: [0x02,0x01,0x02,0xd0,0x04,0x0d,0x02,0x20] + +v_cmp_lt_f32 s[2:3] v4, -|v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -|v6| ; encoding: [0x02,0x02,0x02,0xd0,0x04,0x0d,0x02,0x40] + +v_cmp_lt_f32 s[2:3] -|v4|, -|v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], -|v4|, -|v6| ; encoding: [0x02,0x03,0x02,0xd0,0x04,0x0d,0x02,0x60] + +// +// Instruction tests: +// + +v_cmp_f_f32 s[2:3], v4, v6 +// CHECK: v_cmp_f_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x00,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3], v4, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_eq_f32 s[2:3], v4, v6 +// CHECK: v_cmp_eq_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x04,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_le_f32 s[2:3], v4, v6 +// CHECK: v_cmp_le_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x06,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_gt_f32 s[2:3], v4, v6 +// CHECK: v_cmp_gt_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x08,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lg_f32 s[2:3], v4, v6 +// CHECK: v_cmp_lg_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0a,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_ge_f32 s[2:3], v4, v6 +// CHECK: v_cmp_ge_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0c,0xd0,0x04,0x0d,0x02,0x00] + +// TODO: Finish VOPC + +//===----------------------------------------------------------------------===// +// VOP1 Instructions +//===----------------------------------------------------------------------===// + +// +// Modifier tests: +// + +v_fract_f32 v1, -v2 +// CHECK: v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x20] + +v_fract_f32 v1, |v2| +// CHECK: v_fract_f32_e64 v1, |v2| ; encoding: [0x01,0x01,0x40,0xd3,0x02,0x01,0x00,0x00] + +v_fract_f32 v1, -|v2| +// CHECK: v_fract_f32_e64 v1, -|v2| ; encoding: [0x01,0x01,0x40,0xd3,0x02,0x01,0x00,0x20] + +v_fract_f32 v1, v2 clamp +// CHECK: v_fract_f32_e64 v1, v2 clamp ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x00] + +v_fract_f32 v1, v2 mul:2 +// CHECK: v_fract_f32_e64 v1, v2 mul:2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x08] + +v_fract_f32 v1, v2, div:2 clamp +// CHECK: v_fract_f32_e64 v1, v2 clamp div:2 ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x18] + +// TODO: Finish VOP1 + +///===---------------------------------------------------------------------===// +// VOP2 Instructions +///===---------------------------------------------------------------------===// + +// TODO: Modifier tests + +v_cndmask_b32 v1, v3, v5, s[4:5] +// CHECK: v_cndmask_b32_e64 v1, v3, v5, s[4:5] ; encoding: [0x01,0x00,0x00,0xd2,0x03,0x0b,0x12,0x00] + +//TODO: readlane, writelane + +v_add_f32 v1, v3, s5 +// CHECK: v_add_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x06,0xd2,0x03,0x0b,0x00,0x00] + +v_sub_f32 v1, v3, s5 +// CHECK: v_sub_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x08,0xd2,0x03,0x0b,0x00,0x00] + +v_subrev_f32 v1, v3, s5 +// CHECK: v_subrev_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0a,0xd2,0x03,0x0b,0x00,0x00] + +v_mac_legacy_f32 v1, v3, s5 +// CHECK: v_mac_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0c,0xd2,0x03,0x0b,0x00,0x00] + +v_mul_legacy_f32 v1, v3, s5 +// CHECK: v_mul_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0e,0xd2,0x03,0x0b,0x00,0x00] + +v_mul_f32 v1, v3, s5 +// CHECK: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x10,0xd2,0x03,0x0b,0x00,0x00] + +v_mul_i32_i24 v1, v3, s5 +// CHECK: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x12,0xd2,0x03,0x0b,0x00,0x00] + +///===---------------------------------------------------------------------===// +// VOP3 Instructions +///===---------------------------------------------------------------------===// + +// TODO: Modifier tests + +v_mad_legacy_f32 v2, v4, v6, v8 +// CHECK: v_mad_legacy_f32 v2, v4, v6, v8 ; encoding: [0x02,0x00,0x80,0xd2,0x04,0x0d,0x22,0x04] + + + + + diff --git a/test/MC/R600/vopc.s b/test/MC/R600/vopc.s new file mode 100644 index 0000000..f44919a --- /dev/null +++ b/test/MC/R600/vopc.s @@ -0,0 +1,40 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Generic Checks +//===----------------------------------------------------------------------===// + +// src0 sgpr +v_cmp_lt_f32 vcc, s2, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] + +// src0 inline immediate +v_cmp_lt_f32 vcc, 0, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] + +// src0 literal +v_cmp_lt_f32 vcc, 10.0, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] + +// src0, src1 max vgpr +v_cmp_lt_f32 vcc, v255, v255 +// CHECK: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] + +// force 32-bit encoding +v_cmp_lt_f32_e32 vcc, v2, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] + + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +v_cmp_f_f32 vcc, v2, v4 +// CHECK: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] + +v_cmp_lt_f32 vcc, v2, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] + +// TODO: Add tests for the rest of the instructions. + diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s index 47dbe08..1bd70a8 100644 --- a/test/MC/SystemZ/insn-bad-z196.s +++ b/test/MC/SystemZ/insn-bad-z196.s @@ -244,6 +244,11 @@ cxlgbr %f0, 16, %r0, 0 cxlgbr %f2, 0, %r0, 0 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: etnd %r7 + + etnd %r7 + #CHECK: error: invalid operand #CHECK: fidbra %f0, 0, %f0, -1 #CHECK: error: invalid operand @@ -546,6 +551,21 @@ locr %r0,%r0,-1 locr %r0,%r0,16 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: ntstg %r0, 524287(%r1,%r15) + + ntstg %r0, 524287(%r1,%r15) + +#CHECK: error: {{(instruction requires: processor-assist)?}} +#CHECK: ppa %r4, %r6, 7 + + ppa %r4, %r6, 7 + +#CHECK: error: {{(instruction requires: miscellaneous-extensions)?}} +#CHECK: risbgn %r1, %r2, 0, 0, 0 + + risbgn %r1, %r2, 0, 0, 0 + #CHECK: error: invalid operand #CHECK: risbhg %r0,%r0,0,0,-1 #CHECK: error: invalid operand @@ -685,3 +705,24 @@ stocg %r0,-524289,1 stocg %r0,524288,1 stocg %r0,0(%r1,%r2),1 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tabort 4095(%r1) + + tabort 4095(%r1) + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbegin 4095(%r1), 42 + + tbegin 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbeginc 4095(%r1), 42 + + tbeginc 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tend + + tend + diff --git a/test/MC/SystemZ/insn-bad-zEC12.s b/test/MC/SystemZ/insn-bad-zEC12.s new file mode 100644 index 0000000..d96e35d --- /dev/null +++ b/test/MC/SystemZ/insn-bad-zEC12.s @@ -0,0 +1,84 @@ +# For zEC12 only. +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ntstg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ntstg %r0, 524288 + + ntstg %r0, -524289 + ntstg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, 16 + + ppa %r0, %r0, -1 + ppa %r0, %r0, 16 + +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,0,-1 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,0,64 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,-1,0 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,256,0 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,-1,0,0 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,256,0,0 + + risbgn %r0,%r0,0,0,-1 + risbgn %r0,%r0,0,0,64 + risbgn %r0,%r0,0,-1,0 + risbgn %r0,%r0,0,256,0 + risbgn %r0,%r0,-1,0,0 + risbgn %r0,%r0,256,0,0 + +#CHECK: error: invalid operand +#CHECK: tabort -1 +#CHECK: error: invalid operand +#CHECK: tabort 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: tabort 0(%r1,%r2) + + tabort -1 + tabort 4096 + tabort 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: tbegin -1, 0 +#CHECK: error: invalid operand +#CHECK: tbegin 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbegin 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbegin 0, -1 +#CHECK: error: invalid operand +#CHECK: tbegin 0, 65536 + + tbegin -1, 0 + tbegin 4096, 0 + tbegin 0(%r1,%r2), 0 + tbegin 0, -1 + tbegin 0, 65536 + +#CHECK: error: invalid operand +#CHECK: tbeginc -1, 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbeginc 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, -1 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, 65536 + + tbeginc -1, 0 + tbeginc 4096, 0 + tbeginc 0(%r1,%r2), 0 + tbeginc 0, -1 + tbeginc 0, 65536 diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index a08cb34..0410a41 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -2666,6 +2666,11 @@ pfdrl 1, 1 pfdrl 1, 0x100000000 +#CHECK: error: {{(instruction requires: population-count)?}} +#CHECK: popcnt %r0, %r0 + + popcnt %r0, %r0 + #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,-1 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s index db5ecdd..36bea38 100644 --- a/test/MC/SystemZ/insn-good-z196.s +++ b/test/MC/SystemZ/insn-good-z196.s @@ -1021,6 +1021,16 @@ ork %r15,%r0,%r0 ork %r7,%r8,%r9 +#CHECK: popcnt %r0, %r0 # encoding: [0xb9,0xe1,0x00,0x00] +#CHECK: popcnt %r0, %r15 # encoding: [0xb9,0xe1,0x00,0x0f] +#CHECK: popcnt %r15, %r0 # encoding: [0xb9,0xe1,0x00,0xf0] +#CHECK: popcnt %r7, %r8 # encoding: [0xb9,0xe1,0x00,0x78] + + popcnt %r0,%r0 + popcnt %r0,%r15 + popcnt %r15,%r0 + popcnt %r7,%r8 + #CHECK: risbhg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d] #CHECK: risbhg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d] #CHECK: risbhg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d] diff --git a/test/MC/SystemZ/insn-good-zEC12.s b/test/MC/SystemZ/insn-good-zEC12.s new file mode 100644 index 0000000..0610de3 --- /dev/null +++ b/test/MC/SystemZ/insn-good-zEC12.s @@ -0,0 +1,126 @@ +# For zEC12 and above. +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s + +#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00] +#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0] +#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70] + + etnd %r0 + etnd %r15 + etnd %r7 + +#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25] +#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25] +#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25] +#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25] +#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25] +#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25] +#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25] +#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25] + + ntstg %r0, -524288 + ntstg %r0, -1 + ntstg %r0, 0 + ntstg %r0, 1 + ntstg %r0, 524287 + ntstg %r0, 0(%r1) + ntstg %r0, 0(%r15) + ntstg %r0, 524287(%r1,%r15) + ntstg %r0, 524287(%r15,%r1) + ntstg %r15, 0 + +#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00] +#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00] +#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f] +#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46] +#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0] + + ppa %r0, %r0, 0 + ppa %r0, %r0, 15 + ppa %r0, %r15, 0 + ppa %r4, %r6, 7 + ppa %r15, %r0, 0 + +#CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59] +#CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] +#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] +#CHECK: risbgn %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x59] +#CHECK: risbgn %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59] +#CHECK: risbgn %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x59] +#CHECK: risbgn %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x59] + + risbgn %r0,%r0,0,0,0 + risbgn %r0,%r0,0,0,63 + risbgn %r0,%r0,0,255,0 + risbgn %r0,%r0,255,0,0 + risbgn %r0,%r15,0,0,0 + risbgn %r15,%r0,0,0,0 + risbgn %r4,%r5,6,7,8 + +#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00] +#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00] +#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00] +#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff] +#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff] +#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff] + + tabort 0 + tabort 0(%r1) + tabort 0(%r15) + tabort 4095 + tabort 4095(%r1) + tabort 4095(%r15) + +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00] +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01] +#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff] +#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00] +#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff] +#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a] +#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a] +#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a] +#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a] + + tbegin 0, 0 + tbegin 4095, 0 + tbegin 0, 0 + tbegin 0, 1 + tbegin 0, 32767 + tbegin 0, 32768 + tbegin 0, 65535 + tbegin 0(%r1), 42 + tbegin 0(%r15), 42 + tbegin 4095(%r1), 42 + tbegin 4095(%r15), 42 + +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00] +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01] +#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff] +#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00] +#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff] +#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a] +#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a] +#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a] +#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a] + + tbeginc 0, 0 + tbeginc 4095, 0 + tbeginc 0, 0 + tbeginc 0, 1 + tbeginc 0, 32767 + tbeginc 0, 32768 + tbeginc 0, 65535 + tbeginc 0(%r1), 42 + tbeginc 0(%r15), 42 + tbeginc 4095(%r1), 42 + tbeginc 4095(%r15), 42 + +#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00] + + tend diff --git a/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s b/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s index a9a78a7..5ce7880 100644 --- a/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s +++ b/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s @@ -1,4 +1,5 @@ # RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - 2>&1 | FileCheck %s # CHECK: ERROR: Fragment can't be larger than a bundle size diff --git a/test/MC/X86/AlignedBundling/different-sections.s b/test/MC/X86/AlignedBundling/different-sections.s index 3e9fcf3..e121532 100644 --- a/test/MC/X86/AlignedBundling/different-sections.s +++ b/test/MC/X86/AlignedBundling/different-sections.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test two different executable sections with bundling. diff --git a/test/MC/X86/AlignedBundling/labeloffset.s b/test/MC/X86/AlignedBundling/labeloffset.s index 65a0086..5b2efe0 100644 --- a/test/MC/X86/AlignedBundling/labeloffset.s +++ b/test/MC/X86/AlignedBundling/labeloffset.s @@ -2,6 +2,8 @@ # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s # RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \ # RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s +# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \ +# RUN: llvm-objdump -disassemble -no-show-raw-insn -r - | FileCheck %s .bundle_align_mode 5 .text diff --git a/test/MC/X86/AlignedBundling/long-nop-pad.s b/test/MC/X86/AlignedBundling/long-nop-pad.s index 9b1ec11..36e4f4b 100644 --- a/test/MC/X86/AlignedBundling/long-nop-pad.s +++ b/test/MC/X86/AlignedBundling/long-nop-pad.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test that long nops are generated for padding where possible. diff --git a/test/MC/X86/AlignedBundling/nesting.s b/test/MC/X86/AlignedBundling/nesting.s index 8996170..74b8fe9 100644 --- a/test/MC/X86/AlignedBundling/nesting.s +++ b/test/MC/X86/AlignedBundling/nesting.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Will be bundle-aligning to 16 byte boundaries .bundle_align_mode 4 diff --git a/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s b/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s index 6ca4046..158cde8 100644 --- a/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s +++ b/test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test some variations of padding to the end of a bundle. diff --git a/test/MC/X86/AlignedBundling/pad-bundle-groups.s b/test/MC/X86/AlignedBundling/pad-bundle-groups.s index b65ee7a..7a9e30c 100644 --- a/test/MC/X86/AlignedBundling/pad-bundle-groups.s +++ b/test/MC/X86/AlignedBundling/pad-bundle-groups.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test some variations of padding for bundle-locked groups. diff --git a/test/MC/X86/AlignedBundling/relax-at-bundle-end.s b/test/MC/X86/AlignedBundling/relax-at-bundle-end.s index ab4affb..f59ecb0 100644 --- a/test/MC/X86/AlignedBundling/relax-at-bundle-end.s +++ b/test/MC/X86/AlignedBundling/relax-at-bundle-end.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test that an instruction near a bundle end gets properly padded # after it is relaxed. diff --git a/test/MC/X86/AlignedBundling/relax-in-bundle-group.s b/test/MC/X86/AlignedBundling/relax-in-bundle-group.s index 0a99bb5..d076190 100644 --- a/test/MC/X86/AlignedBundling/relax-in-bundle-group.s +++ b/test/MC/X86/AlignedBundling/relax-in-bundle-group.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ # RUN: | llvm-objdump -disassemble - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble - | FileCheck %s # Test that instructions inside bundle-locked groups are relaxed even if their # fixup is short enough not to warrant relaxation on its own. diff --git a/test/MC/X86/AlignedBundling/single-inst-bundling.s b/test/MC/X86/AlignedBundling/single-inst-bundling.s index c0275f4..a7df2c9 100644 --- a/test/MC/X86/AlignedBundling/single-inst-bundling.s +++ b/test/MC/X86/AlignedBundling/single-inst-bundling.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ -# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s # Test simple NOP insertion for single instructions. @@ -24,14 +26,17 @@ foo: movl %ebx, %edi callq bar cmpl %r14d, %ebp +# CHECK-RELAX: nopl jle .L_ELSE # Due to the padding that's inserted before the addl, the jump target # becomes farther by one byte. -# CHECK: jle 5 +# CHECK-OPT: jle 5 +# CHECK-RELAX: jle 7 addl %ebp, %eax -# CHECK: nop -# CHECK-NEXT: 20: addl +# CHECK-OPT: nop +# CHECK-OPT-NEXT:20: addl +# CHECK-RELAX: 26: addl jmp .L_RET .L_ELSE: diff --git a/test/MC/X86/expand-var.s b/test/MC/X86/expand-var.s index ef62d8a..8d5529a 100644 --- a/test/MC/X86/expand-var.s +++ b/test/MC/X86/expand-var.s @@ -1,6 +1,6 @@ // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux < %s | llvm-readobj -r | FileCheck %s -// CHECK: Section (2) .rela.text { +// CHECK: Section {{.*}} .rela.text { // CHECK-NEXT: 0x0 R_X86_64_32 d 0x0 // CHECK-NEXT: } diff --git a/test/MC/X86/reloc-undef-global.s b/test/MC/X86/reloc-undef-global.s index a4854d4..24de904 100644 --- a/test/MC/X86/reloc-undef-global.s +++ b/test/MC/X86/reloc-undef-global.s @@ -7,7 +7,7 @@ bar = foo + 4 .long bar // ELF: Relocations [ -// ELF-NEXT: Section (2) .rela.text { +// ELF-NEXT: Section {{.*}} .rela.text { // ELF-NEXT: 0x0 R_X86_64_32 foo 0x4 // ELF-NEXT: } // ELF-NEXT: ] diff --git a/test/MC/X86/stackmap-nops.ll b/test/MC/X86/stackmap-nops.ll index a0d4418..33ef862 100644 --- a/test/MC/X86/stackmap-nops.ll +++ b/test/MC/X86/stackmap-nops.ll @@ -25,26 +25,26 @@ entry: ; CHECK: 7c: 5d ; CHECK: 7d: c3 - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 1) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 2, i32 2) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 3) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 4) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 5, i32 5) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 6, i32 6) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 7, i32 7) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 8, i32 8) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 9, i32 9) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 10, i32 10) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 11, i32 11) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 12) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 13, i32 13) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 14) - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 15) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 1) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 2, i32 2) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 3) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 4) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 5, i32 5) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 6, i32 6) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 7, i32 7) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 8, i32 8) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 9, i32 9) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 10, i32 10) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 11, i32 11) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 12) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 13, i32 13) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 14) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 15) ; Add an extra stackmap with a zero-length shadow to thwart the shadow ; optimization. This will force all 15 bytes of the previous shadow to be ; padded with nops. - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 0) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0) ret void } diff --git a/test/MC/X86/x86-16.s b/test/MC/X86/x86-16.s index 1f87c81..9789cd2 100644 --- a/test/MC/X86/x86-16.s +++ b/test/MC/X86/x86-16.s @@ -30,7 +30,7 @@ // CHECK: movl %eax, -16(%ebp) # encoding: [0x67,0x66,0x89,0x45,0xf0] movl %eax, -16(%ebp) -// CHECK: testb %bl, %cl # encoding: [0x84,0xcb] +// CHECK: testb %bl, %cl # encoding: [0x84,0xd9] testb %bl, %cl // CHECK: cmpl %eax, %ebx # encoding: [0x66,0x39,0xc3] diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s index 648eb5a..56fd658 100644 --- a/test/MC/X86/x86-32.s +++ b/test/MC/X86/x86-32.s @@ -79,7 +79,7 @@ // CHECK: movl %eax, -16(%ebp) # encoding: [0x89,0x45,0xf0] movl %eax, -16(%ebp) -// CHECK: testb %bl, %cl # encoding: [0x84,0xcb] +// CHECK: testb %bl, %cl # encoding: [0x84,0xd9] testb %bl, %cl // CHECK: cmpl %eax, %ebx # encoding: [0x39,0xc3] diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index 10d420a..096e900 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -613,7 +613,7 @@ movq _foo@GOTPCREL(%rip), %r14 movq 0x00(%r13,%rax,8),%r13 // CHECK: testq %rax, %rbx -// CHECK: encoding: [0x48,0x85,0xd8] +// CHECK: encoding: [0x48,0x85,0xc3] testq %rax, %rbx // CHECK: cmpq %rbx, %r14 |