diff options
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/ARM/arm_instructions.s | 134 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 698 | ||||
| -rw-r--r-- | test/MC/ARM/diagnostics.s | 90 | ||||
| -rw-r--r-- | test/MC/ARM/mode-switch.s | 17 | ||||
| -rw-r--r-- | test/MC/ARM/prefetch.ll | 4 | ||||
| -rw-r--r-- | test/MC/ARM/simple-encoding.ll | 7 | ||||
| -rw-r--r-- | test/MC/ARM/thumb.s | 15 | ||||
| -rw-r--r-- | test/MC/ARM/thumb2.s | 15 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/neon-tests.txt | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/X86/x86-32.txt | 26 | ||||
| -rw-r--r-- | test/MC/X86/x86-64.s | 22 |
12 files changed, 885 insertions, 153 deletions
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index 66fc87f3..650fcd2 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -20,76 +20,28 @@ @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] vqdmull.s32 q8, d17, d16 -@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] -@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] -@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9] -@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8] -@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9] -@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] - ldm r2, {r1,r3-r6,sp} - ldmia r2, {r1,r3-r6,sp} - ldmib r2, {r1,r3-r6,sp} - ldmda r2, {r1,r3-r6,sp} - ldmdb r2, {r1,r3-r6,sp} - ldmfd r2, {r1,r3-r6,sp} - -@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] -@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] -@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9] -@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8] -@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] -@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] - stm r2, {r1,r3-r6,sp} - stmia r2, {r1,r3-r6,sp} - stmib r2, {r1,r3-r6,sp} - stmda r2, {r1,r3-r6,sp} - stmdb r2, {r1,r3-r6,sp} - stmfd r2, {r1,r3-r6,sp} - -@ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8] -@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9] -@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8] -@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9] - ldmia r2!, {r1,r3-r6,sp} - ldmib r2!, {r1,r3-r6,sp} - ldmda r2!, {r1,r3-r6,sp} - ldmdb r2!, {r1,r3-r6,sp} - -@ CHECK: stmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8] -@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9] -@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8] -@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9] - stmia r2!, {r1,r3-r6,sp} - stmib r2!, {r1,r3-r6,sp} - stmda r2!, {r1,r3-r6,sp} - stmdb r2!, {r1,r3-r6,sp} - @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] and r1,r2,r3 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] +@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] ands r1,r2,r3 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] eor r1,r2,r3 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] +@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] eors r1,r2,r3 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] sub r1,r2,r3 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0] +@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0] subs r1,r2,r3 @ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] add r1,r2,r3 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0] +@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0] adds r1,r2,r3 @ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0] @@ -101,15 +53,13 @@ @ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] orr r1,r2,r3 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] +@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] orrs r1,r2,r3 @ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] bic r1,r2,r3 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1] +@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1] bics r1,r2,r3 @ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1] @@ -118,8 +68,7 @@ @ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1] mvn r1,r2 -@ FIXME: This is wrong, we are dropping the 's' for now. -@ CHECK-FIXME: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] +@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] mvns r1,r2 @ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0] @@ -128,37 +77,22 @@ @ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0] rsc r1,r2,r3 -@ FIXME: This is broken, CCOut operands don't work correctly when their presence -@ may depend on flags. -@ CHECK-FIXME:: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] -@ mlas r1,r2,r3,r4 - @ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7] bfi r0, r0, #5, #7 @ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] bkpt #10 -@ CHECK: isb @ encoding: [0x6f,0xf0,0x7f,0xf5] - isb @ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1] mrs r8, cpsr -@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee] - mcr p7, #1, r5, c1, c1, #4 @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] mrc p14, #0, r1, c1, c2, #4 -@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xec] - mcrr p7, #1, r5, r4, c1 @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] mrrc p7, #1, r5, r4, c1 -@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe] - mcr2 p7, #1, r5, c1, c1, #4 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] mrc2 p14, #0, r1, c1, c2, #4 -@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xfc] - mcrr2 p7, #1, r5, r4, c1 @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] mrrc2 p7, #1, r5, r4, c1 @@ -167,12 +101,6 @@ @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] cdp2 p7, #1, c1, c1, c1, #4 -@ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5] - clrex - -@ CHECK: clz r9, r0 @ encoding: [0x10,0x9f,0x6f,0xe1] - clz r9, r0 - @ CHECK: qadd r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1] qadd r1, r2, r3 @@ -197,54 +125,6 @@ @ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] nop -@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] - dmb sy - -@ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5] - dmb st - -@ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] - dmb ish - -@ CHECK: dmb ishst @ encoding: [0x5a,0xf0,0x7f,0xf5] - dmb ishst - -@ CHECK: dmb nsh @ encoding: [0x57,0xf0,0x7f,0xf5] - dmb nsh - -@ CHECK: dmb nshst @ encoding: [0x56,0xf0,0x7f,0xf5] - dmb nshst - -@ CHECK: dmb osh @ encoding: [0x53,0xf0,0x7f,0xf5] - dmb osh - -@ CHECK: dmb oshst @ encoding: [0x52,0xf0,0x7f,0xf5] - dmb oshst - -@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] - dsb sy - -@ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5] - dsb st - -@ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] - dsb ish - -@ CHECK: dsb ishst @ encoding: [0x4a,0xf0,0x7f,0xf5] - dsb ishst - -@ CHECK: dsb nsh @ encoding: [0x47,0xf0,0x7f,0xf5] - dsb nsh - -@ CHECK: dsb nshst @ encoding: [0x46,0xf0,0x7f,0xf5] - dsb nshst - -@ CHECK: dsb osh @ encoding: [0x43,0xf0,0x7f,0xf5] - dsb osh - -@ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5] - dsb oshst - @ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1] cpsie aif diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s new file mode 100644 index 0000000..0b728bc --- /dev/null +++ b/test/MC/ARM/basic-arm-instructions.s @@ -0,0 +1,698 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ For complex constructs like shifter operands, check more thoroughly for them +@ once then spot check that following instructions accept the form generally. +@ This gives us good coverage while keeping the overall size of the test +@ more reasonable. + +_func: +@ CHECK: _func + +@------------------------------------------------------------------------------ +@ ADC (immediate) +@------------------------------------------------------------------------------ + adc r1, r2, #0xf + adc r1, r2, #0xf0 + adc r1, r2, #0xf00 + adc r1, r2, #0xf000 + adc r1, r2, #0xf0000 + adc r1, r2, #0xf00000 + adc r1, r2, #0xf000000 + adc r1, r2, #0xf0000000 + adc r1, r2, #0xf000000f + adcs r1, r2, #0xf00 + adcseq r1, r2, #0xf00 + adceq r1, r2, #0xf00 + +@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2] +@ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2] +@ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2] +@ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2] +@ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2] +@ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2] +@ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2] +@ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2] + +@ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2] +@ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02] +@ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02] + +@------------------------------------------------------------------------------ +@ ADC (register) +@ ADC (shifted register) +@------------------------------------------------------------------------------ + adc r4, r5, r6 + @ Constant shifts + adc r4, r5, r6, lsl #1 + adc r4, r5, r6, lsl #31 + adc r4, r5, r6, lsr #1 + adc r4, r5, r6, lsr #31 + adc r4, r5, r6, lsr #32 + adc r4, r5, r6, asr #1 + adc r4, r5, r6, asr #31 + adc r4, r5, r6, asr #32 + adc r4, r5, r6, ror #1 + adc r4, r5, r6, ror #31 + + @ Register shifts + adc r6, r7, r8, lsl r9 + adc r6, r7, r8, lsr r9 + adc r6, r7, r8, asr r9 + adc r6, r7, r8, ror r9 + adc r4, r5, r6, rrx + + @ Destination register is optional + adc r5, r6 + adc r4, r5, lsl #1 + adc r4, r5, lsl #31 + adc r4, r5, lsr #1 + adc r4, r5, lsr #31 + adc r4, r5, lsr #32 + adc r4, r5, asr #1 + adc r4, r5, asr #31 + adc r4, r5, asr #32 + adc r4, r5, ror #1 + adc r4, r5, ror #31 + adc r4, r5, rrx + adc r6, r7, lsl r9 + adc r6, r7, lsr r9 + adc r6, r7, asr r9 + adc r6, r7, ror r9 + adc r4, r5, rrx + +@ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0] + +@ CHECK: adc r4, r5, r6, lsl #1 @ encoding: [0x86,0x40,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, lsl #31 @ encoding: [0x86,0x4f,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, lsr #32 @ encoding: [0x26,0x40,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, asr #1 @ encoding: [0xc6,0x40,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, asr #31 @ encoding: [0xc6,0x4f,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, asr #32 @ encoding: [0x46,0x40,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, ror #1 @ encoding: [0xe6,0x40,0xa5,0xe0] +@ CHECK: adc r4, r5, r6, ror #31 @ encoding: [0xe6,0x4f,0xa5,0xe0] + +@ CHECK: adc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xa7,0xe0] +@ CHECK: adc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xa7,0xe0] +@ CHECK: adc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xa7,0xe0] +@ CHECK: adc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xa7,0xe0] +@ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0] + +@ CHECK: adc r5, r5, r6 @ encoding: [0x06,0x50,0xa5,0xe0] +@ CHECK: adc r4, r4, r5, lsl #1 @ encoding: [0x85,0x40,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, lsl #31 @ encoding: [0x85,0x4f,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, lsr #1 @ encoding: [0xa5,0x40,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, lsr #31 @ encoding: [0xa5,0x4f,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, lsr #32 @ encoding: [0x25,0x40,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, asr #1 @ encoding: [0xc5,0x40,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, asr #31 @ encoding: [0xc5,0x4f,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, asr #32 @ encoding: [0x45,0x40,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, ror #1 @ encoding: [0xe5,0x40,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, ror #31 @ encoding: [0xe5,0x4f,0xa4,0xe0] +@ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0] +@ CHECK: adc r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xa6,0xe0] +@ CHECK: adc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xa6,0xe0] +@ CHECK: adc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xa6,0xe0] +@ CHECK: adc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xa6,0xe0] +@ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: ADR +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ ADD +@------------------------------------------------------------------------------ + add r4, r5, #0xf000 + add r4, r5, r6 + add r4, r5, r6, lsl #5 + add r4, r5, r6, lsr #5 + add r4, r5, r6, lsr #5 + add r4, r5, r6, asr #5 + add r4, r5, r6, ror #5 + add r6, r7, r8, lsl r9 + add r6, r7, r8, lsr r9 + add r6, r7, r8, asr r9 + add r6, r7, r8, ror r9 + add r4, r5, r6, rrx + + @ destination register is optional + add r5, #0xf000 + add r4, r5 + add r4, r5, lsl #5 + add r4, r5, lsr #5 + add r4, r5, lsr #5 + add r4, r5, asr #5 + add r4, r5, ror #5 + add r6, r7, lsl r9 + add r6, r7, lsr r9 + add r6, r7, asr r9 + add r6, r7, ror r9 + add r4, r5, rrx + +@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0] +@ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0] +@ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0] +@ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0] +@ CHECK: add r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe0] +@ CHECK: add r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe0] +@ CHECK: add r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe0] +@ CHECK: add r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe0] +@ CHECK: add r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe0] +@ CHECK: add r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe0] +@ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0] + + +@ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0] +@ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0] +@ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0] +@ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0] +@ CHECK: add r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x84,0xe0] +@ CHECK: add r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x84,0xe0] +@ CHECK: add r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x86,0xe0] +@ CHECK: add r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x86,0xe0] +@ CHECK: add r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0xe0] +@ CHECK: add r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe0] +@ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0] + + +@------------------------------------------------------------------------------ +@ AND +@------------------------------------------------------------------------------ + and r10, r1, #0xf + and r10, r1, r6 + and r10, r1, r6, lsl #10 + and r10, r1, r6, lsr #10 + and r10, r1, r6, lsr #10 + and r10, r1, r6, asr #10 + and r10, r1, r6, ror #10 + and r6, r7, r8, lsl r2 + and r6, r7, r8, lsr r2 + and r6, r7, r8, asr r2 + and r6, r7, r8, ror r2 + and r10, r1, r6, rrx + + @ destination register is optional + and r1, #0xf + and r10, r1 + and r10, r1, lsl #10 + and r10, r1, lsr #10 + and r10, r1, lsr #10 + and r10, r1, asr #10 + and r10, r1, ror #10 + and r6, r7, lsl r2 + and r6, r7, lsr r2 + and r6, r7, asr r2 + and r6, r7, ror r2 + and r10, r1, rrx + +@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0] +@ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0] +@ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0] +@ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0] +@ CHECK: and r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0x01,0xe0] +@ CHECK: and r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0x01,0xe0] +@ CHECK: and r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0x07,0xe0] +@ CHECK: and r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0x07,0xe0] +@ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0] +@ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0] +@ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0] + +@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0] +@ CHECK: and r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0x0a,0xe0] +@ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0] +@ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0] +@ CHECK: and r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0x0a,0xe0] +@ CHECK: and r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0x0a,0xe0] +@ CHECK: and r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0x06,0xe0] +@ CHECK: and r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0x06,0xe0] +@ CHECK: and r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0x06,0xe0] +@ CHECK: and r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0x06,0xe0] +@ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0] + +@------------------------------------------------------------------------------ +@ FIXME: ASR +@------------------------------------------------------------------------------ +@------------------------------------------------------------------------------ +@ FIXME: B +@------------------------------------------------------------------------------ +@------------------------------------------------------------------------------ +@ FIXME: BFC +@------------------------------------------------------------------------------ +@------------------------------------------------------------------------------ +@ FIXME: BFI +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ BIC +@------------------------------------------------------------------------------ + bic r10, r1, #0xf + bic r10, r1, r6 + bic r10, r1, r6, lsl #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, asr #10 + bic r10, r1, r6, ror #10 + bic r6, r7, r8, lsl r2 + bic r6, r7, r8, lsr r2 + bic r6, r7, r8, asr r2 + bic r6, r7, r8, ror r2 + bic r10, r1, r6, rrx + + @ destination register is optional + bic r1, #0xf + bic r10, r1 + bic r10, r1, lsl #10 + bic r10, r1, lsr #10 + bic r10, r1, lsr #10 + bic r10, r1, asr #10 + bic r10, r1, ror #10 + bic r6, r7, lsl r2 + bic r6, r7, lsr r2 + bic r6, r7, asr r2 + bic r6, r7, ror r2 + bic r10, r1, rrx + +@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0xc1,0xe1] +@ CHECK: bic r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0xc1,0xe1] +@ CHECK: bic r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0xc7,0xe1] +@ CHECK: bic r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0xc7,0xe1] +@ CHECK: bic r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0xc7,0xe1] +@ CHECK: bic r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0xc7,0xe1] +@ CHECK: bic r10, r1, r6, rrx @ encoding: [0x66,0xa0,0xc1,0xe1] + + +@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1] +@ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0xca,0xe1] +@ CHECK: bic r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0xca,0xe1] +@ CHECK: bic r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0xc6,0xe1] +@ CHECK: bic r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0xc6,0xe1] +@ CHECK: bic r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0xc6,0xe1] +@ CHECK: bic r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0xc6,0xe1] +@ CHECK: bic r10, r10, r1, rrx @ encoding: [0x61,0xa0,0xca,0xe1] + +@------------------------------------------------------------------------------ +@ BKPT +@------------------------------------------------------------------------------ + bkpt #10 + bkpt #65535 + +@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] +@ CHECK: bkpt #65535 @ encoding: [0x7f,0xff,0x2f,0xe1] + +@------------------------------------------------------------------------------ +@ BL/BLX (immediate) +@------------------------------------------------------------------------------ + + bl _bar + @ FIXME: blx _bar + +@ CHECK: bl _bar @ encoding: [A,A,A,0xeb] +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch + +@------------------------------------------------------------------------------ +@ BLX (register) +@------------------------------------------------------------------------------ + blx r2 + blxne r2 + +@ CHECK: blx r2 @ encoding: [0x32,0xff,0x2f,0xe1] +@ CHECK: blxne r2 @ encoding: [0x32,0xff,0x2f,0x11] + +@------------------------------------------------------------------------------ +@ BX +@------------------------------------------------------------------------------ + + bx r2 + bxne r2 + +@ CHECK: bx r2 @ encoding: [0x12,0xff,0x2f,0xe1] +@ CHECK: bxne r2 @ encoding: [0x12,0xff,0x2f,0x11] + +@------------------------------------------------------------------------------ +@ BXJ +@------------------------------------------------------------------------------ + + bxj r2 + bxjne r2 + +@ CHECK: bxj r2 @ encoding: [0x22,0xff,0x2f,0xe1] +@ CHECK: bxjne r2 @ encoding: [0x22,0xff,0x2f,0x11] + +@------------------------------------------------------------------------------ +@ FIXME: CBNZ/CBZ +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ CDP/CDP2 +@------------------------------------------------------------------------------ + cdp p7, #1, c1, c1, c1, #4 + cdp2 p7, #1, c1, c1, c1, #4 + +@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee] +@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] + + +@------------------------------------------------------------------------------ +@ CLREX +@------------------------------------------------------------------------------ + clrex + +@ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5] + + +@------------------------------------------------------------------------------ +@ CLZ +@------------------------------------------------------------------------------ + clz r1, r2 + clzeq r1, r2 + +@ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1] +@ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01] + +@------------------------------------------------------------------------------ +@ CMN +@------------------------------------------------------------------------------ + cmn r1, #0xf + cmn r1, r6 + cmn r1, r6, lsl #10 + cmn r1, r6, lsr #10 + cmn sp, r6, lsr #10 + cmn r1, r6, asr #10 + cmn r1, r6, ror #10 + cmn r7, r8, lsl r2 + cmn sp, r8, lsr r2 + cmn r7, r8, asr r2 + cmn r7, r8, ror r2 + cmn r1, r6, rrx + +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1] +@ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1] +@ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1] +@ CHECK: cmn sp, r6, lsr #10 @ encoding: [0x26,0x05,0x7d,0xe1] +@ CHECK: cmn r1, r6, asr #10 @ encoding: [0x46,0x05,0x71,0xe1] +@ CHECK: cmn r1, r6, ror #10 @ encoding: [0x66,0x05,0x71,0xe1] +@ CHECK: cmn r7, r8, lsl r2 @ encoding: [0x18,0x02,0x77,0xe1] +@ CHECK: cmn sp, r8, lsr r2 @ encoding: [0x38,0x02,0x7d,0xe1] +@ CHECK: cmn r7, r8, asr r2 @ encoding: [0x58,0x02,0x77,0xe1] +@ CHECK: cmn r7, r8, ror r2 @ encoding: [0x78,0x02,0x77,0xe1] +@ CHECK: cmn r1, r6, rrx @ encoding: [0x66,0x00,0x71,0xe1] + +@------------------------------------------------------------------------------ +@ CMP +@------------------------------------------------------------------------------ + cmp r1, #0xf + cmp r1, r6 + cmp r1, r6, lsl #10 + cmp r1, r6, lsr #10 + cmp sp, r6, lsr #10 + cmp r1, r6, asr #10 + cmp r1, r6, ror #10 + cmp r7, r8, lsl r2 + cmp sp, r8, lsr r2 + cmp r7, r8, asr r2 + cmp r7, r8, ror r2 + cmp r1, r6, rrx + +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1] +@ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1] +@ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1] +@ CHECK: cmp sp, r6, lsr #10 @ encoding: [0x26,0x05,0x5d,0xe1] +@ CHECK: cmp r1, r6, asr #10 @ encoding: [0x46,0x05,0x51,0xe1] +@ CHECK: cmp r1, r6, ror #10 @ encoding: [0x66,0x05,0x51,0xe1] +@ CHECK: cmp r7, r8, lsl r2 @ encoding: [0x18,0x02,0x57,0xe1] +@ CHECK: cmp sp, r8, lsr r2 @ encoding: [0x38,0x02,0x5d,0xe1] +@ CHECK: cmp r7, r8, asr r2 @ encoding: [0x58,0x02,0x57,0xe1] +@ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1] +@ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1] + +@------------------------------------------------------------------------------ +@ DBG +@------------------------------------------------------------------------------ + dbg #0 + dbg #5 + dbg #15 + +@ CHECK: dbg #0 @ encoding: [0xf0,0xf0,0x20,0xe3] +@ CHECK: dbg #5 @ encoding: [0xf5,0xf0,0x20,0xe3] +@ CHECK: dbg #15 @ encoding: [0xff,0xf0,0x20,0xe3] + + +@------------------------------------------------------------------------------ +@ DMB +@------------------------------------------------------------------------------ + dmb sy + dmb st + dmb sh + dmb ish + dmb shst + dmb ishst + dmb un + dmb nsh + dmb unst + dmb nshst + dmb osh + dmb oshst + dmb + +@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] +@ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5] +@ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] +@ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] +@ CHECK: dmb ishst @ encoding: [0x5a,0xf0,0x7f,0xf5] +@ CHECK: dmb ishst @ encoding: [0x5a,0xf0,0x7f,0xf5] +@ CHECK: dmb nsh @ encoding: [0x57,0xf0,0x7f,0xf5] +@ CHECK: dmb nsh @ encoding: [0x57,0xf0,0x7f,0xf5] +@ CHECK: dmb nshst @ encoding: [0x56,0xf0,0x7f,0xf5] +@ CHECK: dmb nshst @ encoding: [0x56,0xf0,0x7f,0xf5] +@ CHECK: dmb osh @ encoding: [0x53,0xf0,0x7f,0xf5] +@ CHECK: dmb oshst @ encoding: [0x52,0xf0,0x7f,0xf5] +@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] + +@------------------------------------------------------------------------------ +@ DSB +@------------------------------------------------------------------------------ + dsb sy + dsb st + dsb sh + dsb ish + dsb shst + dsb ishst + dsb un + dsb nsh + dsb unst + dsb nshst + dsb osh + dsb oshst + dsb + +@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] +@ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5] +@ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] +@ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] +@ CHECK: dsb ishst @ encoding: [0x4a,0xf0,0x7f,0xf5] +@ CHECK: dsb ishst @ encoding: [0x4a,0xf0,0x7f,0xf5] +@ CHECK: dsb nsh @ encoding: [0x47,0xf0,0x7f,0xf5] +@ CHECK: dsb nsh @ encoding: [0x47,0xf0,0x7f,0xf5] +@ CHECK: dsb nshst @ encoding: [0x46,0xf0,0x7f,0xf5] +@ CHECK: dsb nshst @ encoding: [0x46,0xf0,0x7f,0xf5] +@ CHECK: dsb osh @ encoding: [0x43,0xf0,0x7f,0xf5] +@ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5] +@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] + +@------------------------------------------------------------------------------ +@ EOR +@------------------------------------------------------------------------------ + eor r4, r5, #0xf000 + eor r4, r5, r6 + eor r4, r5, r6, lsl #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, asr #5 + eor r4, r5, r6, ror #5 + eor r6, r7, r8, lsl r9 + eor r6, r7, r8, lsr r9 + eor r6, r7, r8, asr r9 + eor r6, r7, r8, ror r9 + eor r4, r5, r6, rrx + + @ destination register is optional + eor r5, #0xf000 + eor r4, r5 + eor r4, r5, lsl #5 + eor r4, r5, lsr #5 + eor r4, r5, lsr #5 + eor r4, r5, asr #5 + eor r4, r5, ror #5 + eor r6, r7, lsl r9 + eor r6, r7, lsr r9 + eor r6, r7, asr r9 + eor r6, r7, ror r9 + eor r4, r5, rrx + +@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0] +@ CHECK: eor r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x25,0xe0] +@ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0] +@ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0] +@ CHECK: eor r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x25,0xe0] +@ CHECK: eor r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x25,0xe0] +@ CHECK: eor r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x27,0xe0] +@ CHECK: eor r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x27,0xe0] +@ CHECK: eor r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x27,0xe0] +@ CHECK: eor r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x27,0xe0] +@ CHECK: eor r4, r5, r6, rrx @ encoding: [0x66,0x40,0x25,0xe0] + + +@ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r4, r4, r5 @ encoding: [0x05,0x40,0x24,0xe0] +@ CHECK: eor r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x24,0xe0] +@ CHECK: eor r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x24,0xe0] +@ CHECK: eor r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x24,0xe0] +@ CHECK: eor r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x24,0xe0] +@ CHECK: eor r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x24,0xe0] +@ CHECK: eor r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x26,0xe0] +@ CHECK: eor r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x26,0xe0] +@ CHECK: eor r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x26,0xe0] +@ CHECK: eor r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x26,0xe0] +@ CHECK: eor r4, r4, r5, rrx @ encoding: [0x65,0x40,0x24,0xe0] + + +@------------------------------------------------------------------------------ +@ ISB +@------------------------------------------------------------------------------ + isb sy + isb + +@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5] +@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5] + + + +@------------------------------------------------------------------------------ +@ LDM* +@------------------------------------------------------------------------------ + ldm r2, {r1,r3-r6,sp} + ldmia r2, {r1,r3-r6,sp} + ldmib r2, {r1,r3-r6,sp} + ldmda r2, {r1,r3-r6,sp} + ldmdb r2, {r1,r3-r6,sp} + ldmfd r2, {r1,r3-r6,sp} + + @ with update + ldm r2!, {r1,r3-r6,sp} + ldmib r2!, {r1,r3-r6,sp} + ldmda r2!, {r1,r3-r6,sp} + ldmdb r2!, {r1,r3-r6,sp} + +@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] +@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] +@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9] +@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8] +@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9] +@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] + +@ CHECK: ldm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8] +@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9] +@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8] +@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9] + +@------------------------------------------------------------------------------ +@ FIXME: LDR* +@------------------------------------------------------------------------------ +@------------------------------------------------------------------------------ +@ FIXME: LSL +@------------------------------------------------------------------------------ +@------------------------------------------------------------------------------ +@ FIXME: LSR +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ MCR/MCR2 +@------------------------------------------------------------------------------ + mcr p7, #1, r5, c1, c1, #4 + mcr2 p7, #1, r5, c1, c1, #4 + +@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee] +@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe] + +@------------------------------------------------------------------------------ +@ MCRR/MCRR2 +@------------------------------------------------------------------------------ + mcrr p7, #15, r5, r4, c1 + mcrr2 p7, #15, r5, r4, c1 + +@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec] +@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc] + + +@------------------------------------------------------------------------------ +@ MLA +@------------------------------------------------------------------------------ + mla r1,r2,r3,r4 + mlas r1,r2,r3,r4 + mlane r1,r2,r3,r4 + mlasne r1,r2,r3,r4 + +@ CHECK: mla r1, r2, r3, r4 @ encoding: [0x92,0x43,0x21,0xe0] +@ CHECK: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] +@ CHECK: mlane r1, r2, r3, r4 @ encoding: [0x92,0x43,0x21,0x10] +@ CHECK: mlasne r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0x10] + +@------------------------------------------------------------------------------ +@ MLS +@------------------------------------------------------------------------------ + mls r2,r5,r6,r3 + mlsne r2,r5,r6,r3 + +@ CHECK: mls r2, r5, r6, r3 @ encoding: [0x95,0x36,0x62,0xe0] +@ CHECK: mlsne r2, r5, r6, r3 @ encoding: [0x95,0x36,0x62,0x10] + +@------------------------------------------------------------------------------ +@ STM* +@------------------------------------------------------------------------------ + stm r2, {r1,r3-r6,sp} + stmia r2, {r1,r3-r6,sp} + stmib r2, {r1,r3-r6,sp} + stmda r2, {r1,r3-r6,sp} + stmdb r2, {r1,r3-r6,sp} + stmfd r2, {r1,r3-r6,sp} + + @ with update + stmia r2!, {r1,r3-r6,sp} + stmib r2!, {r1,r3-r6,sp} + stmda r2!, {r1,r3-r6,sp} + stmdb r2!, {r1,r3-r6,sp} +@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] +@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] +@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9] +@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8] +@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] +@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] + +@ CHECK: stm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8] +@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9] +@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8] +@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9] diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s new file mode 100644 index 0000000..4537a0f --- /dev/null +++ b/test/MC/ARM/diagnostics.s @@ -0,0 +1,90 @@ +@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +@ Check for various assembly diagnostic messages on invalid input. + +@ 's' bit on an instruction that can't accept it. + mlss r1, r2, r3, r4 +@ CHECK-ERRORS: error: instruction 'mls' can not set flags, +@ CHECK-ERRORS: but 's' suffix specified + + + @ Out of range shift immediate values. + adc r1, r2, r3, lsl #invalid + adc r4, r5, r6, lsl #-1 + adc r4, r5, r6, lsl #32 + adc r4, r5, r6, lsr #-1 + adc r4, r5, r6, lsr #33 + adc r4, r5, r6, asr #-1 + adc r4, r5, r6, asr #33 + adc r4, r5, r6, ror #-1 + adc r4, r5, r6, ror #32 + +@ CHECK-ERRORS: error: invalid immediate shift value +@ CHECK-ERRORS: adc r1, r2, r3, lsl #invalid +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, lsl #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, lsl #32 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, lsr #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, lsr #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, asr #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, asr #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, ror #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate shift value out of range +@ CHECK-ERRORS: adc r4, r5, r6, ror #32 + + + @ Out of range 16-bit immediate on BKPT + bkpt #65536 + +@ CHECK-ERRORS: error: invalid operand for instruction + + @ Out of range 4 and 3 bit immediates on CDP[2] + + @ Out of range immediates for CDP/CDP2 + cdp p7, #2, c1, c1, c1, #8 + cdp p7, #1, c1, c1, c1, #8 + cdp2 p7, #2, c1, c1, c1, #8 + cdp2 p7, #1, c1, c1, c1, #8 + +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction + + @ Out of range immediates for DBG + dbg #-1 + dbg #16 + +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ Double-check that we're synced up with the right diagnostics. +@ CHECK-ERRORS: dbg #16 + + @ Out of range immediate for MCR/MCR2/MCRR/MCRR2 + mcr p7, #8, r5, c1, c1, #4 + mcr p7, #2, r5, c1, c1, #8 + mcr2 p7, #8, r5, c1, c1, #4 + mcr2 p7, #1, r5, c1, c1, #8 + mcrr p7, #16, r5, r4, c1 + mcrr2 p7, #16, r5, r4, c1 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction diff --git a/test/MC/ARM/mode-switch.s b/test/MC/ARM/mode-switch.s new file mode 100644 index 0000000..4cc986a --- /dev/null +++ b/test/MC/ARM/mode-switch.s @@ -0,0 +1,17 @@ +@ Test ARM / Thumb mode switching with .code +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] + add.w r0, r0, r1 + +.code 32 +@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0] + add r0, r0, r1 + +.code 16 +@ CHECK: add r0, r0, r1 @ encoding: [0x40,0x18] + + add r0, r0, r1 diff --git a/test/MC/ARM/prefetch.ll b/test/MC/ARM/prefetch.ll index 674b8f3..e77fdb1 100644 --- a/test/MC/ARM/prefetch.ll +++ b/test/MC/ARM/prefetch.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2 +; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2 ; rdar://8924681 define void @t1(i8* %ptr) nounwind { diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll index 3322803..14ed945 100644 --- a/test/MC/ARM/simple-encoding.ll +++ b/test/MC/ARM/simple-encoding.ll @@ -39,8 +39,7 @@ define i32 @f3(i32 %a, i32 %b) { define i32 @f4(i32 %a, i32 %b) { ; CHECK: f4 -; CHECK: add r0, r0, #254, #28 @ encoding: [0xfe,0x0e,0x80,0xe2] -; CHECK: @ 4064 +; CHECK: add r0, r0, #4064 @ encoding: [0xfe,0x0e,0x80,0xe2] ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] %add = add nsw i32 %a, 4064 ret i32 %add @@ -118,7 +117,7 @@ define i32 @f12(i32 %a) { define i64 @f13() { ; CHECK: f13: ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3] -; CHECK: mvn r1, #2, #2 @ encoding: [0x02,0x11,0xe0,0xe3] +; CHECK: mvn r1, #-2147483648 @ encoding: [0x02,0x11,0xe0,0xe3] ret i64 9223372036854775807 } @@ -229,7 +228,7 @@ define i32 @f23(i32 %X, i32 %Y) { define void @f24(i32 %a) { ; CHECK: f24 -; CHECK: cmp r0, #1, #16 @ encoding: [0x01,0x08,0x50,0xe3] +; CHECK: cmp r0, #65536 @ encoding: [0x01,0x08,0x50,0xe3] %b = icmp ugt i32 %a, 65536 br i1 %b, label %r, label %r r: diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s index 55d9789..79ea2e4 100644 --- a/test/MC/ARM/thumb.s +++ b/test/MC/ARM/thumb.s @@ -41,21 +41,6 @@ @ CHECK: bkpt #2 @ encoding: [0x02,0xbe] bkpt #2 -@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] - mcr p7, #1, r5, c1, c1, #4 - -@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] - mrc p14, #0, r1, c1, c2, #4 - -@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x44,0xec,0x11,0x57] - mcrr p7, #1, r5, r4, c1 - -@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] - mrrc p7, #1, r5, r4, c1 - -@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17] - cdp p7, #1, c1, c1, c1, #4 - @ CHECK: nop @ encoding: [0x00,0xbf] nop diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s index 41dda84..7d632db 100644 --- a/test/MC/ARM/thumb2.s +++ b/test/MC/ARM/thumb2.s @@ -189,6 +189,18 @@ @ CHECK: vmsr fpsid, r0 @ encoding: [0xe0,0xee,0x10,0x0a] vmsr fpsid, r0 +@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] + mcr p7, #1, r5, c1, c1, #4 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] + mrc p14, #0, r1, c1, c2, #4 + +@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x44,0xec,0x11,0x57] + mcrr p7, #1, r5, r4, c1 + +@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] + mrrc p7, #1, r5, r4, c1 + @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] mcr2 p7, #1, r5, c1, c1, #4 @@ -201,6 +213,9 @@ @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57] mrrc2 p7, #1, r5, r4, c1 +@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17] + cdp p7, #1, c1, c1, c1, #4 + @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17] cdp2 p7, #1, c1, c1, c1, #4 diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index ca072c7..0536eeb 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,6 +1,6 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s -# CHECK: addpl r4, pc, #19, #8 +# CHECK: addpl r4, pc, #318767104 0x4c 0x45 0x8f 0x52 # CHECK: b #0 @@ -21,7 +21,7 @@ # CHECK: mov pc, lr 0x0e 0xf0 0xa0 0xe1 -# CHECK: mov pc, #255, #2 +# CHECK: mov pc, #3221225535 0xff 0xf1 0xa0 0xe3 # CHECK: movw r7, #4096 @@ -72,7 +72,7 @@ # CHECK: movt r8, #65535 0xff 0x8f 0x4f 0xe3 -# CHECK: mvnspl r7, #245, #2 +# CHECK: mvnspl r7, #1073741885 0xf5 0x71 0xf0 0x53 # CHECK-NOT: orr r7, r8, r7, rrx #0 @@ -152,7 +152,7 @@ # CHECK: msr cpsr_fc, r0 0x00 0xf0 0x29 0xe1 -# CHECK: msrmi cpsr_c, #241, #8 +# CHECK: msrmi cpsr_c, #4043309056 0xf1 0xf4 0x21 0x43 # CHECK: rsbs r6, r7, r8 diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index cfb5949..4fa5723 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -27,7 +27,7 @@ # CHECK: vld4.16 {d3[], d4[], d5[], d6[]}, [r0, :64]! 0x7d 0x3f 0xa0 0xf4 -# CHECK: vmov d0, d15 +# CHECK: vorr d0, d15, d15 0x1f 0x01 0x2f 0xf2 # CHECK: vmov.i64 q6, #0xFF00FF00FF diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt new file mode 100644 index 0000000..dd313f1 --- /dev/null +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -0,0 +1,26 @@ +# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s + +# Coverage + +# CHECK: pushl +0xff 0x34 0x24 + +# CHECK: popl +0x58 + +# CHECK: calll +0xff 0xd0 + +# CHECK: incl +0x40 + +# CHECK: leave +0xc9 + +# PR8873: some instructions not recognized in 32-bit mode + +# CHECK: fld +0xdd 0x04 0x24 + +# CHECK: pshufb +0x0f 0x38 0x00 0xc0 diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index 5074a1d..6f828e8 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -219,6 +219,12 @@ inb $161, %al // CHECK: pushq $1 push $1 +// rdar://9716860 +pushq $1 +// CHECK: encoding: [0x6a,0x01] +pushq $1111111 +// CHECK: encoding: [0x68,0x47,0xf4,0x10,0x00] + // rdar://8017530 // CHECK: sldtw 4 sldt 4 @@ -1148,3 +1154,19 @@ movnti %eax, (%rdi) // CHECK: movntiq movntiq %rax, (%rdi) movnti %rax, (%rdi) + +// CHECK: pclmulqdq $17, %xmm0, %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x11] +pclmulhqhqdq %xmm0, %xmm1 + +// CHECK: pclmulqdq $1, %xmm0, %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x01] +pclmulqdq $1, %xmm0, %xmm1 + +// CHECK: pclmulqdq $16, (%rdi), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x10] +pclmullqhqdq (%rdi), %xmm1 + +// CHECK: pclmulqdq $0, (%rdi), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x00] +pclmulqdq $0, (%rdi), %xmm1 |