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-rw-r--r--test/MC/ARM/fp-armv8.s5
-rw-r--r--test/MC/Disassembler/ARM/fp-armv8.txt5
-rw-r--r--test/MC/Disassembler/ARM/invalid-because-armv7.txt6
3 files changed, 16 insertions, 0 deletions
diff --git a/test/MC/ARM/fp-armv8.s b/test/MC/ARM/fp-armv8.s
index cba4a51..1ffd590 100644
--- a/test/MC/ARM/fp-armv8.s
+++ b/test/MC/ARM/fp-armv8.s
@@ -122,3 +122,8 @@
@ CHECK: vrintm.f64 d3, d4 @ encoding: [0x44,0x3b,0xbb,0xfe]
vrintm.f32 s12, s1
@ CHECK: vrintm.f32 s12, s1 @ encoding: [0x60,0x6a,0xbb,0xfe]
+
+@ MVFR2
+
+ vmrs sp, mvfr2
+@ CHECK: vmrs sp, mvfr2 @ encoding: [0x10,0xda,0xf5,0xee]
diff --git a/test/MC/Disassembler/ARM/fp-armv8.txt b/test/MC/Disassembler/ARM/fp-armv8.txt
index 4d2f8f6..46a26f5 100644
--- a/test/MC/Disassembler/ARM/fp-armv8.txt
+++ b/test/MC/Disassembler/ARM/fp-armv8.txt
@@ -153,3 +153,8 @@
0x60 0x6a 0xbb 0xfe
# CHECK: vrintm.f32 s12, s1
+
+
+0x10 0xa 0xf5 0xee
+# CHECK: vmrs r0, mvfr2
+
diff --git a/test/MC/Disassembler/ARM/invalid-because-armv7.txt b/test/MC/Disassembler/ARM/invalid-because-armv7.txt
index 4bf4833..beed8e4 100644
--- a/test/MC/Disassembler/ARM/invalid-because-armv7.txt
+++ b/test/MC/Disassembler/ARM/invalid-because-armv7.txt
@@ -18,3 +18,9 @@
[0x41 0x2b 0xb3 0xbe]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
+
+# Would be vmrs r0, mvfr2
+[0x10 0xa 0xf5 0xee]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x10 0xa 0xf5 0xee]
+