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* Add test case accidentally omitted from r160002.Chad Rosier2012-07-101-0/+242
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-07-107-19/+139
| | | | | | | | | | | | | | X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth2012-07-101-1/+2
| | | | | | | | | | | | | | | back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem2012-07-105-40/+73
| | | | | | | | | | | multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-104-9/+49
| | | | | | single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-103-52/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an efficient merge operation to LiveInterval and use it to avoidChandler Carruth2012-07-102-32/+135
| | | | | | | | | | | quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LiveIntervals how to verify themselves and start using it in someChandler Carruth2012-07-102-0/+42
| | | | | | | | | | of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Allow more flexible patterns in NEON formats.Jim Grosbach2012-07-101-53/+53
| | | | | | | | | Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow intrinsics to be used in place of node matchables.Jim Grosbach2012-07-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | TableGen has support for using an intrinics name directly in a DAG, but this breaks down when referring to just a node, as that's handled initializer list stuff entirely via subclassing in the parser. That is, using an instrinsic like "(int_my_intrinsic ...)" works fine. Using it standalone for parameterizing the operator in such a DAG does not. Fixing this is simple enough, as we simply declare Intrinsic as deriving from SDPatternOperator, which is the class name intended for exactly this purpose in TargetSelectionDAG.td. When the intrinsic is actually used in the DAG pattern, it will be recognized and expanded to an intrinsic_wo_chain (et. al.) just like when it's used directly. Incoming ARM NEON cleanup based on this and a bit of functionality improvement after that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159973 91177308-0d34-0410-b5e6-96231b3b80d8
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-1010-37/+376
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete code for folding undefs in ScalarEvolution. It's invalid inDan Gohman2012-07-091-14/+0
| | | | | | | obscure ways, and it isn't actually important in the real world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159969 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-093-29/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine model: allow itineraries to be shared by different processor models.Andrew Trick2012-07-091-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959 91177308-0d34-0410-b5e6-96231b3b80d8
* indentationAndrew Trick2012-07-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson2012-07-092-0/+62
| | | | | | | | | move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren2012-07-092-138/+202
| | | | | | | | | | | | getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-095-274/+249
| | | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: merge the functions that remove dead allocas and dead ↵Nuno Lopes2012-07-095-123/+75
| | | | | | | | | mallocs/callocs/... This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :) In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159952 91177308-0d34-0410-b5e6-96231b3b80d8
* Some formatting to keep Clang happyRichard Barton2012-07-091-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-093-8/+29
| | | | | | single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-092-1/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
* Spelling!Richard Barton2012-07-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton2012-07-092-0/+887
| | | | | | three-register dp instructions where permissable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some trivial copy ctors so the classes become trivially copyable and ↵Benjamin Kramer2012-07-082-6/+0
| | | | | | get the optimized SmallVector implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159916 91177308-0d34-0410-b5e6-96231b3b80d8
* SmallVector: Make use of move semantics to speed up moving objects in ↵Benjamin Kramer2012-07-081-6/+6
| | | | | | erase() and insert() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159914 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-0727-502/+904
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-07-072-5/+5
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* Tweak spelling.Andrew Trick2012-07-073-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-072-5/+43
| | | | | | | | | It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVMConfig.cmake.in: Quote around @LLVM_INSTALL_PREFIX@, or it would not ↵NAKAMURA Takumi2012-07-071-1/+1
| | | | | | | | accept whitespace paths. Thanks to Kai. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159887 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the DebugInfo wrappers instead of mucking about with the MDNode directly.Bill Wendling2012-07-071-22/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159881 91177308-0d34-0410-b5e6-96231b3b80d8
* Print the name last.Bill Wendling2012-07-061-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159879 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier2012-07-062-5/+5
| | | | | | should be camel case, and start with a lower case letter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877 91177308-0d34-0410-b5e6-96231b3b80d8
* teach instcombine to remove allocated buffers even if there are stores, ↵Nuno Lopes2012-07-066-17/+128
| | | | | | | | | | | | memcpy/memmove/memset, and objectsize users. This means we can do cheap DSE for heap memory. Nothing is done if the pointer excapes or has a load. The churn in the tests is mostly due to objectsize, since we want to make sure we don't delete the malloc call before evaluating the objectsize (otherwise it becomes -1/0) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159876 91177308-0d34-0410-b5e6-96231b3b80d8
* Since SmallMap was removed in r158644, remove documentation in ↵Dmitri Gribenko2012-07-061-81/+0
| | | | | | ProgrammersManual.html. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159874 91177308-0d34-0410-b5e6-96231b3b80d8
* Check if it's a scope last, because several things are scopes.Bill Wendling2012-07-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159873 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add test cleanup entry to the README.Jim Grosbach2012-07-061-0/+21
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* revert r159851.Akira Hatanaka2012-07-066-303/+326
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-066-326/+303
| | | | | | | Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a print method to the ObjC property object.Bill Wendling2012-07-062-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159848 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing comma in array initialization list.Bill Wendling2012-07-061-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159843 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary 'llvm::'.Bill Wendling2012-07-061-19/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159842 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary 'llvm::'.Bill Wendling2012-07-061-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159841 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Chad Rosier2012-07-061-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159839 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-064-0/+321
| | | | | | | | | | For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.Chad Rosier2012-07-062-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159837 91177308-0d34-0410-b5e6-96231b3b80d8
* Update getFunction parameter documentation. Fixes PR13268.Chad Rosier2012-07-061-2/+3
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* Revert r159789.Dmitri Gribenko2012-07-061-17/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159834 91177308-0d34-0410-b5e6-96231b3b80d8
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