aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Add 'landingpad' instructions to the list of instructions to ignore.Bill Wendling2012-05-041-7/+9
| | | | | | | Also combine the code in the 'assert' statement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156155 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper2012-05-041-22/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-047-125/+30
| | | | | | This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-044-89/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass -fcolor-diagnostics when it is supported. This makes a difference whenRafael Espindola2012-05-041-0/+4
| | | | | | using cmake+ninja, since ninja buffers the compiler output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156150 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SuperRegClassIterator for findRepresentativeClass().Jakob Stoklund Olesen2012-05-042-30/+15
| | | | | | | | The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156147 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize SparcInstrInfo before SparcTargetLowering.Jakob Stoklund Olesen2012-05-042-2/+3
| | | | | | | The TargetLowering construction needs to use a valid TargetRegisterInfo instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156146 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SuperRegClassIterator class.Jakob Stoklund Olesen2012-05-042-15/+69
| | | | | | | | This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144 91177308-0d34-0410-b5e6-96231b3b80d8
* A pile of long over-due refactorings here. There are some very, *very*Chandler Carruth2012-05-045-50/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | minor behavior changes with this, but nothing I have seen evidence of in the wild or expect to be meaningful. The real goal is unifying our logic and simplifying the interfaces. A summary of the changes follows: - Make 'callIsSmall' actually accept a callsite so it can handle intrinsics, and simplify callers appropriately. - Nuke a completely bogus declaration of 'callIsSmall' that was still lurking in InlineCost.h... No idea how this got missed. - Teach the 'isInstructionFree' about the various more intelligent 'free' heuristics that got added to the inline cost analysis during review and testing. This mostly surrounds int->ptr and ptr->int casts. - Switch most of the interesting parts of the inline cost analysis that were essentially computing 'is this instruction free?' to use the code metrics routine instead. This way we won't keep duplicating logic. All of this is motivated by the desire to allow other passes to compute a roughly equivalent 'cost' metric for a particular basic block as the inline cost analysis. Sadly, re-using the same analysis for both is really messy because only the actual inline cost analysis is ever going to go to the contortions required for simplification, SROA analysis, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156140 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a FoldingSetVector datastructure which is analogous to a SetVector,Chandler Carruth2012-05-031-0/+105
| | | | | | | | | | but using a FoldingSet underneath and with a largely compatible interface to that of FoldingSet. This can be used anywhere a FoldingSet would be natural, but iteration order is significant. The initial intended use case is in Clang's template specialization lists to preserve instantiation order iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156131 91177308-0d34-0410-b5e6-96231b3b80d8
* PR12729: Change 'llvm-objdump' to display the available targets.Pete Cooper2012-05-031-0/+3
| | | | | | | Patch by Meador Inge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156128 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove accidentally added file.Jakob Stoklund Olesen2012-05-031-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156124 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-033-37/+32
| | | | | | TargetRegisterClass now gives access to the necessary tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen2012-05-032-4/+17
| | | | | | | | This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit SuperRegMasks as part of the existing SubClassMask arrays.Jakob Stoklund Olesen2012-05-032-102/+83
| | | | | | | | | The RC->getSubClassMask() pointer now points to a sequence of register class bit masks. The first bit mask is the normal sub-class mask. The following masks are super-reg class masks used by getMatchingSuperRegClass(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156120 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-036-44/+128
| | | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor the logic for testing whether a basic block is viable for codeChandler Carruth2012-05-032-14/+29
| | | | | | | | | | | extraction into a public interface. Also clean it up and apply it more consistently such that we check for landing pads *anywhere* in the extracted code, not just in single-block extraction. This will be used to guide decisions in passes that are planning to eventually perform a round of code extraction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156114 91177308-0d34-0410-b5e6-96231b3b80d8
* remove calls to calloc if the allocated memory is not used (it was already ↵Nuno Lopes2012-05-033-5/+5
| | | | | | | | being done for malloc) fix a few typos found by Chad in my previous commit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156110 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0318-93/+5036
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
* Add rudimentary CMake logic for detecting Graphviz.Ted Kremenek2012-05-032-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156108 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for calloc to objectsize loweringNuno Lopes2012-05-034-5/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156102 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the type of SubClassMask.Jakob Stoklund Olesen2012-05-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156084 91177308-0d34-0410-b5e6-96231b3b80d8
* Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-19/+67
| | | | | | | | Many register classes only have a few super-registers, so it is not necessary to keep individual bit masks for all possible sub-register indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156083 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the half type to the LLVM IR vim syntax highlighting.Owen Anderson2012-05-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156080 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-032-4/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen2012-05-032-44/+46
| | | | | | | | Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
| | | | | | This adds new instructions for Hexagon V4 architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
* replace 'break's with 'return 0' in visitCallInst code for objectsize, since ↵Nuno Lopes2012-05-031-5/+5
| | | | | | | | there is no need to fallback to visitCallSite. This gives a 0.9% in a test case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156069 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct variable in this example. Pointed out by waynix on IRC.Duncan Sands2012-05-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156067 91177308-0d34-0410-b5e6-96231b3b80d8
* Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper2012-05-031-3/+3
| | | | | | vector elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ↵Craig Topper2012-05-033-22/+37
| | | | | | lower half correctly. Missed in r155982. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-033-17/+28
| | | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156048 91177308-0d34-0410-b5e6-96231b3b80d8
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-034-8/+45
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace cleanup.Bill Wendling2012-05-021-87/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156034 91177308-0d34-0410-b5e6-96231b3b80d8
* [docs] Include the Kaleidescope tutorial in the Sphinx docs build.Daniel Dunbar2012-05-0220-52/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156032 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-022-0/+27
| | | | | | just like it now knows for FMULs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029 91177308-0d34-0410-b5e6-96231b3b80d8
* For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd2012-05-021-4/+4
| | | | | | | | | and Hybrid for 32 bit, since benchmarks show ILP scheduling is better most of the time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the Intel Atom detection code to recognizePreston Gurd2012-05-022-3/+5
| | | | | | | | Lincroft and Medfield. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-022-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add tools/lld to .gitignore.Michael J. Spencer2012-05-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156021 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-022-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
* Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor2012-05-026-4/+4
| | | | | | | be used by clang-tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156000 91177308-0d34-0410-b5e6-96231b3b80d8
* [llvm-c] Make a few function declarations proper prototypesAnders Waldenborg2012-05-021-6/+6
| | | | | | | | | | | This avoids warnings when included in a application that uses -Wstrict-prototypes. e.g: AsmPrinters.def:27:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155997 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-024-68/+171
| | | | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r155853Manman Ren2012-05-022-37/+0
| | | | | | | | | The commit is intended to fix rdar://10961709. But it is the root cause of PR12720. Revert it for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
* [tsan] typo and style (thanks to Nick Lewycky)Kostya Serebryany2012-05-021-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155986 91177308-0d34-0410-b5e6-96231b3b80d8
* The value held in the vector may be RAUW'ed by some of the canonicalizationBill Wendling2012-05-022-2/+53
| | | | | | | | methods. Use a weak value handle to keep up with this. PR12245 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155984 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-025-33/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support ↵Craig Topper2012-05-025-36/+104
| | | | | | for AsmPrinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982 91177308-0d34-0410-b5e6-96231b3b80d8
* Update SmallVector to support move semantics if the host does.John McCall2012-05-022-14/+231
| | | | | | | | | | | | | Note that support for rvalue references does not imply support for the full set of move-related STL operations. I've preserved support for an odd little thing in insert() where we're trying to support inserting a new element from an existing one. If we actually want to support that, there's a lot more we need to do: insert can call either grow or push_back, neither of which is safe against this particular use pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155979 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-14 04:35:13 +0000