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* Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with ↵Hal Finkel2013-07-023-77/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'select' denoms) I'm reverting this commit because: 1. As discussed during review, it needs to be rewritten (to avoid creating and then deleting instructions). 2. This is causing optimizer crashes. Specifically, I'm seeing things like this: While deleting: i1 % Use still stuck around after Def is destroyed: <badref> = select i1 <badref>, i32 0, i32 1 opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed. I'd guess that these will go away once we're no longer creating/deleting instructions here, but just in case, I'm adding a regression test. Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message: InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms Real world code sometimes has the denominator of a 'udiv' be a 'select'. LLVM can handle such cases but only when the 'select' operands are symmetric in structure (both select operands are a constant power of two or a left shift, etc.). This falls apart if we are dealt a 'udiv' where the code is not symetric or if the select operands lead us to more select instructions. Instead, we should treat the LHS and each select operand as a distinct divide operation and try to optimize them independently. If we can to simplify each operation, then we can replace the 'udiv' with, say, a 'lshr' that has a new select with a bunch of new operands for the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185415 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing break statements. Noticed by inspection.Nick Lewycky2013-07-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185414 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in commentTobias Grosser2013-07-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185413 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-026-35/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
* IRVerifier: Correctly check attribute typesTobias Grosser2013-07-021-1/+2
| | | | | | | | | | | Add missing parenthesis such that all and not only the very first attribute is checked. Testing this piece of code is not possible with an LLVM-IR test file, as the LLVM-IR parser has a similar check such that the wrong IR does not even arrive at the verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185408 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-024-56/+70
| | | | | | | | | floating point loads and stores. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
* PR14728: DebugInfo: TLS variables with -gsplit-dwarfDavid Blaikie2013-07-014-17/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185398 91177308-0d34-0410-b5e6-96231b3b80d8
* [APFloat] Ensure that we can properly parse strings that do not have null ↵Michael Gottesman2013-07-012-1/+33
| | | | | | | | terminators. rdar://14323230 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185397 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up some asserts that are within an if statement. This removes the needRichard Trieu2013-07-011-4/+6
| | | | | | | for assert(0 && "text"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185396 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak some comments that referred to the old bias computations.Jakob Stoklund Olesen2013-07-011-13/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185395 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-017-2/+45
| | | | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove floating point computations form SpillPlacement.cpp.Jakob Stoklund Olesen2013-07-013-69/+70
| | | | | | | | | | | | | | | | | | Patch by Benjamin Kramer! Use the BlockFrequency class instead of floats in the Hopfield network computations. This rescales the node Bias field from a [-2;2] float range to two block frequencies BiasN and BiasP pulling in opposite directions. This construct has a more predictable behavior when block frequencies saturate. The per-node scaling factors are no longer necessary, assuming the block frequencies around a bundle are consistent. This patch can cause the register allocator to make different spilling decisions. The differences should be small. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185393 91177308-0d34-0410-b5e6-96231b3b80d8
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix 32-bit PowerPC TLS relocsUlrich Weigand2013-07-012-8/+14
| | | | | | | | | Some TLS relocs were copied incorrectly from ppc64 to ppc32, and some were missing completely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185390 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-017-9/+38
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-013-12/+54
| | | | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a newline.Chad Rosier2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185385 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: clean up usage of Verify.Manman Ren2013-07-012-17/+19
| | | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185383 91177308-0d34-0410-b5e6-96231b3b80d8
* Index: test/CodeGen/PowerPC/reloc-align.llBill Schmidt2013-07-013-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | =================================================================== --- test/CodeGen/PowerPC/reloc-align.ll (revision 0) +++ test/CodeGen/PowerPC/reloc-align.ll (revision 0) @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327) +++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy) @@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI OutStreamer.EmitRawText(StringRef("\tmsync")); return; } + break; + case PPC::LD: + case PPC::STD: + case PPC::LWA: { + // Verify alignment is legal, so we don't create relocations + // that can't be supported. + // FIXME: This test is currently disabled for Darwin. The test + // suite shows a handful of test cases that fail this check for + // Darwin. Those need to be investigated before this sanity test + // can be enabled for those subtargets. + if (!Subtarget.isDarwin()) { + unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; + const MachineOperand &MO = MI->getOperand(OpNum); + if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4) + llvm_unreachable("Global must be word-aligned for LD, STD, LWA!"); + } + // Now process the instruction normally. + break; } + } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); OutStreamer.EmitInstruction(TmpInst); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327) +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy) @@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() { if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { SDLoc dl(GA); const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-013-36/+44
| | | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
* Make PBQP require/preserve MachineLoopInfo - the spiller requires it.Lang Hames2013-07-011-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185378 91177308-0d34-0410-b5e6-96231b3b80d8
* [docs] Amend confusing titleSean Silva2013-07-011-3/+3
| | | | | | | | | | "Writing an LLVM Compiler Backend" can be misinterpreted as meaning "backend" in the sense of "using LLVM as a backend for your compiler for your new language". This new name is less ambiguous. As a bonus, this brings the title in line with the file name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185377 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-012-8/+8
| | | | | | | | | | | that have three register operands. No intended functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Also add "msync" aliasUlrich Weigand2013-07-012-0/+3
| | | | | | | | | This adds an alias for "msync" (which is used on Book E systems instead of "sync"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-015-20/+25
| | | | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix test case to check that mips64 instructions are generated.Akira Hatanaka2013-07-011-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185371 91177308-0d34-0410-b5e6-96231b3b80d8
* Really fix the test. Sorry for the breakage...Anton Korobeynikov2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185369 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the test which relies on uncommitted changeAnton Korobeynikov2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185368 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the build after r185363. Use llvm::next instead of raw next.Cameron Zwarich2013-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185367 91177308-0d34-0410-b5e6-96231b3b80d8
* Add jump tables handling for MSP430.Anton Korobeynikov2013-07-013-0/+65
| | | | | | | Patch by Job Noorman! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185364 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16508.Cameron Zwarich2013-07-012-4/+36
| | | | | | | | | | | | When phis get lowered, destination copies are inserted using an iterator that is determined once for all phis in the block, which BuildMI interprets as a request to insert an instruction directly before the iterator. In the case of a cyclic phi, source copies may also be inserted directly before this iterator, which can cause source copies to be inserted before destination copies. The fix is to keep an iterator to the last phi and then advance it while lowering each phi in order to insert destination copies directly after the phis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185363 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't form PPC CTR loops for over-sized exit countsHal Finkel2013-07-012-0/+26
| | | | | | | | | | Although you can't generate this from C on PPC64, if you have a loop using a 64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had been cauing the PPCCTRLoops pass to assert. Thanks to Joerg Sonnenberger for providing a test case! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185361 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-014-17/+36
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185360 91177308-0d34-0410-b5e6-96231b3b80d8
* (1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.Matt Beaumont-Gay2013-07-014-3/+3
| | | | | | | | | (2) Rename llvm-cov test inputs so the string "llvm-cov" doesn't get substituted by lit within the input filenames on the RUN line. (3) XFAIL llvm-cov.test because it asserts: include/llvm/ADT/SmallVector.h:140: reference llvm::SmallVectorTemplateCommon<llvm::GCOVBlock *, void>::operator[](unsigned int) [T = llvm::GCOVBlock *]: Assertion `begin() + idx < end()' failed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185358 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")Tim Northover2013-07-013-95/+57
| | | | | | | | | Turns out I'd misread the architecture reference manual and thought that was a load/store-store barrier, when it's not. Thanks for pointing it out Eli! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: Scope of a DebugLoc should not be null.Manman Ren2013-07-011-6/+3
| | | | | | | No functionality change. Remove handling for the null case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185354 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix @got references to local symbolsUlrich Weigand2013-07-012-0/+80
| | | | | | | | | | | | | A @got reference must always result in a relocation, so that the linker has a chance to set up the GOT entry, even if the symbol happens to be local. Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces a relocation to be emitted for GOT references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add "wait" instructionUlrich Weigand2013-07-012-4/+15
| | | | | | | | This adds the "wait" instruction and its extended mnemonics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185350 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support "eieio" instructionUlrich Weigand2013-07-013-1/+11
| | | | | | | | | This adds support for the "eieio" instruction to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185349 91177308-0d34-0410-b5e6-96231b3b80d8
* Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it ↵Michael Gottesman2013-07-011-1/+1
| | | | | | in c++ mode instead of c mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185348 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add some existing instructions to ppc64-encoding-bookII.sUlrich Weigand2013-07-011-3/+8
| | | | | | | | | | | | | The test case had a couple of FIXMEs where the instruction is in fact already supported by the back-end. In some other case, while the generic form of the instruction is not yet supported, a specialized form is. This adds tests for those already supported instructions / instruction forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185347 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add variants of "sync" instructionUlrich Weigand2013-07-013-9/+19
| | | | | | | | | This adds support for the "sync $L" instruction with operand, and provides aliases for "lwsync" and "ptesync". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: relax the atomic release barrier to "dmb ishst"Tim Northover2013-07-013-57/+95
| | | | | | | | | | | I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add support for module-scope inline asmJustin Holewinski2013-07-012-0/+20
| | | | | | | Since we were explicitly not calling AsmPrinter::doInitialization, any module-scope inline asm was not being printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185336 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] We dont use NVBuiltin anymoreJustin Holewinski2013-07-012-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185335 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Cut down on physical register defsJustin Holewinski2013-07-013-28/+13
| | | | | | | | We are using virtual registers throughout now, but we still need to keep a few physical registers per class around to keep the infrastructure happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185334 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] 64-bit ADDC/ADDE are not legalJustin Holewinski2013-07-012-0/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185333 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix vector loads from parameters that span multiple loads, and fix ↵Justin Holewinski2013-07-013-156/+22
| | | | | | some typos git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185332 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Handle signext/zeroext attributes properlyJustin Holewinski2013-07-012-19/+41
| | | | | | | | Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value. Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185331 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add support for native SIGN_EXTEND_INREG where availableJustin Holewinski2013-07-013-4/+143
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185330 91177308-0d34-0410-b5e6-96231b3b80d8
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