| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Don't hide the first ELF symbol. | Rafael Espindola | 2013-06-05 | 5 | -3/+39 |
| * | R600: Schedule copy from phys register at beginning of block | Vincent Lejeune | 2013-06-05 | 12 | -11/+42 |
| * | yaml2obj: split out COFF logic into separate file | Sean Silva | 2013-06-05 | 4 | -287/+330 |
| * | [mips] brcond + setgt/setugt instruction selection patterns. | Akira Hatanaka | 2013-06-05 | 2 | -0/+138 |
| * | yaml2obj: add -format=<fmt> to choose input YAML interpretation | Sean Silva | 2013-06-05 | 1 | -11/+39 |
| * | Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit. | Jakub Staszak | 2013-06-05 | 1 | -70/+56 |
| * | [PATCH] Fix VGATHER* operand constraints | Michael Liao | 2013-06-05 | 3 | -1/+23 |
| * | Represent symbols with a SymbolIndex,SectionIndex pair. | Rafael Espindola | 2013-06-05 | 1 | -66/+51 |
| * | ARM sched model: Add more ALU and CMP instructions | Arnold Schwaighofer | 2013-06-05 | 1 | -37/+49 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-05 | 4 | -7/+89 |
| * | ARMInstrInfo: Improve isSwiftFastImmShift | Arnold Schwaighofer | 2013-06-05 | 1 | -0/+2 |
| * | SubtargetEmitter fix | Arnold Schwaighofer | 2013-06-05 | 1 | -1/+1 |
| * | This is a simple patch that changes RRX and RRXS to accept all registers as o... | Mihai Popa | 2013-06-05 | 3 | -1/+48 |
| * | The GNU/HURD is also using the libc. Therefor, endian.h should be included, n... | Sylvestre Ledru | 2013-06-05 | 1 | -1/+1 |
| * | Fix a tblgen subtargetemitter bug, for future Swift support. | Andrew Trick | 2013-06-05 | 1 | -4/+23 |
| * | PR15662: Optimized debug info produces out of order function parameters | David Blaikie | 2013-06-05 | 2 | -3/+104 |
| * | R600: Make sure to schedule AR register uses and defs in the same clause | Tom Stellard | 2013-06-05 | 4 | -4/+72 |
| * | Don't print default values for NumberOfAuxSymbols and AuxiliaryData. | Rafael Espindola | 2013-06-05 | 3 | -2/+11 |
| * | Handle (at least don't crash on) relocations with no symbols. | Rafael Espindola | 2013-06-05 | 1 | -6/+11 |
| * | Move BinaryRef to a new include/llvm/Object/YAML.h file. | Rafael Espindola | 2013-06-05 | 6 | -51/+99 |
| * | Revert "R600: Add a pass that merge Vector Register" | Rafael Espindola | 2013-06-05 | 5 | -400/+0 |
| * | Handle relocations that don't point to symbols. | Rafael Espindola | 2013-06-05 | 19 | -73/+62 |
| * | [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro | Sean Silva | 2013-06-04 | 1 | -1/+1 |
| * | R600: Add a pass that merge Vector Register | Vincent Lejeune | 2013-06-04 | 5 | -0/+400 |
| * | R600: Const/Neg/Abs can be folded to dot4 | Vincent Lejeune | 2013-06-04 | 6 | -47/+213 |
| * | Cortex-R5 can issue Thumb2 integer division instructions. | Evan Cheng | 2013-06-04 | 3 | -21/+25 |
| * | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer | 2013-06-04 | 9 | -1278/+208 |
| * | ARM sched model: Add VFP div instruction on Swift | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+16 |
| * | ARM sched model: Add SIMD/VFP load/store instructions on Swift | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+364 |
| * | ARM sched model: Add integer VFP/SIMD instructions on Swift | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+120 |
| * | ARM sched model: Add integer load/store instructions on Swift | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+209 |
| * | ARM sched model: Add integer arithmetic instructions on Swift | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+155 |
| * | ARM sched model: Cortex A9 - More InstRW sched resources | Arnold Schwaighofer | 2013-06-04 | 1 | -4/+45 |
| * | ARM sched model: Add branch thumb instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -18/+21 |
| * | ARM sched model: Add branch thumb2 instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -11/+15 |
| * | ARM sched model: Add branch instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -27/+35 |
| * | ARM sched model: Add preload thumb2 instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -3/+6 |
| * | ARM sched model: Add preload instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -2/+4 |
| * | ARM sched model: Add more ALU and CMP thumb instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -46/+61 |
| * | ARM sched model: Add more ALU and CMP thumb2 instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -52/+86 |
| * | ARM sched model: Add more ALU and CMP instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -37/+49 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-04 | 4 | -7/+89 |
| * | ARMInstrInfo: Improve isSwiftFastImmShift | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+2 |
| * | SubtargetEmitter fix | Arnold Schwaighofer | 2013-06-04 | 1 | -1/+1 |
| * | Fix link. | Richard Smith | 2013-06-04 | 1 | -1/+1 |
| * | Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., | Venkatraman Govindaraju | 2013-06-04 | 19 | -154/+157 |
| * | IndVarSimplify: check if loop invariant expansion can trap | David Majnemer | 2013-06-04 | 2 | -1/+33 |
| * | ARM: Fix crash in ARM backend inside of ARMConstantIslandPass | David Majnemer | 2013-06-04 | 2 | -0/+15 |
| * | Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options. | Bob Wilson | 2013-06-04 | 3 | -6/+3 |
| * | R600: Swizzle texture/export instructions | Vincent Lejeune | 2013-06-04 | 3 | -25/+131 |
