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* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-022-2/+10
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-021-8/+9
| | | | | | | and tidy up the comment describing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
* remove trailing whitespaceJim Grosbach2010-06-021-75/+75
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105333 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove uses of getCalleeSavedRegClasses from outside theRafael Espindola2010-06-021-5/+4
| | | | | | | backends and removes the virtual declaration. With that out of the way I should be able to cleanup one backend at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't call flush() at a library level which isn't checking for errorsDan Gohman2010-06-011-1/+1
| | | | | | | and doesn't know where the output is going. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105274 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in a comment.Dan Gohman2010-06-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105272 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValueDan Gohman2010-05-291-4/+1
| | | | | | | | shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set doesn't needs its EnableFastISel argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105101 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo.Nick Lewycky2010-05-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105096 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the logic behind CastInst::isNoopCast into a separate static function,Dan Gohman2010-05-281-0/+8
| | | | | | | as is done with most other cast opcode predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105008 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment; vectors are not a special case here.Dan Gohman2010-05-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105006 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TargetRegisterInfo::composeSubRegIndices hook with a defaultJakob Stoklund Olesen2010-05-282-1/+32
| | | | | | | | | | implementation that is correct for most targets. Tablegen will override where needed. Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing subreg indices when sustituting registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
* Move FindAvailableLoadedValue isSafeToLoadUnconditionally out ofDan Gohman2010-05-283-29/+51
| | | | | | | | lib/Transforms/Utils and into lib/Analysis so that Analysis passes can use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104949 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment.Dan Gohman2010-05-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104947 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen2010-05-271-2/+3
| | | | | | | | | optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ancient prototype.Jakob Stoklund Olesen2010-05-271-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104903 91177308-0d34-0410-b5e6-96231b3b80d8
* back out 104862/104869. Can reuse stacksave after all. Very cool.Jim Grosbach2010-05-272-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ParseIRFile and getLazyIRFileModule incoporate the underlyingDan Gohman2010-05-271-2/+4
| | | | | | | | error message string into their own error message string, so that the information isn't lost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104887 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't special-case stdout in llvm::WriteBitcodeToFile; just considerDan Gohman2010-05-271-1/+2
| | | | | | | | it to be the caller's responsibility to provide a stream in binary mode. This fixes a layering violation and avoids an outs() call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104878 91177308-0d34-0410-b5e6-96231b3b80d8
* hook ISD::STACKADDR to an intrinsicJim Grosbach2010-05-271-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104869 91177308-0d34-0410-b5e6-96231b3b80d8
* add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EHJim Grosbach2010-05-271-0/+3
| | | | | | to update the jmpbuf in the presence of VLAs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
* Add basic error checking to MemoryBuffer::getSTDIN.Dan Gohman2010-05-271-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104855 91177308-0d34-0410-b5e6-96231b3b80d8
* remove incorrect GCCBuiltin<> usageJim Grosbach2010-05-271-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104833 91177308-0d34-0410-b5e6-96231b3b80d8
* typoGabor Greif2010-05-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104832 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Lint printing warnings multiple times. Remove the ErrorStrDan Gohman2010-05-261-2/+1
| | | | | | | | option from lintModule, which was an artifact from being based on Verifier code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104765 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add TargetMachine support for setting the value of MCRelaxAll withDaniel Dunbar2010-05-261-1/+11
| | | | | | -filetype=obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
* Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen2010-05-261-0/+4
| | | | | | | This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry inJim Grosbach2010-05-262-3/+8
| | | | | | | | ISD::. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the check for "calls setjmp" to SelectionDAGISel so that it can be used byBill Wendling2010-05-261-1/+17
| | | | | | | more than just the stack slot coloring algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104722 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the use of PriorityQueue and just use a std::vector,Dan Gohman2010-05-261-13/+5
| | | | | | | | | implementing pop with a linear search for a "best" element. The priority queue was a neat idea, but in practice the comparison functions depend on dynamic information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104718 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix indentation.Dan Gohman2010-05-261-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104717 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Change RelaxInstruction to only take the input and output instructions.Daniel Dunbar2010-05-261-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query itDaniel Dunbar2010-05-261-4/+1
| | | | | | before encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104707 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-11/+17
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Eliminate MCAsmFixup, replace with MCFixup.Daniel Dunbar2010-05-264-47/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104699 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Simplify MCFixup and increase the available offset size.Daniel Dunbar2010-05-261-29/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104698 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Use accessors for access to MCAsmFixup.Daniel Dunbar2010-05-261-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104697 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Eliminate MCFragment vtable, which was unnecessary.Daniel Dunbar2010-05-261-12/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104689 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r104655 as it's breaking the bots.Eric Christopher2010-05-261-14/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104664 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-17/+11
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-262-10/+7
| | | | | | | base class, since all the implementations are the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104659 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete an unused function.Dan Gohman2010-05-262-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104658 91177308-0d34-0410-b5e6-96231b3b80d8
* Dale and Evan suggested putting the "check for setjmp" much earlier in theBill Wendling2010-05-261-1/+14
| | | | | | | machine code generation. That's a good idea, so I made it so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104655 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-11/+17
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Start adding mach-o tls reloc support.Eric Christopher2010-05-261-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104651 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the SuperregHashTable. It is essentially the same as SubregHashTable.Jakob Stoklund Olesen2010-05-251-17/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-5/+1
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure aeskeygenassist uses an unsigned immediate field.Eric Christopher2010-05-251-2/+2
| | | | | | | Fixes rdar://8017638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
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