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* Fix PR4076. Correctly create live interval of physical register with ↵Evan Cheng2009-04-271-10/+20
| | | | | | two-address update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70245 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR4056. It's possible a physical register def is dead if its implicit ↵Evan Cheng2009-04-271-2/+2
| | | | | | use is deleted by two-address pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70213 91177308-0d34-0410-b5e6-96231b3b80d8
* It has finally happened. Spiller is now using live interval info.Evan Cheng2009-04-211-3/+3
| | | | | | | This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69743 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a linearscan register allocation optimization. When the register ↵Evan Cheng2009-04-201-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g. %reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0] %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0] %reg1486<def> = MOV32rr %reg1506 %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead> %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0] => %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0] %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0] %reg1486<def> = MOV32rr %reg1506 %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead> %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0] From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block. Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused. This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69585 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't abort on an aliasing physical register that does not haveDan Gohman2009-04-131-1/+1
| | | | | | | a live interval. This is needed for some upcoming subreg changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68956 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson2009-04-091-1/+1
| | | | | | | | | | | | | register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman2009-04-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assign a new stack slot if the pre-alloc splitter already assigned one.Owen Anderson2009-03-261-2/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67764 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3391 and PR3864. Reg allocator infinite looping.Evan Cheng2009-03-231-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67544 91177308-0d34-0410-b5e6-96231b3b80d8
* Model inline asm constraint which ties an input to an output register as ↵Evan Cheng2009-03-231-4/+6
| | | | | | machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the Win32 VS2008 build:Sebastian Redl2009-03-191-1/+1
| | | | | | | | | | - Make type declarations match the struct/class keyword of the definition. - Move AddSignalHandler into the namespace where it belongs. - Correctly call functions from template base. - Some other small changes. With this patch, LLVM and Clang should build properly and with far less noise under VS2008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67347 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.Evan Cheng2009-03-191-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67335 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix how livein live intervals are handled. Previously it could end at MBB ↵Evan Cheng2009-03-051-4/+9
| | | | | | start. Sorry, no small test case possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66129 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3486. Fix a bug in code that manually patch physical register live ↵Evan Cheng2009-02-081-2/+9
| | | | | | interval after its sub-register is coalesced with a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64082 91177308-0d34-0410-b5e6-96231b3b80d8
* Exit with nice warnings when register allocator run out of registers.Evan Cheng2009-01-291-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63267 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-10/+10
| | | | | | sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
* The coalescer does not coalesce a virtual register to a physical register if ↵Evan Cheng2009-01-071-3/+49
| | | | | | | | | | | | | | | any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61847 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3149. If an early clobber def is a physical register and it is tied to ↵Evan Cheng2008-12-191-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. 172 %ECX<def> = MOV32rr %reg1039<kill> 180 INLINEASM <es:subl $5,$1 sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>, 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0 188 %EAX<def> = MOV32rr %EAX<kill> 196 %ECX<def> = MOV32rr %ECX<kill> 204 %ECX<def> = MOV32rr %ECX<kill> 212 %EAX<def> = MOV32rr %EAX<kill> 220 %EAX<def> = MOV32rr %EAX 228 %reg1039<def> = MOV32rr %ECX<kill> The early clobber operand ties ECX input to the ECX def. The live interval of ECX is represented as this: %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47) The right way to represent this is something like %reg20,inf = [46,47:2)[174,182:1)[181:230:0) 0@174-(182) 1@181-230 @2@46-(47) Of course that won't work since that means overlapping live ranges defined by two val#. The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61259 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify some comments.Dan Gohman2008-12-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60683 91177308-0d34-0410-b5e6-96231b3b80d8
* Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from ↵Evan Cheng2008-12-051-9/+11
| | | | | | constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60596 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Evan Cheng2008-12-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60592 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.Dan Gohman2008-12-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60586 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* LiveRanges are represented as half-open ranges. Fix the findLiveInMBBs codeDan Gohman2008-11-261-1/+1
| | | | | | | | and the LiveInterval.h top-level comment and accordingly. This fixes blocks having spurious live-in registers in boundary cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60092 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence unused variable warnings.Devang Patel2008-11-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59841 91177308-0d34-0410-b5e6-96231b3b80d8
* Use find_first/find_next to iterate through all the set bits in aDan Gohman2008-11-131-8/+7
| | | | | | | BitVector, instead of manually testing each bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59246 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some debugging code made redundant by the change to doDan Gohman2008-11-121-8/+0
| | | | | | | | coalescing as a separate pass rather than inside of LiveIntervalAnalysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59146 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rewrite code that update register live interval that's split.Evan Cheng2008-10-291-3/+24
| | | | | | | | - Create and update spill slot live intervals. - Lots of bug fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58367 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR2634. Create new virtual registers from spills early so that weDavid Greene2008-10-271-8/+19
| | | | | | | | can give it the same stack slot as the spilled interval if it is folded. This prevents the fold/unfold code from pointing to the wrong register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58255 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid splitting an interval multiple times; avoid splitting ↵Evan Cheng2008-10-241-0/+9
| | | | | | re-materializable val# (for now). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58068 91177308-0d34-0410-b5e6-96231b3b80d8
* By min, I mean max.Evan Cheng2008-10-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57766 91177308-0d34-0410-b5e6-96231b3b80d8
* When creating intervals, leave min(1, numdefs) holes after each instruction.Evan Cheng2008-10-181-5/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57765 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to enable StrongPHIElimination, for ease of testing.Owen Anderson2008-10-071-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57259 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-11/+11
| | | | | | | isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a simple error in renumbering kill markaers, that took an inordinant ↵Owen Anderson2008-09-301-1/+1
| | | | | | amount of time to track down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56889 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 56835 along with header file changes.Evan Cheng2008-09-301-5/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56848 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert commit 56835 since it breaks the build.Duncan Sands2008-09-301-15/+5
| | | | | | | | | | | "If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56837 91177308-0d34-0410-b5e6-96231b3b80d8
* If a re-materializable instruction has a register operand, the spiller will ↵Evan Cheng2008-09-301-5/+15
| | | | | | change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56835 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of earlyclobber handling. Approach theDale Johannesen2008-09-241-13/+15
| | | | | | | | | | | | RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8
* Fetch the starting index of the block when assigning intervals. This gets ↵Owen Anderson2008-09-211-2/+2
| | | | | | | | | live-in indices correct in the presence of things like EH labels. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56410 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysisDale Johannesen2008-09-191-71/+4
| | | | | | | | | and redo as linked list walk. Logic moved into RA. Per review feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56326 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bit to mark operands of asm's that conflictDale Johannesen2008-09-171-2/+80
| | | | | | | | | | | with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
* Live intervals for live-in registers should begin at the beginning of a ↵Owen Anderson2008-09-151-7/+11
| | | | | | | | | | basic block, not at the first instruction. Also, their valno's should have an unknown def. This has no effect currently, but was causing issues when StrongPHIElimination was enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56231 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-3/+3
| | | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the fast-path spilling code to attempt folding, but still leaving out ↵Owen Anderson2008-08-191-59/+68
| | | | | | remat and splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55012 91177308-0d34-0410-b5e6-96231b3b80d8
* The fast-path still needs to set kill markers and spill/restore points as ↵Owen Anderson2008-08-191-0/+3
| | | | | | | | | | appropriate. With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with the SimpleSpiller and this fast-path enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55000 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to enable the fast spilling path.Owen Anderson2008-08-191-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54958 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few more bugs:Owen Anderson2008-08-181-3/+8
| | | | | | | | 1) Assign stack slots to new temporaries. 2) Don't insert an interval into the return vector more than once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54956 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix several bugs in the new fast-path:Owen Anderson2008-08-181-16/+16
| | | | | | | | | 1) Remove an incorrect assertion. 2) Set the stack slot weight properly. 3) Resize the VirtRegMap when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54949 91177308-0d34-0410-b5e6-96231b3b80d8
* Clients of addIntervalForSpills expect the added intervals to be returned ↵Owen Anderson2008-08-181-0/+9
| | | | | | sorted by starting index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54939 91177308-0d34-0410-b5e6-96231b3b80d8
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