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path: root/lib/CodeGen/MachineScheduler.cpp
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* misched: Added handleMove support for updating all kill flags, not just for a...Andrew Trick2012-10-161-1/+1
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-151-20/+104
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-10/+20
* misched: avoid scheduling an instruction twice.Andrew Trick2012-10-081-25/+29
* misched: add a hook for custom DAG postprocessing.Andrew Trick2012-09-141-0/+9
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-111-256/+100
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
* Simplify the computeOperandLatency API.Andrew Trick2012-08-231-10/+8
* Add a getName function to MachineFunction. Use it in places that previously d...Craig Topper2012-08-221-1/+1
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-1/+2
* misched: allow NULL InstrItineraries.Andrew Trick2012-07-021-0/+1
* misched: avoid scheduling instructions that can't be dispatched.Andrew Trick2012-06-291-6/+29
* misched: count micro-ops toward the issue limit.Andrew Trick2012-06-291-10/+19
* Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer2012-06-161-1/+7
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
* Move RegisterPressure.h.Andrew Trick2012-06-061-1/+1
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-31/+81
* misched: comments from code review.Andrew Trick2012-06-051-3/+3
* misched: trace formattingAndrew Trick2012-05-251-6/+5
* Silence unused variable warnings from when assertions are disabled.Kaelyn Uhrain2012-05-241-0/+2
* misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick2012-05-241-2/+16
* misched: Trace regpressure.Andrew Trick2012-05-241-2/+4
* misched: Give each ReadyQ a unique IDAndrew Trick2012-05-241-36/+45
* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-241-49/+232
* misched: Release bottom roots in reverse order.Andrew Trick2012-05-241-9/+23
* misched: rename ReadyQ classAndrew Trick2012-05-241-8/+9
* misched: copy comments so compareRPDelta is readable by itself.Andrew Trick2012-05-241-1/+4
* commentsAndrew Trick2012-05-171-2/+3
* misched: trace ReadyQ.Andrew Trick2012-05-171-0/+8
* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-171-36/+184
* commentAndrew Trick2012-05-171-2/+0
* misched: fix liveness iteratorsAndrew Trick2012-05-171-10/+16
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
* misched: Introducing Top and Bottom register pressure trackers during schedul...Andrew Trick2012-05-101-10/+71
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-241-2/+12
* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-241-0/+25
* misched: ignore debug values during schedulingAndrew Trick2012-04-241-6/+31
* misched: DAG builder support for tracking register pressure within the curren...Andrew Trick2012-04-241-4/+48
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-011-0/+1
* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-211-0/+1
* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-211-0/+6
* misched: cleanup main loopAndrew Trick2012-03-211-10/+14
* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
* Silence operator precedence warnings.Benjamin Kramer2012-03-141-3/+3