| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update LLVM for 3.5 rebase (r209712). | Stephen Hines | 2014-05-29 | 1 | -4315/+6854 |
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -149/+948 |
| * | Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. This | Tim Northover | 2013-12-09 | 1 | -0/+6 |
| * | Merging r196456: | Bill Wendling | 2013-12-08 | 1 | -1/+24 |
| * | Merging r196190: | Bill Wendling | 2013-12-08 | 1 | -1/+1 |
| * | Merging r195932: | Bill Wendling | 2013-12-01 | 1 | -7/+7 |
| * | Merging r195905: | Bill Wendling | 2013-12-01 | 1 | -2/+2 |
| * | Merging r195843: | Bill Wendling | 2013-12-01 | 1 | -0/+17 |
| * | Merging r195716: | Bill Wendling | 2013-11-26 | 1 | -6/+159 |
| * | Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. | Hao Liu | 2013-11-19 | 1 | -34/+183 |
| * | Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors. | Hao Liu | 2013-11-18 | 1 | -2/+38 |
| * | Implement aarch64 neon instruction class SIMD misc. | Kevin Qin | 2013-11-14 | 1 | -0/+67 |
| * | Implement AArch64 Neon instruction set Bitwise Extract. | Jiangning Liu | 2013-11-06 | 1 | -86/+113 |
| * | Implement AArch64 post-index vector load/store multiple N-element structure c... | Hao Liu | 2013-11-05 | 1 | -0/+135 |
| * | Implemented aarch64 neon intrinsic vcopy_lane with float type. | Kevin Qin | 2013-11-05 | 1 | -3/+6 |
| * | [AArch64] Make the use of FP instructions optional, but enabled by default. | Amara Emerson | 2013-10-31 | 1 | -21/+29 |
| * | [AArch64] Add support for NEON scalar floating-point compare instructions. | Chad Rosier | 2013-10-30 | 1 | -1/+4 |
| * | [AArch64] Implement FrameAddr and ReturnAddr | Weiming Zhao | 2013-10-29 | 1 | -0/+41 |
| * | [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. | Amara Emerson | 2013-10-24 | 1 | -2/+6 |
| * | Implement aarch64 neon instruction set AdvSIMD (copy). | Kevin Qin | 2013-10-11 | 1 | -4/+194 |
| * | Implement AArch64 vector load/store multiple N-element structure class SIMD(l... | Hao Liu | 2013-10-10 | 1 | -0/+54 |
| * | Revert "Implement AArch64 vector load/store multiple N-element structure clas... | Rafael Espindola | 2013-10-10 | 1 | -54/+0 |
| * | Implement AArch64 vector load/store multiple N-element structure class SIMD(l... | Hao Liu | 2013-10-10 | 1 | -0/+54 |
| * | [AArch64] Add support for NEON scalar arithmetic instructions: | Chad Rosier | 2013-10-07 | 1 | -0/+3 |
| * | Implement aarch64 neon instruction set AdvSIMD (3V elem). | Jiangning Liu | 2013-10-04 | 1 | -0/+45 |
| * | Initial support for Neon scalar instructions. | Jiangning Liu | 2013-09-24 | 1 | -0/+11 |
| * | AArch64: use RegisterOperand for NEON registers. | Tim Northover | 2013-09-13 | 1 | -17/+13 |
| * | Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instruc... | Hao Liu | 2013-09-04 | 1 | -8/+82 |
| * | Clang and AArch64 backend patches to support shll/shl and vmovl instructions ... | Hao Liu | 2013-08-15 | 1 | -0/+52 |
| * | Update makeLibCall to return both the call and the chain associated with the ... | Michael Gottesman | 2013-08-13 | 1 | -1/+1 |
| * | AArch64: add initial NEON support | Tim Northover | 2013-08-01 | 1 | -1/+521 |
| * | AArch64: fix even more JIT failures | Tim Northover | 2013-07-25 | 1 | -1/+1 |
| * | Make some arrays 'static const' | Craig Topper | 2013-07-15 | 1 | -10/+10 |
| * | Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s... | Craig Topper | 2013-07-14 | 1 | -3/+3 |
| * | AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all | Stephen Lin | 2013-07-09 | 1 | -0/+21 |
| * | Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. | Jakob Stoklund Olesen | 2013-07-04 | 1 | -3/+0 |
| * | Revert r185595-185596 which broke buildbots. | Jakob Stoklund Olesen | 2013-07-04 | 1 | -0/+3 |
| * | Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. | Jakob Stoklund Olesen | 2013-07-03 | 1 | -3/+0 |
| * | The getRegForInlineAsmConstraint function should only accept MVT value types. | Chad Rosier | 2013-06-22 | 1 | -1/+1 |
| * | Don't cache the instruction info and register info objects. | Bill Wendling | 2013-06-07 | 1 | -8/+4 |
| * | Order CALLSEQ_START and CALLSEQ_END nodes. | Andrew Trick | 2013-05-29 | 1 | -3/+4 |
| * | Track IR ordering of SelectionDAG nodes 2/4. | Andrew Trick | 2013-05-25 | 1 | -29/+29 |
| * | Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. | Michael J. Spencer | 2013-05-24 | 1 | -1/+1 |
| * | Add LLVMContext argument to getSetCCResultType | Matt Arsenault | 2013-05-18 | 1 | -1/+1 |
| * | AArch64: assert code model is small for TLS accesses | Tim Northover | 2013-05-04 | 1 | -0/+2 |
| * | AArch64: support large code model for jump-tables | Tim Northover | 2013-05-04 | 1 | -5/+18 |
| * | AArch64: implement support for blockaddress in large code model | Tim Northover | 2013-05-04 | 1 | -11/+20 |
| * | AArch64: implement large code model access to global variables. | Tim Northover | 2013-05-04 | 1 | -5/+43 |
| * | Remove unused ShouldFoldAtomicFences flag. | Tim Northover | 2013-04-20 | 1 | -4/+0 |
| * | AArch64: remove barriers from AArch64 atomic operations. | Tim Northover | 2013-04-08 | 1 | -104/+38 |
