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* Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for ↵NAKAMURA Takumi2013-08-061-0/+2
| | | | | | | | | each corresponding CodeGen. Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel. It races to emit *.inc files simultaneously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: add initial NEON supportTim Northover2013-08-0117-35/+2649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: fix even more JIT failuresTim Northover2013-07-252-4/+4
| | | | | | | The last patch corrected some issues, but constant-pool entries had actual codegen bugs in the large memory model (which MCJIT uses). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187126 91177308-0d34-0410-b5e6-96231b3b80d8
* Make some arrays 'static const'Craig Topper2013-07-153-43/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186311 91177308-0d34-0410-b5e6-96231b3b80d8
* Add const qualifier to some static arrays.Craig Topper2013-07-152-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186309 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-3/+3
| | | | | | size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-092-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a OwningPtr instead of a manual delete.Rafael Espindola2013-07-041-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185673 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix leak. Should bring back the valgrind bot.Rafael Espindola2013-07-041-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185663 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-3/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+3
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-3/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove address spaces from MC.Rafael Espindola2013-07-023-7/+6
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-012-10/+14
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185360 91177308-0d34-0410-b5e6-96231b3b80d8
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-182-6/+6
| | | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-164-59/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-076-28/+22
| | | | | | | These objects are internal to the TargetMachine object and may change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-6/+6
| | | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-6/+6
| | | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-3/+4
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: clarify -help messageTim Northover2013-05-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182804 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-253-41/+41
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-243-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-1/+1
| | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Disassembled CFG reconstruction.Ahmed Bougacha2013-05-241-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds on some existing code to do CFG reconstruction from a disassembled binary: - MCModule represents the binary, and has a list of MCAtoms. - MCAtom represents either disassembled instructions (MCTextAtom), or contiguous data (MCDataAtom), and covers a specific range of addresses. - MCBasicBlock and MCFunction form the reconstructed CFG. An MCBB is backed by an MCTextAtom, and has the usual successors/predecessors. - MCObjectDisassembler creates a module from an ObjectFile using a disassembler. It first builds an atom for each section. It can also construct the CFG, and this splits the text atoms into basic blocks. MCModule and MCAtom were only sketched out; MCFunction and MCBB were implemented under the experimental "-cfg" llvm-objdump -macho option. This cleans them up for further use; llvm-objdump -d -cfg now generates graphviz files for each function found in the binary. In the future, MCObjectDisassembler may be the right place to do "intelligent" disassembly: for example, handling constant islands is just a matter of splitting the atom, using information that may be available in the ObjectFile. Also, better initial atom formation than just using sections is possible using symbols (and things like Mach-O's function_starts load command). This brings two minor regressions in llvm-objdump -macho -cfg: - The printing of a relocation's referenced symbol. - An annotation on loop BBs, i.e., which are their own successor. Relocation printing is replaced by the MCSymbolizer; the basic CFG annotation will be superseded by more related functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182628 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: add CMake dependency to fix very parallel buildsTim Northover2013-05-181-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182190 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-182-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove addFrameMove.Rafael Espindola2013-05-161-11/+13
| | | | | | | Now that we have good testing, remove addFrameMove and create cfi instructions directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182052 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the MachineMove class.Rafael Espindola2013-05-132-4/+6
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-111-5/+4
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused argument.Rafael Espindola2013-05-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: enable MCJIT and tests now that everything passes.Tim Northover2013-05-041-1/+1
| | | | | | | This removes dire warnings about AArch64 being unsupported and enables the tests when appropriate on this platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement first relocation required for MCJITTim Northover2013-05-041-0/+6
| | | | | | | | | | | R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so is required to compile any function without the "nounwind" attribute. This change implements very basic infrastructure in the RuntimeDyldELF file and allows (for example) the test-shift.ll MCJIT test to pass on AArch64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181131 91177308-0d34-0410-b5e6-96231b3b80d8
* Build system changes to enable MCJIT on AArch64Tim Northover2013-05-041-1/+1
| | | | | | | These changes just allow AArch64 to take part in the MCJIT world when built correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181130 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: assert code model is small for TLS accessesTim Northover2013-05-041-0/+2
| | | | | | | Supporting TLS in the large memory model is rather difficult at the moment, so make sure no-one gets into difficulties by mistake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181121 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: support literal pool access in large memory model.Tim Northover2013-05-041-20/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: support large code model for jump-tablesTim Northover2013-05-041-5/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement support for blockaddress in large code modelTim Northover2013-05-041-11/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181118 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement large code model access to global variables.Tim Northover2013-05-047-14/+126
| | | | | | | | | | | | | | The MOVZ/MOVK instruction sequence may not be the most efficient (a literal-pool load could be better) but adding that would require reinstating the ConstantIslands pass. For now the sequence is correct, and that's enough. Beware, as of commit GNU ld does not appear to support the relocations needed for this. Its primary purpose (for now) will be to support JITed code, since in that case there is no guarantee of where your code will end up in memory relative to external symbols it references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64 InstrFormats:Jia Liu2013-04-281-1/+1
| | | | | | | | delete blank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180687 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: remove unnecessary check that RS is validTim Northover2013-04-231-2/+3
| | | | | | | | AArch64 always demands a register-scavenger, so the pointer should never be NULL. However, in the spirit of paranoia, we'll assert it before use just in case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180080 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: remove useless commentTim Northover2013-04-201-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179952 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused ShouldFoldAtomicFences flag.Tim Northover2013-04-201-4/+0
| | | | | | | | I think it's almost impossible to fold atomic fences profitably under LLVM/C++11 semantics. As a result, this is now unused and just cluttering up the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for subsections to the ELF assembler. Fixes PR8717.Peter Collingbourne2013-04-171-4/+5
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D598 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix undefined behavior in AArch64David Majnemer2013-04-111-7/+11
| | | | | | | | | A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179317 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: remove barriers from AArch64 atomic operations.Tim Northover2013-04-083-145/+193
| | | | | | | | I've managed to convince myself that AArch64's acquire/release instructions are sufficient to guarantee C++11's required semantics, even in the sequentially-consistent case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179005 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-032-0/+432
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: switch patterns to be type-based rather than RegClass-basedTim Northover2013-04-031-503/+492
| | | | | | | It's a bit of churn in the blame log, but I think there are real benefits to the newer system so I'm making the change in one go. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178633 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement GICv3 system registersTim Northover2013-03-282-5/+141
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
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