| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ARM refactor more NEON VLD/VST instructions to use composite physregs | Jim Grosbach | 2012-03-06 | 1 | -8/+7 |
| * | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach | 2012-03-05 | 1 | -45/+37 |
| * | Remove unused variable. | Duncan Sands | 2012-02-23 | 1 | -1/+0 |
| * | Optimize a couple of common patterns involving conditional moves where the false | Evan Cheng | 2012-02-23 | 1 | -3/+115 |
| * | Convert assert(0) to llvm_unreachable | Craig Topper | 2012-02-07 | 1 | -2/+1 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 | 1 | -1/+0 |
| * | ARM updating VST2 pseudo-lowering fixed vs. register update. | Jim Grosbach | 2012-01-10 | 1 | -1/+1 |
| * | ARM NEON assmebly parsing for VLD2 to all lanes instructions. | Jim Grosbach | 2011-12-21 | 1 | -3/+14 |
| * | ARM NEON refactor VST2 w/ writeback instructions. | Jim Grosbach | 2011-12-14 | 1 | -6/+15 |
| * | ARM assembly parsing and encoding for VLD2 with writeback. | Jim Grosbach | 2011-12-09 | 1 | -8/+19 |
| * | ARM assembly parsing and encoding for four-register VST1. | Jim Grosbach | 2011-11-29 | 1 | -1/+2 |
| * | ARM assembly parsing and encoding for three-register VST1. | Jim Grosbach | 2011-11-29 | 1 | -1/+2 |
| * | ARM VST1 w/ writeback assembly parsing and encoding. | Jim Grosbach | 2011-10-31 | 1 | -9/+33 |
| * | Also set addrmode6 alignment when align==size. | Jakob Stoklund Olesen | 2011-10-27 | 1 | -1/+1 |
| * | ARM isel for vld1, opcode selection for register stride post-index pseudos. | Jim Grosbach | 2011-10-27 | 1 | -0/+4 |
| * | ARM refactor am6offset usage for VLD1. | Jim Grosbach | 2011-10-24 | 1 | -8/+34 |
| * | Fix misc warnings. Patch by Joe Abbey. | Eli Friedman | 2011-10-18 | 1 | -1/+0 |
| * | Reapply r141365 now that PR11107 is fixed. | Bill Wendling | 2011-10-10 | 1 | -0/+66 |
| * | Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to | Bill Wendling | 2011-10-10 | 1 | -66/+0 |
| * | Disable ABS optimization for Thumb1 target, we don't have necessary instructi... | Anton Korobeynikov | 2011-10-08 | 1 | -0/+3 |
| * | Peephole optimization for ABS on ARM. | Anton Korobeynikov | 2011-10-07 | 1 | -0/+63 |
| * | Always merge profitable shifts on A9, not just when they have a single use. | Cameron Zwarich | 2011-10-05 | 1 | -6/+2 |
| * | Remove a check from ARM shifted operand isel helper methods, which were blocking | Cameron Zwarich | 2011-10-05 | 1 | -10/+0 |
| * | Add braces around something that throws me for a loop. | Cameron Zwarich | 2011-10-05 | 1 | -1/+2 |
| * | There is no point in setting out-parameters for a ComplexPattern function when | Cameron Zwarich | 2011-10-05 | 1 | -1/+0 |
| * | Also match negative offsets for addrmode3 and addrmode5. | Jakob Stoklund Olesen | 2011-09-23 | 1 | -2/+2 |
| * | Tidy up a few 80 column violations. | Jim Grosbach | 2011-09-13 | 1 | -4/+4 |
| * | When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ... | Owen Anderson | 2011-08-31 | 1 | -1/+8 |
| * | 64-bit atomic cmpxchg for ARM. | Eli Friedman | 2011-08-31 | 1 | -7/+13 |
| * | Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. | Eli Friedman | 2011-08-31 | 1 | -0/+32 |
| * | addrmode_imm12 and addrmode2_offset encode their immediate values differently... | Owen Anderson | 2011-08-29 | 1 | -4/+28 |
| * | Fix ARM codegen breakage caused by r138653. | Owen Anderson | 2011-08-26 | 1 | -6/+15 |
| * | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson | 2011-08-26 | 1 | -4/+4 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 | 1 | -2/+3 |
| * | ARM refactor indexed store instructions. | Jim Grosbach | 2011-08-05 | 1 | -2/+5 |
| * | ARM parsing and encoding of SBFX and UBFX. | Jim Grosbach | 2011-07-27 | 1 | -2/+4 |
| * | Split am2offset into register addend and immediate addend forms, necessary fo... | Owen Anderson | 2011-07-26 | 1 | -13/+40 |
| * | Fix test failures caused by my so_reg refactoring. | Owen Anderson | 2011-07-22 | 1 | -2/+2 |
| * | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson | 2011-07-21 | 1 | -11/+9 |
| * | Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowi... | Owen Anderson | 2011-07-21 | 1 | -15/+52 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -10/+12 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -3/+3 |
| * | Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi... | Owen Anderson | 2011-06-16 | 1 | -12/+23 |
| * | Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs | Bruno Cardoso Lopes | 2011-05-28 | 1 | -0/+105 |
| * | Zap a couple now-unused functions. | Eli Friedman | 2011-04-29 | 1 | -10/+0 |
| * | This patch combines several changes from Evan Cheng for rdar://8659675. | Bob Wilson | 2011-04-19 | 1 | -1/+1 |
| * | Do not lose mem_operands while lowering VLD / VST intrinsics. | Evan Cheng | 2011-04-19 | 1 | -4/+29 |
| * | Reduce code duplication. | Owen Anderson | 2011-03-18 | 1 | -31/+13 |
| * | Generate a VTBL instruction instead of a series of loads and stores when we | Bill Wendling | 2011-03-14 | 1 | -0/+29 |
| * | Remove dead code. These ARM instruction definitions no longer exist. | Jim Grosbach | 2011-03-11 | 1 | -1/+1 |
