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path: root/lib/Target/ARM/ARMInstrFormats.td
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* Renaming for consistency.Evan Cheng2009-06-271-6/+6
* Change thumb2 instruction definitions so if-converter so add predicate operan...Evan Cheng2009-06-251-7/+38
* Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-b...Evan Cheng2009-06-231-0/+22
* Initial Thumb2 support. Majority of the work is done by David Goodwin. There areEvan Cheng2009-06-231-0/+20
* Add support for ARM's Advanced SIMD (NEON) instruction set.Bob Wilson2009-06-221-8/+111
* Handle the rest of pseudo instructions.Evan Cheng2008-11-131-29/+29
* Fix pre- and post-indexed load / store encoding bugs.Evan Cheng2008-11-131-19/+21
* Consolidate formats; fix FCMPED etc. encodings.Evan Cheng2008-11-121-22/+19
* Fix VFP conversion instruction encodings.Evan Cheng2008-11-121-19/+30
* Fix FMDRR encoding.Evan Cheng2008-11-111-6/+15
* Encode VFP load / store instructions.Evan Cheng2008-11-111-60/+53
* Encode VFP conversion instructions.Evan Cheng2008-11-111-1/+20
* Encode VFP arithmetic instructions.Evan Cheng2008-11-111-2/+98
* Jump table JIT support. Work in progress.Evan Cheng2008-11-071-26/+2
* Encode misc arithmetic instructions.Evan Cheng2008-11-071-0/+8
* Encode extend instructions; more clean up.Evan Cheng2008-11-061-10/+20
* - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.Evan Cheng2008-11-061-43/+13
* Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 enc...Evan Cheng2008-11-061-126/+123
* Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.Evan Cheng2008-11-061-20/+27
* Fix encoding of multiple instructions with 3 src operands; also handle smmul,...Evan Cheng2008-11-061-32/+38
* Encode pic load / store instructions; fix some encoding bugs.Evan Cheng2008-11-051-24/+40
* Restructure ARM code emitter to use instruction formats instead of addressing...Evan Cheng2008-11-051-38/+39
* LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.Evan Cheng2008-11-041-1/+0
* Add binary encoding support for multiply instructions. Some blanks left to fi...Jim Grosbach2008-11-031-0/+22
* Update ARM Insn encoding to get endian-ness to match the documentation (31-0 ...Jim Grosbach2008-10-141-23/+19
* Fix addrmode1 instruction encodings; fix bx_ret encoding.Evan Cheng2008-09-171-7/+0
* Specify instruction encoding using range list to avoid endianess issues.Evan Cheng2008-09-171-25/+26
* Revert 56176. All those instruction formats are still needed.Evan Cheng2008-09-131-9/+20
* Eliminate unnecessary instruction formats.Evan Cheng2008-09-121-20/+9
* Addrmode 1 S bit can be dynamically set. Look for CPSR def.Evan Cheng2008-09-121-2/+0
* Control flow instruction encodings.Evan Cheng2008-09-011-12/+66
* ldm / stm instruction encodings.Evan Cheng2008-09-011-3/+25
* AXI2 and AXI3 instruction encodings.Evan Cheng2008-09-011-0/+84
* Reorganize instruction formats again; AXI1 encoding.Evan Cheng2008-09-011-34/+35
* addrmode3 instruction encodings.Evan Cheng2008-09-011-28/+194
* Reorganize some instruction format definitions. No functionality change.Evan Cheng2008-09-011-18/+29
* Rest of addrmode2 instruction encodings.Evan Cheng2008-09-011-4/+96
* Addr2 word / byte load encodings.Evan Cheng2008-08-311-1/+21
* Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng2008-08-311-4/+5
* addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 e...Evan Cheng2008-08-291-3/+10
* More refactoring.Evan Cheng2008-08-291-0/+55
* Refactor ARM instruction format definitions into a separate file. No function...Evan Cheng2008-08-281-0/+228
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