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path: root/lib/Target/ARM/ARMInstrInfo.td
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* [ARMv8]Joey Gouly2013-08-281-3/+3
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-271-4/+42
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-1/+6
* ARM: make sure ARM-mode pseudo-inst requires IsARMTim Northover2013-08-231-1/+1
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-23/+32
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-211-0/+5
* ARMv8: SWP and SWPB are obsoleted on ARMv8.Joey Gouly2013-08-131-2/+6
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patc...Silviu Baranga2013-07-291-1/+3
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-221-12/+0
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-161-7/+50
* ARM: Add a pack pattern for matching arithmetic shift rightArnold Schwaighofer2013-07-051-0/+3
* ARM: Fix incorrect pack patternArnold Schwaighofer2013-07-051-2/+4
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-041-0/+2
* This corrects the implementation of Thumb ADR instruction. There are three i...Mihai Popa2013-07-031-1/+1
* ARM: Fix pseudo-instructions for SRS (Store Return State).Tilmann Scheller2013-06-281-4/+4
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-261-0/+2
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-261-2/+3
* This reverts r155000.Joey Gouly2013-06-201-6/+1
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-191-2/+2
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-1/+11
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-081-0/+2
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-061-27/+35
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-061-2/+4
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-2/+2
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-051-37/+49
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-051-1/+1
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-88/+66
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-041-27/+35
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-041-2/+4
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-041-37/+49
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instruction...Mihai Popa2013-05-131-5/+5
* s tightens up the encoding description for ARM post-indexed ldr instructions....Mihai Popa2013-04-301-0/+1
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-261-1/+5
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-171-4/+11
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-16/+40
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-101-1/+4
* ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer2013-04-051-20/+40
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-04-011-15/+30
* Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer2013-03-261-30/+15
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-03-261-15/+30
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-231-0/+12
* Move MRI liveouts to ARM return instructions.Jakob Stoklund Olesen2013-02-051-1/+1
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-2/+26
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-291-0/+12
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-4/+6
* Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering allChad Rosier2012-11-061-13/+5
* Fix a miscompilation caused by a typo. When turning a adde with negative valueEvan Cheng2012-10-241-6/+6
* Add LLVM support for Swift.Bob Wilson2012-09-291-19/+49
* MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648Evan Cheng2012-09-181-2/+4
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-051-42/+0
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