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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-23/+53
| | | | | Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-5/+10
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-120/+145
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-37/+72
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-10/+25
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-19/+159
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-285/+164
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-9/+14
| | | | | | ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add subtarget feature for CRCBernard Ogden2013-10-291-1/+3
| | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Mark double-precision instructions as suchTim Northover2013-10-241-0/+3
| | | | | | | | | | | | This prevents us from silently accepting invalid instructions on (for example) Cortex-M4 with just single-precision VFP support. No tests for the extra Pat Requires because they're essentially assertions: the affected code should have been lowered to libcalls before ISel. rdar://problem/15302004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-231-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hardware division as a default feature on Cortex-A15. Also add test ↵Silviu Baranga2013-10-181-2/+2
| | | | | | cases to check this, and change diagnostics for the hwdiv-arm feature to something useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192963 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-071-0/+3
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-1/+2
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: support interrupt attributeTim Northover2013-10-011-1/+8
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-011-15/+7
| | | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-125/+207
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Split A/R class into separate subtarget features.Amara Emerson2013-09-231-3/+3
| | | | | | | Patch by Bradley Smith. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-181-0/+39
| | | | | | | Patch by Bradley Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-131-2/+2
| | | | | | | | to be more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-4/+2
| | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-051-0/+10
| | | | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8]Joey Gouly2013-08-281-3/+3
| | | | | | | | | | | | Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-271-4/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: make sure ARM-mode pseudo-inst requires IsARMTim Northover2013-08-231-1/+1
| | | | | | | | | | I'd forgotten that "Requires" blocks override rather than add to the constraints, so my pseudo-instruction was being selected in Thumb mode leading to nonsense instructions. rdar://problem/14817358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-23/+32
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-211-0/+5
| | | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMv8: SWP and SWPB are obsoleted on ARMv8.Joey Gouly2013-08-131-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The ↵Silviu Baranga2013-07-291-1/+3
| | | | | | patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187349 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-221-12/+0
| | | | | | | | After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186810 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-161-7/+50
| | | | | | | Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add a pack pattern for matching arithmetic shift rightArnold Schwaighofer2013-07-051-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185714 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix incorrect pack patternArnold Schwaighofer2013-07-051-2/+4
| | | | | | | | | | | A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them in the bottom half of "x". An arithmetic and logic shift are only equivalent in this context if the shift amount is 16. We would be shifting in ones into the bottom 16bits instead of zeros if "y" is negative. radar://14338767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-041-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-031-1/+1
| | | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix pseudo-instructions for SRS (Store Return State).Tilmann Scheller2013-06-281-4/+4
| | | | | | | | | | | | | | | The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is: srsfa -> srsib srsea -> srsia srsfd -> srsdb srsed -> srsda This fixes <rdar://problem/14214734>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-261-0/+2
| | | | | | | This allows for targeting the ARMv8 AArch32 variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-261-2/+3
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts r155000.Joey Gouly2013-06-201-6/+1
| | | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-2/+2
| | | | | | caching it. The TLI may change between functions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-1/+11
| | | | | | ISB should only accepts full system sync, other options are reserved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-081-0/+2
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-061-27/+35
| | | | | | Reapply 183263. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-061-2/+4
| | | | | | Reapply 183261. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-2/+2
| | | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-051-37/+49
| | | | | | Reapply of 183258. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a simple patch that changes RRX and RRXS to accept all registers as ↵Mihai Popa2013-06-051-1/+1
| | | | | | | | operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
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