| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Make sure FABS on v2f32 and v4f32 is legal on ARM NEON | Anton Korobeynikov | 2012-11-16 | 1 | -6/+9 |
| * | Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers." | Jakob Stoklund Olesen | 2012-10-26 | 1 | -15/+17 |
| * | ARM: v1i64 and v2i64 VBSL intrinsic support. | Jim Grosbach | 2012-10-15 | 1 | -0/+17 |
| * | Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808 | Evan Cheng | 2012-10-10 | 1 | -0/+8 |
| * | Add LLVM support for Swift. | Bob Wilson | 2012-09-29 | 1 | -4/+28 |
| * | ARM: Use a dedicated intrinsic for vector bitwise select. | Jim Grosbach | 2012-09-21 | 1 | -2/+29 |
| * | Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte | Evan Cheng | 2012-09-18 | 1 | -0/+33 |
| * | Use correct part of complex operand to encode VST1 alignment. | Tim Northover | 2012-09-06 | 1 | -2/+2 |
| * | Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to... | James Molloy | 2012-09-06 | 1 | -17/+15 |
| * | Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows una... | Evan Cheng | 2012-08-15 | 1 | -0/+34 |
| * | Use correct loads for vector types during extending-load operations. | Tim Northover | 2012-08-13 | 1 | -36/+36 |
| * | More replacing of target-dependent intrinsics with target-indepdent | Joel Jones | 2012-07-18 | 1 | -2/+2 |
| * | This is one of the first steps at moving to replace target-dependent | Joel Jones | 2012-07-13 | 1 | -1/+1 |
| * | ARM: Allow more flexible patterns in NEON formats. | Jim Grosbach | 2012-07-10 | 1 | -53/+53 |
| * | ARM: Add missing two-operand VBIC aliases. | Jim Grosbach | 2012-05-02 | 1 | -0/+2 |
| * | Fix the order of the operands in the llvm.fma intrinsic patterns for ARM, | Lang Hames | 2012-04-27 | 1 | -4/+4 |
| * | Use VLD1 in NEON extenting-load patterns instead of VLDR. | Tim Northover | 2012-04-26 | 1 | -56/+59 |
| * | Tidy up. 80 columns, whitespace, et. al. | Jim Grosbach | 2012-04-23 | 1 | -18/+18 |
| * | ARM: VSLI two-operand assmebly aliases are tblgen'erated. | Jim Grosbach | 2012-04-23 | 1 | -19/+0 |
| * | ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases. | Jim Grosbach | 2012-04-23 | 1 | -58/+4 |
| * | ARM: vqdmulh two-operand aliases are tblgen'erated now. | Jim Grosbach | 2012-04-23 | 1 | -11/+0 |
| * | ARM: tblgen'erate more NEON two-operand aliases. | Jim Grosbach | 2012-04-20 | 1 | -39/+12 |
| * | ARM: tblgen'erate more NEON two-operand aliases. | Jim Grosbach | 2012-04-20 | 1 | -153/+4 |
| * | ARM: Update NEON assembly two-operand aliases. | Jim Grosbach | 2012-04-20 | 1 | -304/+14 |
| * | Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON. | James Molloy | 2012-04-17 | 1 | -8/+44 |
| * | ARM two-operand forms for vhadd and vhsub instructions. | Jim Grosbach | 2012-04-16 | 1 | -0/+62 |
| * | ARM assembly two-operand forms for VRSHL. | Jim Grosbach | 2012-04-16 | 1 | -1/+36 |
| * | ARM two-operand aliases for VRHADD instructions. | Jim Grosbach | 2012-04-16 | 1 | -0/+32 |
| * | ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction. | Jim Grosbach | 2012-04-11 | 1 | -1/+3 |
| * | ARM 'vzip.32 Dd, Dm' is a pseudo-instruction. | Jim Grosbach | 2012-04-11 | 1 | -1/+3 |
| * | Add more fused mul+add/sub patterns. rdar://10139676 | Evan Cheng | 2012-04-11 | 1 | -2/+8 |
| * | Clean up ARM fused multiply + add/sub support some more: rename some isel | Evan Cheng | 2012-04-11 | 1 | -14/+14 |
| * | Fix a number of problems with ARM fused multiply add/subtract instructions. | Evan Cheng | 2012-04-11 | 1 | -5/+4 |
| * | Handle llvm.fma.* intrinsics. rdar://10914096 | Evan Cheng | 2012-04-10 | 1 | -0/+8 |
| * | ARM assembly aliases for two-operand V[R]SHR instructions. | Jim Grosbach | 2012-04-05 | 1 | -5/+36 |
| * | ARM encoding for VSWP got the second operand incorrect. | Jim Grosbach | 2012-03-30 | 1 | -4/+4 |
| * | Spill DPair registers, not just QPR. | Jakob Stoklund Olesen | 2012-03-28 | 1 | -4/+4 |
| * | Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version. | Richard Barton | 2012-03-28 | 1 | -21/+13 |
| * | ARM more NEON VLD/VST composite physical register refactoring. | Jim Grosbach | 2012-03-06 | 1 | -11/+11 |
| * | ARM refactor more NEON VLD/VST instructions to use composite physregs | Jim Grosbach | 2012-03-06 | 1 | -51/+27 |
| * | ARM Refactor VLD/VST spaced pair instructions. | Jim Grosbach | 2012-03-05 | 1 | -16/+16 |
| * | ARM Remove a bit of dead code. | Jim Grosbach | 2012-03-05 | 1 | -9/+0 |
| * | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach | 2012-03-05 | 1 | -75/+29 |
| * | updated patch for the ARM fused multiply add/sub | Sebastian Pop | 2012-03-05 | 1 | -12/+12 |
| * | ARM vbit/vbif/vbsl assembly optional size suffix. | Jim Grosbach | 2012-02-28 | 1 | -0/+14 |
| * | Improve generated code for extending loads and some trunc stores on ARM. | James Molloy | 2012-02-20 | 1 | -0/+111 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Third time's the charm...? | Lang Hames | 2012-02-14 | 1 | -2/+2 |
| * | Unswap swap operands, partially reducing confusion. | Lang Hames | 2012-02-14 | 1 | -2/+2 |
| * | Make operands for VSWP read-modify-write. | Lang Hames | 2012-02-13 | 1 | -4/+6 |
