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* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-26/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-131-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
* Now Igor, throw the switch...give my creation life!Bill Wendling2011-10-171-1/+2
| | | | | | | | | | | | | | | | | | Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark tADDrSPi as having side effects again.Jakob Stoklund Olesen2011-10-151-3/+3
| | | | | | | | | | | It really doesn't, but when r141929 removed the hasSideEffects flag from this instruction, it caused miscompilations. I am guessing that it got moved across a stack pointer update. Also clear isRematerializable after checking that this instruction is in fact never rematerialized in the nightly test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142030 91177308-0d34-0410-b5e6-96231b3b80d8
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-141-1/+1
| | | | | | | | | | TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.Jim Grosbach2011-09-201-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140108 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb CPS definition is not disassembler only.Jim Grosbach2011-09-201-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for SUB(immediate).Jim Grosbach2011-09-161-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a more efficient lowering for Unordered/Monotonic atomic load/store on ↵Eli Friedman2011-09-151-0/+25
| | | | | | Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-4/+5
| | | | | | have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding for SUB (SP minu immediate).Jim Grosbach2011-08-241-4/+6
| | | | | | | Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that form is Thumb2 only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach2011-08-241-17/+30
| | | | | | | | Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing explicit writeback operand to tSTMIA_UPD.Jim Grosbach2011-08-241-3/+4
| | | | | | rdar://10014745 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb add SP assembly syntax fix.Jim Grosbach2011-08-241-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138448 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-15/+15
| | | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding for SVC.Jim Grosbach2011-08-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding for tSTRspi.Jim Grosbach2011-08-231-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up Thumb load/store multiple definitions.Jim Grosbach2011-08-231-36/+34
| | | | | | | | | There is no non-writeback store multiple instruction in Thumb1, so don't define one. As a result load multiple is the only instantiation of the multiclass, so refactor that away entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r138278 now that r138289 has fixed the root issue.Jim Grosbach2011-08-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138299 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarilly mark tMUL as not commutable.Jim Grosbach2011-08-221-1/+1
| | | | | | | | It's not playing nicely in the coalescer with the tied operand. Disable commutability for now while we figure out the deeper fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138278 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up predicates on ARM target instruction aliases.Jim Grosbach2011-08-221-9/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding support for NOP.Jim Grosbach2011-08-191-1/+7
| | | | | | | The irony is not lost that this is not a completely trivial patchset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix NEG aliasJim Grosbach2011-08-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138125 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tests.Jim Grosbach2011-08-191-0/+4
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* Thumb assembly parsing and encoding for MUL.Jim Grosbach2011-08-191-4/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for MOV.Jim Grosbach2011-08-191-0/+5
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* Thumb assembly parsing and encoding for LSL(immediate).Jim Grosbach2011-08-191-1/+1
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* Thumb assembly parsing and encoding for LDRSB and LDRSH.Jim Grosbach2011-08-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDRH.Jim Grosbach2011-08-191-0/+2
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* Thumb assembly parsing and encoding for LDRB.Jim Grosbach2011-08-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDR(immediate) form T2.Jim Grosbach2011-08-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDR(immediate) form T1.Jim Grosbach2011-08-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explanatory comment.Jim Grosbach2011-08-191-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138042 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-181-3/+8
| | | | | | | | | Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for CMP.Jim Grosbach2011-08-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.Jim Grosbach2011-08-181-25/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137956 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 columns.Jim Grosbach2011-08-181-1/+1
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* Clean up patterns for Thumb1 system instructions.Jim Grosbach2011-08-171-24/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137897 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-4/+10
| | | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for ADR.Jim Grosbach2011-08-171-1/+1
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* Thumb ADD(immediate) parsing support.Jim Grosbach2011-08-161-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-151-6/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-11/+17
| | | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 BL instructions encoding 22 bits of displacement, not 21.Owen Anderson2011-08-081-1/+4
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* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-4/+12
| | | | | | range 1-32, with 32 encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-18/+4
| | | | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix broken encoding of tCBNZ.Owen Anderson2011-08-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136837 91177308-0d34-0410-b5e6-96231b3b80d8
* Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.Jim Grosbach2011-08-011-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136656 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding for SVC instruction.Jim Grosbach2011-07-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly support for SETEND instruction.Jim Grosbach2011-07-221-14/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135778 91177308-0d34-0410-b5e6-96231b3b80d8
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