| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [ARMv8] Add CRC instructions. | Joey Gouly | 2013-09-18 | 1 | -0/+40 |
| * | [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}. | Joey Gouly | 2013-09-17 | 1 | -1/+2 |
| * | [ARMv8] Implement the new DMB/DSB operands. | Joey Gouly | 2013-09-05 | 1 | -2/+3 |
| * | Add AArch32 DCPS{1,2,3} and HLT instructions. | Richard Barton | 2013-09-05 | 1 | -0/+14 |
| * | Reverting 190043 for now. | Tilmann Scheller | 2013-09-05 | 1 | -1/+1 |
| * | ARM: Add GPR register class excluding LR for use with the ADR instruction. | Tilmann Scheller | 2013-09-05 | 1 | -1/+1 |
| * | [ARMv8] | Joey Gouly | 2013-08-28 | 1 | -11/+17 |
| * | [ARMv8] Add a missing IsThumb to t2LDAEXD. | Joey Gouly | 2013-08-28 | 1 | -1/+1 |
| * | [ARMv8] Add MC support for the new load/store acquire/release instructions. | Joey Gouly | 2013-08-27 | 1 | -12/+123 |
| * | ARM: use TableGen patterns to select CMOV operations. | Tim Northover | 2013-08-22 | 1 | -72/+46 |
| * | Make "mov" work for all Thumb2 MOV encodings | Mihai Popa | 2013-08-21 | 1 | -0/+3 |
| * | Thumb2 add immediate alias for SP | Mihai Popa | 2013-08-19 | 1 | -1/+2 |
| * | Fix Thumb2 aliasing complementary instructions taking modified immediates | Mihai Popa | 2013-08-16 | 1 | -4/+4 |
| * | This fixes three issues related to Thumb literal loads: | Mihai Popa | 2013-08-15 | 1 | -3/+3 |
| * | This fixes the Thumb2 CPS assembly syntax. | Mihai Popa | 2013-08-09 | 1 | -1/+5 |
| * | Fix assembling of Thumb2 branch instructions. | Mihai Popa | 2013-08-09 | 1 | -4/+6 |
| * | The name "tCDP" isn't used anywhere else in the source code, so renaming it f... | Mihai Popa | 2013-08-08 | 1 | -1/+1 |
| * | This corrects creation of operands for t2PLDW. It also removes the definition... | Mihai Popa | 2013-08-06 | 1 | -25/+22 |
| * | Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ins... | Mihai Popa | 2013-08-06 | 1 | -4/+4 |
| * | Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. | Kevin Enderby | 2013-07-31 | 1 | -0/+10 |
| * | This adds range checking for "ldr Rn, [pc, #imm]" Thumb | Mihai Popa | 2013-07-22 | 1 | -1/+1 |
| * | ARM: remove now unneeded custom Asm converters | Tim Northover | 2013-07-22 | 1 | -29/+13 |
| * | ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form. | Tilmann Scheller | 2013-07-19 | 1 | -1/+6 |
| * | ARM: Make sure the instruction alias for PLI uses the right subtarget features. | Tilmann Scheller | 2013-07-18 | 1 | -1/+3 |
| * | ARM: Add support for the Thumb2 PLI alternate literal form. | Tilmann Scheller | 2013-07-16 | 1 | -0/+3 |
| * | ARM: implement ldrex, strex and clrex intrinsics | Tim Northover | 2013-07-16 | 1 | -8/+27 |
| * | ARM: Fix incorrect pack pattern for thumb2 | Jim Grosbach | 2013-07-09 | 1 | -1/+6 |
| * | This corrects the implementation of Thumb ADR instruction. There are three i... | Mihai Popa | 2013-07-03 | 1 | -1/+1 |
| * | ARM: fix more cases where predication may or may not be allowed | Tim Northover | 2013-06-26 | 1 | -13/+12 |
| * | ARM: allow predicated barriers in Thumb mode | Tim Northover | 2013-06-26 | 1 | -12/+10 |
| * | ARM: enable decoding of pc-relative PLD/PLI | Amaury de la Vieuville | 2013-06-24 | 1 | -10/+33 |
| * | ARM: fix literal load with positive offset encoding | Amaury de la Vieuville | 2013-06-18 | 1 | -3/+3 |
| * | ARM: add operands pre-writeback variants when needed | Amaury de la Vieuville | 2013-06-18 | 1 | -18/+31 |
| * | ARM: fix thumb literal loads decoding | Amaury de la Vieuville | 2013-06-18 | 1 | -4/+12 |
| * | ARM: fix thumb coprocessor instruction with pre-writeback disassembly | Amaury de la Vieuville | 2013-06-14 | 1 | -1/+1 |
| * | ARM: ISB cannot be passed the same options as DMB | Amaury de la Vieuville | 2013-06-10 | 1 | -1/+1 |
| * | ARM sched model: Add branch thumb2 instructions | Arnold Schwaighofer | 2013-06-06 | 1 | -11/+15 |
| * | ARM sched model: Add preload thumb2 instructions | Arnold Schwaighofer | 2013-06-06 | 1 | -3/+6 |
| * | ARM sched model: Add more ALU and CMP thumb2 instructions | Arnold Schwaighofer | 2013-06-06 | 1 | -52/+86 |
| * | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer | 2013-06-04 | 1 | -107/+66 |
| * | ARM sched model: Add branch thumb2 instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -11/+15 |
| * | ARM sched model: Add preload thumb2 instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -3/+6 |
| * | ARM sched model: Add more ALU and CMP thumb2 instructions | Arnold Schwaighofer | 2013-06-04 | 1 | -52/+86 |
| * | Tidy some register classes for ARM and Thumb | JF Bastien | 2013-05-29 | 1 | -1/+1 |
| * | ARM: Fix encoding of hint instruction for Thumb. | Quentin Colombet | 2013-04-26 | 1 | -11/+6 |
| * | ARM: Correct printing of pre-indexed operands. | Quentin Colombet | 2013-04-12 | 1 | -1/+1 |
| * | ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. | Tim Northover | 2013-04-10 | 1 | -1/+2 |
| * | ARM: Convenience aliases for 'srs*' instructions. | Jim Grosbach | 2013-02-23 | 1 | -0/+7 |
| * | Some enhancements for memcpy / memset inline expansion. | Evan Cheng | 2012-12-10 | 1 | -2/+4 |
| * | The code pattern "imm0_255_neg" is used for checking if an immediate value is... | Nadav Rotem | 2012-11-14 | 1 | -6/+7 |
