aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Commit message (Expand)AuthorAgeFilesLines
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+1
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexedEvan Cheng2012-02-071-24/+58
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-24/+0
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-3/+4
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-7/+5
* ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.NAKAMURA Takumi2011-11-251-0/+1
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+22
* Hide cpu name checking in ARMSubtarget.Evan Cheng2011-11-091-1/+1
* Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with l...Evan Cheng2011-11-081-3/+9
* Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodin...Owen Anderson2011-08-291-1/+2
* Update the load-store optimizer for changes to the operands on LDR_PRE_IMM an...Owen Anderson2011-08-291-4/+10
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w...Owen Anderson2011-08-261-1/+1
* ARM STR_POST_IMM offset encoding fix in load/store optimizer.Jim Grosbach2011-08-121-13/+10
* ARM refactor indexed store instructions.Jim Grosbach2011-08-051-2/+8
* Split am2offset into register addend and immediate addend forms, necessary fo...Owen Anderson2011-07-261-3/+3
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A...Evan Cheng2011-07-201-1/+2
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-10/+2
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-11/+11
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
* Clean up comment a bit.Eric Christopher2011-05-251-2/+2
* Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turne...Cameron Zwarich2011-05-181-4/+7
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-291-1/+1
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-4/+4
* Clean up some code for clarity.Bob Wilson2011-04-051-5/+24
* Check early if this is an unsupported opcode, so that we can avoid needlessly...Owen Anderson2011-03-291-0/+4
* Add safety check that didn't show up in testing.Owen Anderson2011-03-291-0/+1
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually...Owen Anderson2011-03-291-17/+5
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-151-9/+3
* Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ...Jakob Stoklund Olesen2011-02-151-21/+15
* Move code for OffsetCompare struct closer to where it is used.Bob Wilson2011-02-071-11/+11
* Fix a few more places that should use MBB::getLastNonDebugInstr().Jakob Stoklund Olesen2011-01-131-1/+1
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
* PR8921: LDM/POP do not support interworking prior to v5t.Bob Wilson2011-01-061-1/+2
* Missed the _RET versions of LDMIA.Bill Wendling2010-11-181-0/+2
* Add missing opcodes now that this function's used in more than one place.Bill Wendling2010-11-171-0/+20
* Revert r119109 for now. It's breaking 176.gcc.Evan Cheng2010-11-171-17/+0
* The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling2010-11-171-2/+8
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-67/+236
* Make sure ARM multi load / store pass copies memoperands when forming ldrd / ...Evan Cheng2010-11-151-0/+17
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-69/+34
* One more spot where the new arm mode LDR instruction representationJim Grosbach2010-10-271-3/+3
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-18/+27
* Grammar.Jim Grosbach2010-10-261-1/+1
* Transfer implicit ops when forming load multiple and return instructions.Evan Cheng2010-10-221-0/+1
* Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.Bob Wilson2010-09-291-1/+1
* move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helperJim Grosbach2010-09-151-2/+2
* Calculate the number of VLDM/VSTM registers by subtracting the number ofBob Wilson2010-09-101-2/+2
* Fix merging base-updates for VLDM/VSTM: Before I switched these instructionsBob Wilson2010-09-101-1/+2
* Remember to clear the shadow kill flag at the same time as clearing the realJakob Stoklund Olesen2010-08-301-0/+1