| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h | Craig Topper | 2012-03-26 | 1 | -1/+1 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed | Evan Cheng | 2012-02-07 | 1 | -24/+58 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 | 1 | -24/+0 |
| * | ARM Ld/St Optimizer fix. | Andrew Trick | 2012-01-11 | 1 | -3/+4 |
| * | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 2011-12-07 | 1 | -7/+5 |
| * | ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build. | NAKAMURA Takumi | 2011-11-25 | 1 | -0/+1 |
| * | Preserve MachineMemOperands in ARMLoadStoreOptimizer. | Andrew Trick | 2011-11-11 | 1 | -0/+22 |
| * | Hide cpu name checking in ARMSubtarget. | Evan Cheng | 2011-11-09 | 1 | -1/+1 |
| * | Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with l... | Evan Cheng | 2011-11-08 | 1 | -3/+9 |
| * | Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodin... | Owen Anderson | 2011-08-29 | 1 | -1/+2 |
| * | Update the load-store optimizer for changes to the operands on LDR_PRE_IMM an... | Owen Anderson | 2011-08-29 | 1 | -4/+10 |
| * | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson | 2011-08-26 | 1 | -1/+1 |
| * | ARM STR_POST_IMM offset encoding fix in load/store optimizer. | Jim Grosbach | 2011-08-12 | 1 | -13/+10 |
| * | ARM refactor indexed store instructions. | Jim Grosbach | 2011-08-05 | 1 | -2/+8 |
| * | Split am2offset into register addend and immediate addend forms, necessary fo... | Owen Anderson | 2011-07-26 | 1 | -3/+3 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+2 |
| * | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach | 2011-06-29 | 1 | -10/+2 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -11/+11 |
| * | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 | 1 | -1/+1 |
| * | Clean up comment a bit. | Eric Christopher | 2011-05-25 | 1 | -2/+2 |
| * | Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turne... | Cameron Zwarich | 2011-05-18 | 1 | -4/+7 |
| * | use the MachineInstrBuilder operator-> to simplify some code. | Chris Lattner | 2011-04-29 | 1 | -1/+1 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -4/+4 |
| * | Clean up some code for clarity. | Bob Wilson | 2011-04-05 | 1 | -5/+24 |
| * | Check early if this is an unsupported opcode, so that we can avoid needlessly... | Owen Anderson | 2011-03-29 | 1 | -0/+4 |
| * | Add safety check that didn't show up in testing. | Owen Anderson | 2011-03-29 | 1 | -0/+1 |
| * | Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually... | Owen Anderson | 2011-03-29 | 1 | -17/+5 |
| * | Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587 | Evan Cheng | 2011-03-15 | 1 | -9/+3 |
| * | Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ... | Jakob Stoklund Olesen | 2011-02-15 | 1 | -21/+15 |
| * | Move code for OffsetCompare struct closer to where it is used. | Bob Wilson | 2011-02-07 | 1 | -11/+11 |
| * | Fix a few more places that should use MBB::getLastNonDebugInstr(). | Jakob Stoklund Olesen | 2011-01-13 | 1 | -1/+1 |
| * | Do not model all INLINEASM instructions as having unmodelled side effects. | Evan Cheng | 2011-01-07 | 1 | -1/+1 |
| * | PR8921: LDM/POP do not support interworking prior to v5t. | Bob Wilson | 2011-01-06 | 1 | -1/+2 |
| * | Missed the _RET versions of LDMIA. | Bill Wendling | 2010-11-18 | 1 | -0/+2 |
| * | Add missing opcodes now that this function's used in more than one place. | Bill Wendling | 2010-11-17 | 1 | -0/+20 |
| * | Revert r119109 for now. It's breaking 176.gcc. | Evan Cheng | 2010-11-17 | 1 | -17/+0 |
| * | The machine instruction no longer encodes the submode as a separate operand. We | Bill Wendling | 2010-11-17 | 1 | -2/+8 |
| * | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 | 1 | -67/+236 |
| * | Make sure ARM multi load / store pass copies memoperands when forming ldrd / ... | Evan Cheng | 2010-11-15 | 1 | -0/+17 |
| * | Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like | Jim Grosbach | 2010-10-27 | 1 | -69/+34 |
| * | One more spot where the new arm mode LDR instruction representation | Jim Grosbach | 2010-10-27 | 1 | -3/+3 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -18/+27 |
| * | Grammar. | Jim Grosbach | 2010-10-26 | 1 | -1/+1 |
| * | Transfer implicit ops when forming load multiple and return instructions. | Evan Cheng | 2010-10-22 | 1 | -0/+1 |
| * | Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits. | Bob Wilson | 2010-09-29 | 1 | -1/+1 |
| * | move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper | Jim Grosbach | 2010-09-15 | 1 | -2/+2 |
| * | Calculate the number of VLDM/VSTM registers by subtracting the number of | Bob Wilson | 2010-09-10 | 1 | -2/+2 |
| * | Fix merging base-updates for VLDM/VSTM: Before I switched these instructions | Bob Wilson | 2010-09-10 | 1 | -1/+2 |
| * | Remember to clear the shadow kill flag at the same time as clearing the real | Jakob Stoklund Olesen | 2010-08-30 | 1 | -0/+1 |
