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path: root/lib/Target/ARM/ARMScheduleV6.td
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* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-2/+2
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+6
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-3/+3
* Sorry, several patches in one.Evan Cheng2011-01-201-0/+6
* Conditional moves are slightly more expensive than moves.Evan Cheng2010-11-131-0/+2
* putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick2010-10-211-0/+12
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-211-12/+0
* Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng2010-10-211-0/+12
* Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld...Evan Cheng2010-10-071-2/+8
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-6/+19
* ARM instruction itinerary fixes:Evan Cheng2010-09-301-13/+30
* Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.Evan Cheng2010-09-291-0/+12
* Assign bitwise binary instructions different itinerary classes from ALU instr...Evan Cheng2010-09-291-0/+7
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-281-1/+1
* Remove a unused instruction itinerary class.Evan Cheng2010-09-251-1/+0
* Fix zero and sign extension instructions scheduling itineraries.Evan Cheng2010-09-251-0/+4
* More pseudo instruction scheduling itinerary fixes.Evan Cheng2010-09-241-0/+7
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-091-0/+5
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-1/+1
* Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov2010-04-181-69/+73
* Add ARMv6 itineraries.David Goodwin2009-11-181-1/+187
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-231-86/+1
* Add Cortex-A8 VFP model.David Goodwin2009-09-211-6/+35
* Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin2009-08-191-6/+46
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-2/+4
* Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin2009-08-131-1/+3
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ...David Goodwin2009-08-111-9/+7
* Checkpoint scheduling itinerary changes.David Goodwin2009-08-101-7/+13
* Fix comment.Evan Cheng2009-07-211-1/+1
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ...Evan Cheng2009-06-191-0/+22
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