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path: root/lib/Target/ARM/Thumb1RegisterInfo.h
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* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-1/+1
* Update to LLVM 3.5a.Stephen Hines2014-04-241-16/+14
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-211-5/+0
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-311-1/+2
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+2
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-2/+1
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on regist...Jakob Stoklund Olesen2011-04-261-0/+3
* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-311-0/+2
* Implement frame unwinding information emission for Thumb1. Not finished yet b...Anton Korobeynikov2011-03-051-1/+2
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-2/+0
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ou...Anton Korobeynikov2010-11-151-3/+0
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-3/+2
* Add Thumb1 support for virtual frame indices.Jim Grosbach2010-08-191-7/+8
* Constify some arguments.Eric Christopher2010-07-201-1/+1
* Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola2010-07-111-3/+0
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-1/+2
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-1/+1
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-2/+3
* Cleanup now that frame index scavenging via post-pass is working for ARM and ...Jim Grosbach2009-10-281-3/+0
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+3
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-201-3/+0
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-4/+1
* Re-enable register scavenging in Thumb1 by default.Jim Grosbach2009-10-081-0/+1
* reverting thumb1 scavenging default due to test failure while I figure out wh...Jim Grosbach2009-10-071-1/+0
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-071-0/+1
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-2/+3
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-0/+8
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ...Owen Anderson2009-08-111-1/+1
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ...Owen Anderson2009-08-101-1/+1
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-2/+2
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-0/+2
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index eliminatio...David Goodwin2009-07-241-0/+4
* Let callers decide the sub-register index on the def operand of rematerialize...Evan Cheng2009-07-161-1/+1
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-1/+1
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-9/+8
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1Ins...David Goodwin2009-07-021-0/+60
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