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path: root/lib/Target/ARM/Thumb2InstrInfo.cpp
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* Update to LLVM 3.5a.Stephen Hines2014-04-241-1/+0
* ARM: remove unnecessary state-tracking during frame lowering.Tim Northover2013-11-041-0/+7
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-181-1/+2
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+7
* Reverting 190043 for now.Tilmann Scheller2013-09-051-14/+2
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-051-2/+14
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-3/+3
* ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover2013-04-211-20/+64
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-191-1/+1
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-2/+2
* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-131-42/+0
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper2012-04-201-6/+6
* Prune some includesCraig Topper2012-03-271-1/+0
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-5/+5
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-1/+0
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Handle regmask operands in ARMInstrInfo.Jakob Stoklund Olesen2012-02-171-1/+1
* Make use of MachinePointerInfo::getFixedStack. This removes all mentionJay Foad2011-11-151-5/+2
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-3/+2
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A...Evan Cheng2011-07-201-1/+1
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-15/+4
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-301-7/+7
* Kill dead code.Jim Grosbach2011-06-301-1/+0
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-6/+4
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+0
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-1/+1
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-8/+11
* Guard against de-referencing MBB.end().Evan Cheng2011-02-221-1/+4
* Skipping over debugvalue instructions to determine whether the split spot is ...Evan Cheng2011-02-211-0/+3
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-051-6/+0
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-27/+0
* Thread the determination of branch prediction hit rates back through the if-c...Owen Anderson2010-10-011-4/+7
* Provide an option to restore old-style if-conversion heuristics for Thumb2.Owen Anderson2010-10-011-0/+29
* Part one of switching to using a more sane heuristic for determining if-conve...Owen Anderson2010-09-281-25/+0
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-211-4/+6
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-1/+1
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-301-4/+4
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-111-27/+19
* The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to addBob Wilson2010-06-291-2/+2
* Change if-cvt options to something that actually as useable.Evan Cheng2010-06-291-4/+6
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-251-0/+23
* Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng2010-06-221-0/+16
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-1/+58
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-5/+7
* Allow target to place 2-address pass inserted copies in better spots. Thumb2 ...Evan Cheng2010-06-091-0/+43
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-1/+2
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-5/+3