| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update aosp/master LLVM for rebase to r230699. | Stephen Hines | 2015-03-23 | 1 | -9/+4 |
| * | Update aosp/master LLVM for rebase to r222494. | Stephen Hines | 2014-12-02 | 1 | -3/+3 |
| * | Update LLVM for rebase to r212749. | Stephen Hines | 2014-07-21 | 1 | -1/+2 |
| * | Update LLVM for 3.5 rebase (r209712). | Stephen Hines | 2014-05-29 | 1 | -7/+7 |
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -16/+13 |
| * | ARM: Remove unused variable. | Benjamin Kramer | 2013-04-08 | 1 | -2/+0 |
| * | Avoid high-latency false CPSR dependencies even for tMOVSi. | Jakob Stoklund Olesen | 2013-04-04 | 1 | -46/+103 |
| * | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 2013-01-02 | 1 | -1/+1 |
| * | Resort the #include lines in include/... and lib/... with the | Chandler Carruth | 2013-01-02 | 1 | -1/+1 |
| * | Remove the Function::getFnAttributes method in favor of using the AttributeSet | Bill Wendling | 2012-12-30 | 1 | -3/+5 |
| * | On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, | Evan Cheng | 2012-12-20 | 1 | -77/+92 |
| * | Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl... | Bill Wendling | 2012-12-19 | 1 | -1/+1 |
| * | Disable ARM partial flag dependency optimization at -Oz | Quentin Colombet | 2012-12-18 | 1 | -2/+10 |
| * | Repair bundles that were broken by removing and reinserting the first | Jakob Stoklund Olesen | 2012-12-18 | 1 | -1/+8 |
| * | Extract a method, no functional change intended. | Jakob Stoklund Olesen | 2012-12-18 | 1 | -31/+35 |
| * | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 | 1 | -5/+5 |
| * | Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ... | Jakob Stoklund Olesen | 2012-08-28 | 1 | -21/+5 |
| * | Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM. | Jakob Stoklund Olesen | 2012-08-27 | 1 | -5/+21 |
| * | Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits... | Sebastian Pop | 2012-05-04 | 1 | -0/+1 |
| * | Tidy up. 80 columns. | Jim Grosbach | 2012-04-06 | 1 | -1/+1 |
| * | Use uint16_t to store registers and opcode in static tables in the target spe... | Craig Topper | 2012-03-11 | 1 | -3/+3 |
| * | Use uint16_t to store instruction implicit uses and defs. Reduces static data. | Craig Topper | 2012-03-08 | 1 | -1/+1 |
| * | Make sure the regs are low regs for tMUL size reduction. | Jim Grosbach | 2012-02-24 | 1 | -1/+6 |
| * | Thumb2 size reduction fix for tied operands of tMUL. | Jim Grosbach | 2012-02-24 | 1 | -1/+13 |
| * | Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. | Evan Cheng | 2011-12-17 | 1 | -4/+7 |
| * | - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function | Evan Cheng | 2011-12-14 | 1 | -13/+28 |
| * | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 2011-12-07 | 1 | -3/+2 |
| * | Avoid partial CPSR dependency from loop backedges. rdar://10357570 | Evan Cheng | 2011-10-27 | 1 | -24/+43 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 | 1 | -0/+1 |
| * | ARM extend instructions simplification. | Jim Grosbach | 2011-07-27 | 1 | -5/+13 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | Fix off-by-one error. | Jim Grosbach | 2011-07-01 | 1 | -1/+1 |
| * | Pseudo-ize t2MOVCC[ri]. | Jim Grosbach | 2011-07-01 | 1 | -2/+0 |
| * | Refact ARM Thumb1 tMOVr instruction family. | Jim Grosbach | 2011-06-30 | 1 | -1/+1 |
| * | Size reducing SP adjusting t2ADDri needs to check predication. | Jim Grosbach | 2011-06-30 | 1 | -1/+4 |
| * | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach | 2011-06-29 | 1 | -26/+47 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -34/+34 |
| * | use the MachineInstrBuilder operator-> to simplify some code. | Chris Lattner | 2011-04-29 | 1 | -1/+1 |
| * | Avoid some 's' 16-bit instruction which partially update CPSR | Bob Wilson | 2011-04-19 | 1 | -85/+165 |
| * | Handle MI flags inside Thumb2SizeReduction pass. | Anton Korobeynikov | 2011-03-05 | 1 | -0/+9 |
| * | Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ... | Owen Anderson | 2011-02-08 | 1 | -43/+9 |
| * | Temporary workaround for a bad bug introduced by r121082 which replaced | Evan Cheng | 2011-02-08 | 1 | -8/+5 |
| * | The tLDR et al instructions were emitting either a reg/reg or reg/imm | Bill Wendling | 2010-12-14 | 1 | -29/+36 |
| * | Refactor the ARM CMPz* patterns to just use the normal CMP instructions when | Jim Grosbach | 2010-12-07 | 1 | -5/+3 |
| * | Second attempt at converting Thumb2's LDRpci, including updating the gazillio... | Owen Anderson | 2010-12-07 | 1 | -6/+42 |
| * | The Thumb tADDrSPi instruction is not valid when the destination is SP. | Bob Wilson | 2010-12-04 | 1 | -1/+8 |
| * | Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. | Jim Grosbach | 2010-12-03 | 1 | -1/+13 |
| * | Reduce t2 ldr/str instructions to the correct t1 versions when there's an | Jim Grosbach | 2010-12-03 | 1 | -6/+6 |
| * | Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. | Jim Grosbach | 2010-12-03 | 1 | -1/+2 |
| * | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 | 1 | -19/+24 |
