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* dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.llChris Lattner2007-04-171-1/+1
* add a noteChris Lattner2007-04-171-0/+43
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-162-3/+3
* arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.Chris Lattner2007-04-131-1/+5
* Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-ne...Chris Lattner2007-04-111-3/+3
* restore support for negative stridesChris Lattner2007-04-101-3/+5
* remove dead target hooksChris Lattner2007-04-092-98/+49
* remove some dead target hooks, subsumed by isLegalAddressingModeChris Lattner2007-04-092-30/+0
* Implement inline asm modifier P.Evan Cheng2007-04-041-0/+1
* Typo.Evan Cheng2007-04-041-1/+1
* Remove unused constant pool entries.Evan Cheng2007-04-031-32/+60
* Fixed a bug that causes codegen of noop like add r0, r0, #0.Evan Cheng2007-04-031-1/+1
* Inverted logic.Evan Cheng2007-04-031-1/+1
* Arm supports negative strides as well, add them. This lets us compile:Chris Lattner2007-04-031-3/+6
* fix off by 1 error in displacement computationDale Johannesen2007-04-021-0/+5
* fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scalesChris Lattner2007-04-021-4/+20
* add support for the 'w' inline asm register class.Chris Lattner2007-04-021-6/+28
* - Divides the comparisons in two types: comparisons that only use N and ZLauro Ramos Venancio2007-04-024-7/+45
* Add i16 address mode.Evan Cheng2007-04-011-2/+7
* implement the new addressing mode description hook.Chris Lattner2007-03-302-0/+42
* New entry.Evan Cheng2007-03-291-0/+5
* Can't re-materialize mov r, imm in thumb since mov would clobber the conditio...Evan Cheng2007-03-291-1/+1
* Add support for hidden visibility to darwin/arm.Evan Cheng2007-03-291-0/+4
* Remove isLegalAddressImmediate.Evan Cheng2007-03-282-20/+0
* bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" o...Lauro Ramos Venancio2007-03-273-11/+11
* findRegisterUseOperand() changed.Evan Cheng2007-03-262-3/+3
* switch TargetLowering::getConstraintType to take the entire constraint,Chris Lattner2007-03-252-6/+8
* repair x86 performance, dejagnu problems from previous changeDale Johannesen2007-03-212-3/+4
* Updated.Evan Cheng2007-03-201-1/+6
* do not share old induction variables when this would result in invalidDale Johannesen2007-03-202-0/+29
* bugfix: When the source register of CALL_NOLINK was LR, the following code wa...Lauro Ramos Venancio2007-03-203-19/+28
* Make two piece constant generation as a single instruction. It's re-materiali...Evan Cheng2007-03-202-30/+55
* New entry.Evan Cheng2007-03-201-0/+13
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-202-16/+38
* fix indentationChris Lattner2007-03-201-1/+1
* fix obvious comment bugDale Johannesen2007-03-201-1/+1
* Fix naming inconsistencies.Evan Cheng2007-03-196-30/+30
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-193-2/+12
* Constant generation instructions are re-materializable.Evan Cheng2007-03-192-5/+11
* Only ARMv6 has BSWAP.Lauro Ramos Venancio2007-03-161-0/+4
* Added isLegalAddressExpression(). Only allows X +/- C for now.Evan Cheng2007-03-162-0/+21
* AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]Evan Cheng2007-03-131-0/+23
* Zero is always a legal AM immediate.Evan Cheng2007-03-131-0/+3
* Implement getTargetLowering() or else LSR won't be using ARM specific hooks.Evan Cheng2007-03-132-1/+8
* Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.Evan Cheng2007-03-122-8/+88
* Minor stuff.Evan Cheng2007-03-091-0/+4
* Add comments about LSR / ARM.Evan Cheng2007-03-091-0/+4
* Unfinished work and ideas related to register scavenger.Evan Cheng2007-03-091-0/+14
* apply comments from review of last patchDale Johannesen2007-03-091-2/+2
* Add some observations from CoreGraphics benchmark. Remove registerDale Johannesen2007-03-091-47/+47