| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix an apparent typo that made GCC complain | Matt Beaumont-Gay | 2011-04-08 | 1 | -1/+1 |
| * | Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is... | Evan Cheng | 2011-04-08 | 1 | -23/+1 |
| * | Check opcoe (dmb, dsb) instead of bitfields matching. | Johnny Chen | 2011-04-08 | 1 | -12/+1 |
| * | Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. | Johnny Chen | 2011-04-08 | 1 | -9/+10 |
| * | Sanity check the option operand for DMB/DSB. | Johnny Chen | 2011-04-08 | 2 | -8/+29 |
| * | Mark hasExtraDefRegAllocReq=1 on LDRD. | Jim Grosbach | 2011-04-08 | 1 | -1/+5 |
| * | Add sanity checking for bad register specifier(s) for the DPFrm instructions. | Johnny Chen | 2011-04-08 | 1 | -0/+30 |
| * | Add option to emit @llvm.trap as a function call instead of a trap instructio... | Evan Cheng | 2011-04-07 | 1 | -1/+23 |
| * | Fixed encoding for VEXTqf | Mon P Wang | 2011-04-07 | 1 | -2/+2 |
| * | Add sanity checking for invalid register encodings for signed/unsigned extend... | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Add sanity checking for invalid register encodings for saturating instructions. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Add some more comments about checkings of invalid register numbers. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector... | Tanya Lattner | 2011-04-07 | 1 | -0/+6 |
| * | Sanity check MSRi for invalid mask values and reject it as invalid. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | The ARM disassembler was not recognizing USADA8 instruction. Need to add che... | Johnny Chen | 2011-04-07 | 1 | -3/+5 |
| * | Change -arm-divmod-libcall to a target neutral option. | Evan Cheng | 2011-04-07 | 1 | -6/+1 |
| * | Should also check SMLAD for invalid register values. | Johnny Chen | 2011-04-07 | 1 | -6/+12 |
| * | Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ... | Owen Anderson | 2011-04-06 | 1 | -1/+8 |
| * | Cleanups from Jim: remove redundant constraints and a dead FIXME. | Owen Anderson | 2011-04-06 | 1 | -11/+5 |
| * | Tidy up. | Jim Grosbach | 2011-04-06 | 1 | -2/+1 |
| * | A8.6.393 | Johnny Chen | 2011-04-06 | 1 | -26/+47 |
| * | A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" | Johnny Chen | 2011-04-06 | 1 | -1/+14 |
| * | Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. | Johnny Chen | 2011-04-06 | 2 | -1/+3 |
| * | Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. | Johnny Chen | 2011-04-06 | 1 | -7/+3 |
| * | Reapply r128946 (pseudoization of various instructions), and fix the extra im... | Owen Anderson | 2011-04-05 | 2 | -65/+42 |
| * | Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal... | Johnny Chen | 2011-04-05 | 1 | -1/+7 |
| * | Clean up some code for clarity. | Bob Wilson | 2011-04-05 | 1 | -5/+24 |
| * | Revert r128946 while I figure out why it broke the buildbots. | Owen Anderson | 2011-04-05 | 2 | -38/+64 |
| * | A7.3 register encoding | Johnny Chen | 2011-04-05 | 1 | -0/+10 |
| * | Give RSBS and RSCS the pseudo treatment. | Owen Anderson | 2011-04-05 | 2 | -64/+38 |
| * | ARM disassembler was erroneously accepting an invalid RSC instruction. | Johnny Chen | 2011-04-05 | 1 | -0/+6 |
| * | ARM disassembler was erroneously accepting an invalid LSL instruction. | Johnny Chen | 2011-04-05 | 1 | -0/+4 |
| * | Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doi... | Owen Anderson | 2011-04-05 | 3 | -80/+76 |
| * | The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. | Johnny Chen | 2011-04-05 | 1 | -7/+19 |
| * | ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. | Johnny Chen | 2011-04-05 | 1 | -2/+10 |
| * | Make second source operand of LDRD pre/post explicit. | Jim Grosbach | 2011-04-05 | 2 | -8/+28 |
| * | Constants with multiple encodings (ARM): | Johnny Chen | 2011-04-05 | 1 | -2/+3 |
| * | Check for invalid register encodings for UMAAL and friends where: | Johnny Chen | 2011-04-05 | 1 | -2/+49 |
| * | Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/... | Owen Anderson | 2011-04-05 | 2 | -41/+56 |
| * | Revamp the SjLj "dispatch setup" intrinsic. | Bill Wendling | 2011-04-05 | 2 | -4/+4 |
| * | Just use BL all the time. It's safer that way. | Eric Christopher | 2011-04-05 | 1 | -9/+1 |
| * | Fix SRS/SRSW encoding bits. | Johnny Chen | 2011-04-05 | 1 | -0/+4 |
| * | A8.6.105 MUL | Johnny Chen | 2011-04-04 | 1 | -1/+3 |
| * | RFE encoding should also specify the "should be" encoding bits. | Johnny Chen | 2011-04-04 | 3 | -28/+49 |
| * | Fix incorrect alignment for NEON VST2b32_UPD. | Johnny Chen | 2011-04-04 | 1 | -7/+132 |
| * | - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT | Bruno Cardoso Lopes | 2011-04-04 | 7 | -32/+240 |
| * | Do some peephole optimizations to remove pointless VMOVs from Neon to integer | Cameron Zwarich | 2011-04-02 | 1 | -0/+31 |
| * | Fixed a bug in disassembly of STR_POST, where the immediate is the second ope... | Johnny Chen | 2011-04-02 | 1 | -5/+13 |
| * | Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. | Johnny Chen | 2011-04-01 | 1 | -0/+1 |
| * | MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDI... | Johnny Chen | 2011-04-01 | 1 | -0/+1 |
