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* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-198-16/+142
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-183-1/+80
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-172-9/+27
* ARM: Deduplicate ConstantPoolValues.Benjamin Kramer2013-09-162-47/+36
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-3/+3
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-138-31/+31
* [ARMv8] Emit the proper .fpu directive.Joey Gouly2013-09-131-3/+6
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-123-31/+27
* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
* Remove unused private member in ARMAsmPrinter.cpp.Logan Chien2013-09-101-1/+1
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-094-36/+121
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-2/+5
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-057-20/+27
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-054-7/+47
* Reverting 190043 for now.Tilmann Scheller2013-09-053-23/+3
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-053-3/+23
* ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.Jim Grosbach2013-09-041-0/+7
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-1/+4
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ...Silviu Baranga2013-09-041-78/+54
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+11
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-2/+7
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-021-7/+2
* ARM: Default to Swift when compiling for iOS 6 or later.Tilmann Scheller2013-09-021-2/+7
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-012-81/+80
* Revert "ARM: Improve pattern for isel mul of vector by scalar."Michael Gottesman2013-08-301-11/+0
* ARM: Improve pattern for isel mul of vector by scalar.Jim Grosbach2013-08-291-0/+11
* Clean up some usage of Triple. The base class has methods for determining if...Cameron Esfahani2013-08-293-6/+5
* [ARMv8]Joey Gouly2013-08-282-14/+20
* ARM: Use "dmb sy" for barriers on M-class CPUsTim Northover2013-08-281-1/+4
* [ARMv8] Add a missing IsThumb to t2LDAEXD.Joey Gouly2013-08-281-1/+1
* ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.Tim Northover2013-08-281-8/+6
* ARM: add patterns for vqdmlal with separate vqdmull and vqaddsTim Northover2013-08-281-0/+38
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-275-27/+218
* [ARMv8] Add some negative tests for the recent VFP/NEON instructions.Joey Gouly2013-08-272-2/+7
* ARM: add natural patterns for vaddhl and vsubhl.Tim Northover2013-08-271-0/+14
* Revert "Fix the build broken by r189315." and "Move everything depending on O...Charles Davis2013-08-272-79/+81
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-08-272-81/+79
* ARM: Constrain regclass for TSTri instruction.Jim Grosbach2013-08-261-0/+2
* ARM: FastISel verifier error cleanup.Jim Grosbach2013-08-261-0/+7
* ARM: Fix ELF global base reg intialization.Jim Grosbach2013-08-261-3/+8
* [ARM] Fix another ARM FastISel -verify-machineinstrs issue.Joey Gouly2013-08-231-0/+4
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-234-6/+31
* ARM: make sure ARM-mode pseudo-inst requires IsARMTim Northover2013-08-231-1/+1
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-222-9/+105
* Fix ARM vcvt encoding when the number of fractional bits is zero.Mihai Popa2013-08-221-0/+19
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-221-0/+4
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-2/+9
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-227-326/+137
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