| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal | Dan Gohman | 2008-04-12 | 1 | -3/+0 |
| * | Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. | Evan Cheng | 2008-03-31 | 2 | -12/+0 |
| * | Add explicit keywords. | Dan Gohman | 2008-03-25 | 1 | -1/+1 |
| * | Add more patterns to match in the integer comparison test harnesses. | Scott Michel | 2008-03-20 | 3 | -9/+8 |
| * | Use PassManagerBase instead of FunctionPassManager for functions | Dan Gohman | 2008-03-11 | 2 | -4/+4 |
| * | - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. | Scott Michel | 2008-03-10 | 1 | -9/+7 |
| * | Default ISD::PREFETCH to expand. | Evan Cheng | 2008-03-10 | 1 | -1/+0 |
| * | Integer comparison tests for CellSPU. | Scott Michel | 2008-03-10 | 4 | -75/+182 |
| * | Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's | Scott Michel | 2008-03-10 | 1 | -0/+3 |
| * | cell really does support cross-regclass moves, because R3 is in lots of diffe... | Chris Lattner | 2008-03-09 | 1 | -4/+9 |
| * | Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ... | Evan Cheng | 2008-03-08 | 1 | -0/+1 |
| * | Refine Cell's i64 constant generation code to cover more constants where the | Scott Michel | 2008-03-06 | 1 | -7/+28 |
| * | - Fix support for "special" i64 immediates that can be loaded | Scott Michel | 2008-03-05 | 4 | -647/+361 |
| * | Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ... | Evan Cheng | 2008-02-28 | 1 | -1/+1 |
| * | Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool | Bill Wendling | 2008-02-26 | 1 | -3/+3 |
| * | Merge current work back to tree to minimize diffs and drift. Major highlights | Scott Michel | 2008-02-23 | 9 | -993/+1903 |
| * | Fix newly-introduced 4.3 warnings | Anton Korobeynikov | 2008-02-20 | 3 | -8/+8 |
| * | I cannot find a libgcc function for this builtin. Therefor expanding it to a... | Andrew Lenharth | 2008-02-16 | 1 | -1/+2 |
| * | Rewrite tblgen handling of subtarget features so | Dale Johannesen | 2008-02-14 | 1 | -0/+1 |
| * | Fix single precision FP constants on SPU. They are actually legal, | Nate Begeman | 2008-02-14 | 3 | -20/+9 |
| * | Move some useful operands up into the all-targets .td | Nate Begeman | 2008-02-14 | 1 | -3/+0 |
| * | Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits | Dan Gohman | 2008-02-13 | 2 | -2/+2 |
| * | don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS. | Chris Lattner | 2008-02-13 | 1 | -11/+3 |
| * | Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. | Dan Gohman | 2008-02-13 | 2 | -8/+7 |
| * | Rename MRegisterInfo to TargetRegisterInfo. | Dan Gohman | 2008-02-10 | 5 | -7/+9 |
| * | It's not always safe to fold movsd into xorpd, etc. Check the alignment of th... | Evan Cheng | 2008-02-08 | 2 | -5/+8 |
| * | Move to getCALLSEQ_END to ensure CALLSEQ_END node produces a flag. This is co... | Evan Cheng | 2008-02-05 | 1 | -2/+7 |
| * | Dwarf requires variable entries to be in the source order. Right now, since w... | Evan Cheng | 2008-02-04 | 1 | -1/+0 |
| * | Get rid of the annoying blank lines before labels. | Evan Cheng | 2008-02-02 | 1 | -1/+0 |
| * | SDIsel processes llvm.dbg.declare by recording the variable debug information... | Evan Cheng | 2008-02-02 | 1 | -0/+1 |
| * | Add an extra operand to LABEL nodes which distinguishes between debug, EH, or... | Evan Cheng | 2008-01-31 | 1 | -3/+3 |
| * | Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a prope... | Evan Cheng | 2008-01-30 | 2 | -14/+0 |
| * | More cleanups for CellSPU: | Scott Michel | 2008-01-30 | 15 | -458/+389 |
| * | Factor the addressing mode and the load/store VT out of LoadSDNode | Dan Gohman | 2008-01-30 | 1 | -2/+2 |
| * | Overhaul Cell SPU's addressing mode internals so that there are now | Scott Michel | 2008-01-29 | 8 | -680/+566 |
| * | Forward progress: crtbegin.c now compiles successfully! | Scott Michel | 2008-01-17 | 4 | -149/+248 |
| * | This commit changes: | Chris Lattner | 2008-01-17 | 1 | -3/+11 |
| * | rename SDTRet -> SDTNone. | Chris Lattner | 2008-01-15 | 1 | -1/+1 |
| * | improve cygwin compatibility, patch by Sam Bishop | Chris Lattner | 2008-01-12 | 1 | -1/+1 |
| * | More CellSPU refinements: | Scott Michel | 2008-01-11 | 2 | -15/+36 |
| * | More CellSPU refinement and progress: | Scott Michel | 2008-01-11 | 7 | -343/+370 |
| * | no need to explicitly clear these fields. | Chris Lattner | 2008-01-07 | 1 | -1/+0 |
| * | remove MachineOpCode typedef. | Chris Lattner | 2008-01-07 | 1 | -2/+2 |
| * | Move even more functionality from MRegisterInfo into TargetInstrInfo. | Owen Anderson | 2008-01-07 | 4 | -59/+52 |
| * | rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. | Chris Lattner | 2008-01-06 | 1 | -1/+1 |
| * | Change the 'isStore' inferrer to look for 'SDNPMayStore' | Chris Lattner | 2008-01-06 | 1 | -171/+169 |
| * | Move some more instruction creation methods from RegisterInfo into InstrInfo. | Owen Anderson | 2008-01-01 | 4 | -201/+196 |
| * | Fix a problem where lib/Target/TargetInstrInfo.h would include and use | Chris Lattner | 2008-01-01 | 2 | -3/+2 |
| * | Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the | Owen Anderson | 2007-12-31 | 3 | -37/+43 |
| * | Rename SSARegMap -> MachineRegisterInfo in keeping with the idea | Chris Lattner | 2007-12-31 | 3 | -56/+44 |
