index
:
external_llvm.git
replicant-6.0
Unnamed repository; edit this file 'description' to name the repository.
git repository hosting
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
lib
/
Target
/
Hexagon
/
HexagonInstrInfo.td
Commit message (
Expand
)
Author
Age
Files
Lines
*
Update aosp/master LLVM for rebase to r230699.
Stephen Hines
2015-03-23
1
-2015
/
+4847
*
Update aosp/master LLVM for rebase to r222494.
Stephen Hines
2014-12-02
1
-10
/
+89
*
Update LLVM for 3.5 rebase (r209712).
Stephen Hines
2014-05-29
1
-6
/
+8
*
Hexagon: Pass to replace tranfer/copy instructions into combine instruction
Jyotsna Verma
2013-05-14
1
-0
/
+6
*
Hexagon: Set accessSize and addrMode on all load/store instructions.
Jyotsna Verma
2013-05-07
1
-37
/
+62
*
Hexagon - Add peephole optimizations for zero extends.
Pranav Bhandarkar
2013-05-02
1
-0
/
+21
*
Hexagon: Use multiclass for Jump instructions.
Jyotsna Verma
2013-05-01
1
-123
/
+149
*
Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
Jyotsna Verma
2013-04-23
1
-79
/
+82
*
Hexagon: Remove assembler mapped instruction definitions.
Jyotsna Verma
2013-04-23
1
-47
/
+53
*
Hexagon: Set isPredicatedNew flag on predicate new instructions.
Jyotsna Verma
2013-04-12
1
-12
/
+11
*
Hexagon: Set isPredicatedFlase flag for all the instructions with negated pre...
Jyotsna Verma
2013-04-12
1
-11
/
+11
*
Hexagon: Replace switch-case in isDotNewInst with TSFlags.
Jyotsna Verma
2013-03-28
1
-4
/
+5
*
Hexagon: Use multiclass for gp-relative instructions.
Jyotsna Verma
2013-03-28
1
-439
/
+1
*
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
Jyotsna Verma
2013-03-26
1
-28
/
+48
*
Hexagon: Add patterns for zero extended loads from i1->i64.
Jyotsna Verma
2013-03-08
1
-0
/
+12
*
Hexagon: Add support to lower block address.
Jyotsna Verma
2013-03-07
1
-0
/
+9
*
reverting patch 176508.
Jyotsna Verma
2013-03-05
1
-9
/
+0
*
Hexagon: Add support for lowering block address.
Jyotsna Verma
2013-03-05
1
-0
/
+9
*
Hexagon: Add encoding bits to the TFR64 instructions.
Jyotsna Verma
2013-03-05
1
-20
/
+46
*
Hexagon: Change insn class to support instruction encoding.
Jyotsna Verma
2013-02-14
1
-4
/
+4
*
Move MRI liveouts to Hexagon return instructions.
Jakob Stoklund Olesen
2013-02-05
1
-1
/
+1
*
Hexagon: Add V4 combine instructions and some more Def Pats for V2.
Jyotsna Verma
2013-02-04
1
-8
/
+53
*
Use multiclass for post-increment store instructions.
Jyotsna Verma
2013-01-29
1
-104
/
+63
*
Add constant extender support for MInst type instructions.
Jyotsna Verma
2013-01-29
1
-23
/
+37
*
Remove more unnecessary # operators with nothing to paste proceeding them.
Craig Topper
2013-01-07
1
-22
/
+22
*
Remove # from the beginning and end of def names. The # is a paste operator a...
Craig Topper
2013-01-07
1
-42
/
+42
*
Add constant extender support to GP-relative load/store instructions.
Jyotsna Verma
2012-12-20
1
-13
/
+18
*
Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading...
Jyotsna Verma
2012-12-04
1
-11
/
+70
*
Add constant extender support to ALU32 instructions for V2.
Jyotsna Verma
2012-12-04
1
-51
/
+79
*
Move all operand definitions into HexagonOperands.td
Jyotsna Verma
2012-12-04
1
-53
/
+0
*
Move generic Hexagon subtarget information into Hexagon.td
Jyotsna Verma
2012-12-04
1
-64
/
+0
*
Define store instructions with base+immediate offset addressing mode
Jyotsna Verma
2012-12-03
1
-101
/
+78
*
Define load instructions with base+immediate offset addressing mode
Jyotsna Verma
2012-12-03
1
-203
/
+73
*
Use multiclass for the load instructions with MEMri operand.
Jyotsna Verma
2012-11-30
1
-184
/
+66
*
Use multiclass for the store instructions with MEMri operand.
Jyotsna Verma
2012-11-30
1
-83
/
+64
*
Use multiclass for 'transfer' instructions.
Jyotsna Verma
2012-11-29
1
-79
/
+97
*
Renamed HexagonImmediates.td -> HexagonOperands.td.
Jyotsna Verma
2012-11-21
1
-1
/
+1
*
Added multiclass for post-increment load instructions.
Jyotsna Verma
2012-11-14
1
-126
/
+64
*
Test commit.
Jyotsna Verma
2012-11-13
1
-0
/
+1
*
Use the relationship models infrastructure to add two relations - getPredOpcode
Pranav Bhandarkar
2012-11-01
1
-193
/
+119
*
[Hexagon] Don't mark callee saved registers as clobbered by a tail call
Arnold Schwaighofer
2012-08-13
1
-9
/
+3
*
Remove variable_ops from call instructions in most targets.
Jakob Stoklund Olesen
2012-07-13
1
-5
/
+5
*
Fix typos found by http://github.com/lyda/misspell-check
Benjamin Kramer
2012-06-02
1
-1
/
+1
*
Revert 156634 upon request until code improvement changes are made.
Brendon Cahoon
2012-05-14
1
-125
/
+108
*
Hexagon constant extender support.
Brendon Cahoon
2012-05-11
1
-108
/
+125
*
Hexagon V5 FP Support.
Sirish Pande
2012-05-10
1
-20
/
+54
*
Extensions of Hexagon V4 instructions.
Sirish Pande
2012-05-03
1
-859
/
+1332
*
Revert r155365, r155366, and r155367. All three of these have regression
Chandler Carruth
2012-04-23
1
-1354
/
+794
*
Hexagon V5 (floating point) support.
Sirish Pande
2012-04-23
1
-657
/
+1212
*
Support for Hexagon architectural feature, new value jump.
Sirish Pande
2012-04-23
1
-4
/
+5
[next]