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* Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-222-57/+0
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-214-19/+20
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-2/+2
* Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma2013-02-2010-32/+336
* Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h withJyotsna Verma2013-02-191-28/+60
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-151-33/+25
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+12
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-136-1052/+224
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-114-382/+1470
* Implement HexagonInstrInfo::analyzeCompare.Krzysztof Parzyszek2013-02-112-0/+86
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-052-1/+214
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-051-102/+70
* Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen2013-02-052-11/+10
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-051-16/+143
* Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma2013-02-043-8/+135
* Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".Jyotsna Verma2013-02-013-504/+33
* Add appropriate TSFlags to the instructions that must be always extended.Jyotsna Verma2013-02-011-148/+147
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-28/+25
* Use multiclass for post-increment store instructions.Jyotsna Verma2013-01-294-346/+125
* Add constant extender support for MInst type instructions.Jyotsna Verma2013-01-292-75/+151
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-1/+7
* Add indexed load/store instructions for offset validation check.Jyotsna Verma2013-01-171-0/+4
* Improve r172468: const_cast is not needed hereDmitri Gribenko2013-01-141-3/+2
* Fix Another CastDavid Greene2013-01-141-1/+2
* Remove more unnecessary # operators with nothing to paste proceeding them.Craig Topper2013-01-072-40/+40
* Remove # from the beginning and end of def names. The # is a paste operator a...Craig Topper2013-01-072-66/+66
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-072-13/+1
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-0215-30/+30
* Remove Function::getParamAttributes and use the AttributeSet accessor methods...Bill Wendling2012-12-301-1/+1
* Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.Jakub Staszak2012-12-291-0/+0
* Add constant extender support to GP-relative load/store instructions.Jyotsna Verma2012-12-202-44/+42
* Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.Jyotsna Verma2012-12-203-40/+26
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling2012-12-191-1/+1
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
* [CMake] Update dependencies to intrinsics_gen corresponding to r169711.NAKAMURA Takumi2012-12-101-2/+2
* In hexagon convertToHardwareLoop, don't deref end() iteratorMatthew Curtis2012-12-071-7/+14
* Define new-value store instructions with base+immediate addressing modeJyotsna Verma2012-12-051-128/+53
* Use multiclass to define store instructions with base+immediate offsetJyotsna Verma2012-12-051-138/+68
* Fix misplaced closing brace.Matthew Curtis2012-12-051-1/+2
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-041-352/+116
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading...Jyotsna Verma2012-12-043-17/+97
* Add constant extender support to ALU32 instructions for V2.Jyotsna Verma2012-12-041-51/+79
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-048-15/+15
* Move all operand definitions into HexagonOperands.tdJyotsna Verma2012-12-042-53/+57
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