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* Hexagon: Add emitFrameIndexDebugValue function to emit debug information.Jyotsna Verma2013-03-292-0/+14
* Hexagon: Disable DwarfUsesInlineInfoSection flag.Jyotsna Verma2013-03-291-1/+0
* Hexagon: Replace switch-case in isDotNewInst with TSFlags.Jyotsna Verma2013-03-284-176/+26
* Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.Jyotsna Verma2013-03-281-0/+2
* Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma2013-03-282-1094/+204
* Switch to LLVM support function abs64 to keep VS2008 happy.Tim Northover2013-03-271-1/+1
* Hexagon: Disable optimizations at O0.Jyotsna Verma2013-03-271-18/+31
* Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma2013-03-262-186/+48
* Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/...Jyotsna Verma2013-03-261-41/+0
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w...Jyotsna Verma2013-03-225-494/+483
* Hexagon: Removed asserts regarding alignment and offset.Jyotsna Verma2013-03-141-5/+4
* Cleanup #includes.Jakub Staszak2013-03-101-1/+2
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+3
* Hexagon: Add patterns for zero extended loads from i1->i64.Jyotsna Verma2013-03-082-0/+24
* Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma2013-03-071-0/+10
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-074-0/+28
* reverting patch 176508.Jyotsna Verma2013-03-054-28/+0
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-054-0/+28
* Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma2013-03-051-0/+23
* Hexagon: Use MO operand flags to mark constant extended instructions.Jyotsna Verma2013-03-053-471/+43
* Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma2013-03-051-20/+46
* Added FIXME for future Hexagon cleanup.Andrew Trick2013-03-021-0/+3
* Hexagon: Add constant extender support framework.Jyotsna Verma2013-03-014-23/+228
* Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-222-57/+0
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-214-19/+20
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-2/+2
* Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma2013-02-2010-32/+336
* Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h withJyotsna Verma2013-02-191-28/+60
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-151-33/+25
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+12
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-136-1052/+224
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-114-382/+1470
* Implement HexagonInstrInfo::analyzeCompare.Krzysztof Parzyszek2013-02-112-0/+86
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-052-1/+214
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-051-102/+70
* Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen2013-02-052-11/+10
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-051-16/+143
* Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma2013-02-043-8/+135
* Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".Jyotsna Verma2013-02-013-504/+33
* Add appropriate TSFlags to the instructions that must be always extended.Jyotsna Verma2013-02-011-148/+147
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-28/+25
* Use multiclass for post-increment store instructions.Jyotsna Verma2013-01-294-346/+125
* Add constant extender support for MInst type instructions.Jyotsna Verma2013-01-292-75/+151
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-1/+7