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path: root/lib/Target/Mips/Mips16InstrInfo.cpp
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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-0/+3
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-2/+2
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-4/+2
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-41/+33
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-0/+1
* Update to LLVM 3.5a.Stephen Hines2014-04-241-94/+72
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-151-0/+6
* Mips16InstrInfo.cpp: Use <cctype> instead of <ctype.h>NAKAMURA Takumi2013-11-131-2/+1
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-131-1/+47
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-121-1/+2
* Remove unused stdio.h includesDmitri Gribenko2013-08-181-3/+1
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-141-2/+2
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-2/+2
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-28/+109
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-131-2/+2
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-291-10/+9
* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-251-55/+0
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-241-53/+0
* Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-241-22/+0
* Expand pseudos/macros:Reed Kotler2013-02-201-0/+56
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-191-1/+16
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-191-0/+26
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+8
* Expand pseudo/macro BteqzT8SltuX16 . There is no test case becauseReed Kotler2013-02-181-0/+5
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+3
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+3
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-181-0/+15
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-161-4/+9
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-161-8/+6
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-3/+12
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-3/+72
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-191-19/+33
* fix most of remaining issues with large frames.Reed Kotler2012-12-201-8/+131
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-311-1/+17
* Change mips16 delay slot jumps to non delay slot forms by default.Reed Kotler2012-10-301-1/+1
* Add conditional branch instructions and their patterns.Reed Kotler2012-10-171-2/+29
* Div, Rem int/unsigned int Reed Kotler2012-10-121-8/+15
* 1. Add load/store words from the stackReed Kotler2012-09-281-2/+19
* mips16 fixes.Akira Hatanaka2012-09-141-1/+1
* Remove unused private field to silence build warning.Craig Topper2012-08-231-1/+1
* Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka2012-08-021-0/+4
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-311-1/+6
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-311-0/+123
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