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* Refactor ABI code in the PowerPC backend.Tilmann Scheller2009-07-031-33/+33
| | | | | | | | | | | | Make CalculateParameterAndLinkageAreaSize() Darwin-specific. Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin(). Rename MachoABI to DarwinABI for consistency. Rename ELF ABI to SVR4 ABI for consistency. Factor out common call return lowering between the Darwin and SVR4 ABI. Factor out common call lowering between the Darwin and SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the SVR4 ABI for PowerPC.Tilmann Scheller2009-07-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Implement LowerFORMAL_ARGUMENTS_SVR4(). Implement LowerCALL_SVR4(). Add support for split arguments. Implement by value parameter passing for aggregates. Add support for variable argument lists. Create the spill area for argument registers of variable argument functions no longer at a fixed offset. Make sure callee saved registers are spilled to the correct stack offsets. Change allocation order of non-volatile floating-point registers. Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls. Add support for variable argument calls with Vector arguments. Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers. Stop creating illegal i8 values in LowerVASTART(). Add memory access width hints. Make sure to reserve space on the stack for the frame pointer. When using the SVR4 ABI, reserve r13 for the Small Data Area pointer. Assure that the frame pointer is spilled to the correct location on the stack. Some FP registers were not marked as volatile. Make sure the i64 words from a long double are passed either both in registers or both on the stack. Only put integer arguments in registers which are not marked with the inreg flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-0/+2
| | | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RM pseudoreg for the rounding mode, whichDale Johannesen2008-10-291-143/+163
| | | | | | | | | | | | | | | | | | | allows ppcf128->int conversion to work with DeadInstructionElimination. This is now turned off but RM is harmless. It does not do a complete job of modeling the rounding mode. Revert marking MFCR as using all 7 CR subregisters; while correct, this caused the problem in PR 2964, plus the local RA crash noted in the comments. This was needed to make DeadInstructionElimination, but as we are not running that, it is backed out for now. Eventually it should go back in and the other problems fixed where they're broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark MFCR as reading all condition code registers.Dale Johannesen2008-10-241-0/+2
| | | | | | | | | Prevents some more overzealous deletions (mostly in AltiVec code). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58121 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark defs and uses of CTR and LR correctly.Dale Johannesen2008-10-231-6/+16
| | | | | | | | | | Prevents DeadMachineInstructionElim from thinking things like MTCTR are dead (fixes massive testsuite breakage at -O0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58043 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix warnings about mb/me being potentially usedDuncan Sands2008-10-161-2/+2
| | | | | | | uninitialized in these functions with gcc-4.3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57635 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's asChris Lattner2008-10-111-2/+2
| | | | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-14/+14
| | | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement partial-word binary atomics on ppc.Dale Johannesen2008-08-281-0/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 32 & 64 bit versions of PPC atomicDale Johannesen2008-08-251-0/+22
| | | | | | | | binary primitives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove PPC-specific lowering for atomics; theDale Johannesen2008-08-251-29/+6
| | | | | | | | | | generic stuff works fine. Mark rewritten cmp-and-swap as not using CR1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement __sync_synchronize on ppc32. Patch by Gary Benson.Dale Johannesen2008-08-221-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55186 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite ppc code generated for __sync_{bool|val}_compare_and_swapDale Johannesen2008-08-221-4/+7
| | | | | | | | | so that lwarx and stwcx are always executed the same number of times. This is important for performance, I'm told. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement ISD::TRAP support on PPCNate Begeman2008-08-111-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!Evan Cheng2008-07-121-29/+52
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53505 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide correct encoding for PPC LWARX instructions.Anton Korobeynikov2008-06-271-2/+2
| | | | | | | Patch by Gary Benson! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52828 91177308-0d34-0410-b5e6-96231b3b80d8
* Tail call optimization improvements:Arnold Schwaighofer2008-04-301-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
* 64-bit atomic operations.Evan Cheng2008-04-191-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49949 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC32 atomic operations.Evan Cheng2008-04-191-0/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49947 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-12/+0
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-101-4/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).Chris Lattner2008-03-071-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48027 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to workChris Lattner2008-03-071-6/+3
| | | | | | | with 32 or 64-bit operands/results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-2/+5
| | | | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
* Final de-tabification.Bill Wendling2008-02-271-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
* Make register scavenging happy by not using a reg (CR0) that isn't definedNate Begeman2008-02-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-3/+3
| | | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
* remove explicit sets of 'neverHasSideEffects' that can now be Chris Lattner2008-01-101-1/+1
| | | | | | | inferred from the instr patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45824 91177308-0d34-0410-b5e6-96231b3b80d8
* get def use info more correct.Chris Lattner2008-01-101-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-4/+8
| | | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some isStore flags that are now inferred automatically.Chris Lattner2008-01-061-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45652 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the "isRemat" instruction as never having side effects.Bill Wendling2007-12-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45190 91177308-0d34-0410-b5e6-96231b3b80d8
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-0/+2
| | | | | | re-materializable and they should not be spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial commit of the machine code LICM pass. It successfully hoists this:Bill Wendling2007-12-071-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _foo: li r2, 0 LBB1_1: ; bb li r5, 0 stw r5, 0(r3) addi r2, r2, 1 addi r3, r3, 4 cmplw cr0, r2, r4 bne cr0, LBB1_1 ; bb LBB1_2: ; return blr to: _foo: li r2, 0 li r5, 0 LBB1_1: ; bb stw r5, 0(r3) addi r2, r2, 1 addi r3, r3, 4 cmplw cr0, r2, r4 bne cr0, LBB1_1 ; bb LBB1_2: ; return blr ZOMG!! :-) Moar to come... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44687 91177308-0d34-0410-b5e6-96231b3b80d8
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-131-7/+8
| | | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-1/+2
| | | | | | | Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with ↵Evan Cheng2007-10-231-2/+4
| | | | | | right callee-saved defs set for ppc64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43248 91177308-0d34-0410-b5e6-96231b3b80d8
* Next PPC long double bits: ppcf128->i32 conversion.Dale Johannesen2007-10-101-0/+46
| | | | | | | | Surprisingly complicated. Adds getTargetNode for 2 outputs, no inputs (missing). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42822 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
* Some out operands were incorrectly specified as input operands.Evan Cheng2007-08-011-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40697 91177308-0d34-0410-b5e6-96231b3b80d8
* No more noResults.Evan Cheng2007-07-211-7/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops. These stores actually produce results.Evan Cheng2007-07-201-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40074 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-172/+179
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-181-0/+1164
alignment is equal to the stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40004 91177308-0d34-0410-b5e6-96231b3b80d8
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