| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | R600: Signed literals are 64bits wide | Vincent Lejeune | 2013-05-02 | 1 | -3/+3 |
| * | R600: If previous bundle is dot4, PV valid chan is always X | Vincent Lejeune | 2013-05-02 | 1 | -38/+51 |
| * | R600: Improve asmPrint of ALU clause | Vincent Lejeune | 2013-05-02 | 3 | -4/+20 |
| * | R600: Prettier asmPrint of Alu | Vincent Lejeune | 2013-05-02 | 4 | -13/+45 |
| * | R600: Use new tablegen syntax for patterns | Tom Stellard | 2013-05-02 | 3 | -447/+381 |
| * | R600/SI: remove nonsense select pattern | Tom Stellard | 2013-05-02 | 1 | -8/+1 |
| * | R600: Always use texture cache for compute shaders | Vincent Lejeune | 2013-04-30 | 1 | -2/+6 |
| * | R600: use native for alu | Vincent Lejeune | 2013-04-30 | 4 | -4/+135 |
| * | R600: Packetize instructions | Vincent Lejeune | 2013-04-30 | 6 | -3/+464 |
| * | R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips | Vincent Lejeune | 2013-04-30 | 5 | -32/+105 |
| * | R600: Add a Bank Swizzle operand | Vincent Lejeune | 2013-04-30 | 4 | -11/+19 |
| * | R600: Take inner dependency into tex/vtx clauses | Vincent Lejeune | 2013-04-30 | 1 | -0/+34 |
| * | R600: Turn TEX/VTX into native instructions | Vincent Lejeune | 2013-04-30 | 3 | -15/+50 |
| * | R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions | Vincent Lejeune | 2013-04-30 | 9 | -58/+95 |
| * | R600: Add some new processor variants | Vincent Lejeune | 2013-04-30 | 2 | -1/+3 |
| * | R600: Clean up instruction class definitions | Vincent Lejeune | 2013-04-30 | 1 | -23/+14 |
| * | R600: config section now reports use of killgt | Vincent Lejeune | 2013-04-30 | 1 | -0/+4 |
| * | R600: Use correct CF_END instruction on Northern Island GPUs | Tom Stellard | 2013-04-29 | 1 | -1/+1 |
| * | R600: Fix encoding of CF_END_{EG, R600} instructions | Tom Stellard | 2013-04-29 | 1 | -0/+1 |
| * | R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE | Tom Stellard | 2013-04-26 | 1 | -0/+2 |
| * | R600: Initialize BooleanVectorContents | Tom Stellard | 2013-04-24 | 1 | -0/+1 |
| * | R600: Use SHT_PROGBITS for the .AMDGPU.config section | Tom Stellard | 2013-04-24 | 1 | -1/+1 |
| * | R600: Use .AMDGPU.config section to emit stacksize | Vincent Lejeune | 2013-04-23 | 5 | -16/+25 |
| * | R600: Add CF_END | Vincent Lejeune | 2013-04-23 | 3 | -44/+77 |
| * | Remove unused DwarfSectionOffsetDirective string | Matt Arsenault | 2013-04-22 | 1 | -2/+0 |
| * | ArrayRefize getMachineNode(). No functionality change. | Michael Liao | 2013-04-19 | 2 | -2/+2 |
| * | R600: Add pattern for the BFI_INT instruction | Tom Stellard | 2013-04-19 | 3 | -0/+24 |
| * | R600/SI: Use InstFlag for VOP3 modifier operands | Tom Stellard | 2013-04-19 | 2 | -15/+14 |
| * | R600: Make Export Instruction not duplicable | Vincent Lejeune | 2013-04-17 | 1 | -1/+3 |
| * | R600: Export is emitted as a CF_NATIVE inst | Vincent Lejeune | 2013-04-17 | 2 | -14/+9 |
| * | R600: Emit used GPRs count | Vincent Lejeune | 2013-04-17 | 2 | -8/+41 |
| * | R600/SI: Emit config values in register value pairs. | Tom Stellard | 2013-04-15 | 2 | -3/+38 |
| * | R600/SI: Emit configuration value in the .AMDGPU.config ELF section | Tom Stellard | 2013-04-15 | 1 | -1/+9 |
| * | R600: Emit ELF formatted code rather than raw ISA. | Tom Stellard | 2013-04-15 | 5 | -12/+63 |
| * | R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable] | NAKAMURA Takumi | 2013-04-11 | 1 | -0/+1 |
| * | Whitespace. | NAKAMURA Takumi | 2013-04-11 | 1 | -2/+1 |
| * | R600/SI: Add pattern for AMDGPUurecip | Michel Danzer | 2013-04-10 | 3 | -3/+13 |
| * | R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr | Vincent Lejeune | 2013-04-10 | 1 | -1/+10 |
| * | R600/SI: dynamical figure out the reg class of MIMG | Christian Konig | 2013-04-10 | 6 | -2/+63 |
| * | R600/SI: adjust writemask to only the used components | Christian Konig | 2013-04-10 | 4 | -2/+91 |
| * | R600/SI: remove image sample writemask | Christian Konig | 2013-04-10 | 2 | -14/+13 |
| * | R600: Control Flow support for pre EG gen | Vincent Lejeune | 2013-04-08 | 3 | -72/+240 |
| * | R600/SI: Add support for buffer stores v2 | Tom Stellard | 2013-04-05 | 8 | -4/+99 |
| * | R600/SI: Use same names for corresponding MUBUF operands and encoding fields | Tom Stellard | 2013-04-05 | 2 | -27/+27 |
| * | R600: Add RV670 processor | Tom Stellard | 2013-04-05 | 1 | -0/+1 |
| * | R600/SI: Add processor types for each SI variant | Tom Stellard | 2013-04-05 | 2 | -3/+8 |
| * | R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 | Tom Stellard | 2013-04-05 | 1 | -2/+5 |
| * | R600: Use a mask for offsets when encoding instructions | Vincent Lejeune | 2013-04-04 | 1 | -2/+5 |
| * | R600: Fix wrong address when substituting ENDIF | Vincent Lejeune | 2013-04-04 | 1 | -1/+1 |
| * | R600: Take export into account when computing cf address | Vincent Lejeune | 2013-04-04 | 1 | -0/+4 |
