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path: root/lib/Target/Target.td
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* Make LABEL a builtin opcode.Jim Laskey2007-01-261-0/+6
* Comment.Evan Cheng2007-01-121-1/+1
* add a new field needed by the code emitter generator.Chris Lattner2006-11-151-0/+4
* initial steps to getting the predicate on PPC::BLR right.Chris Lattner2006-11-031-0/+11
* remove dead varChris Lattner2006-11-031-1/+0
* Add constraints to Instruction class.Evan Cheng2006-11-011-0/+2
* Move the Imp tblgen class from the X86 backend to common code.Chris Lattner2006-10-121-0/+7
* Add code size to target instruction use it as the 3rd isel sorting tie-breaker.Evan Cheng2006-07-191-0/+3
* Added a Flags field to TargetOperandInfo. Currently the only flag isEvan Cheng2006-05-181-0/+6
* Remove CalleeSavedRegisters from class Target.Evan Cheng2006-05-181-4/+0
* Remove PointerType from class TargetEvan Cheng2006-05-171-4/+0
* Replace "../whatever.td" with "whatever.td", so that out-of-tree backendsVladimir Prus2006-05-161-2/+2
* Improve comment, patch provided by Vladimir Prus!Chris Lattner2006-05-151-1/+3
* Update comment.Chris Lattner2006-05-141-2/+3
* Put PHI/INLINEASM into the correct namespace.Chris Lattner2006-05-011-0/+2
* Renamed AddedCost to AddedComplexity.Evan Cheng2006-04-191-2/+2
* Allow "let AddedCost = n in" to increase pattern complexity.Evan Cheng2006-04-191-0/+3
* Add support for dwarf register numbering.Jim Laskey2006-03-241-0/+21
* Shuffle some includes aroundChris Lattner2006-03-241-1/+2
* Split the valuetypes out of Target.td into ValueTypes.tdChris Lattner2006-03-031-37/+1
* New type v2f32.Evan Cheng2006-03-011-2/+3
* Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bitEvan Cheng2006-02-201-6/+9
* Subtarget feature can now set any variable to any valueEvan Cheng2006-01-271-5/+5
* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-271-3/+11
* New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replaceEvan Cheng2006-01-091-2/+0
* Added field noResults to Instruction.Evan Cheng2005-12-261-0/+1
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-0/+2
* Added support to specify predicates.Evan Cheng2005-12-141-0/+14
* * Added instruction property hasCtrlDep for those which r/w control-flowEvan Cheng2005-12-041-0/+1
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-3/+6
* Add the majority of the vector machien value types we expect to support,Nate Begeman2005-11-291-1/+7
* refix typoChris Lattner2005-11-291-1/+1
* revert my change for the time being, which broke the buildChris Lattner2005-11-291-1/+1
* fix a typo :)Chris Lattner2005-11-281-1/+1
* Capture more operand info, patch by Evan ChengChris Lattner2005-11-191-1/+2
* Also add the new vector value type here, for completeness.Nate Begeman2005-11-181-0/+1
* Add attribute name and type to SubtargetFeatures.Jim Laskey2005-10-261-1/+9
* Plugin new subtarget backend into the build.Jim Laskey2005-10-211-1/+1
* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-191-5/+8
* Push processor descriptions to the top of target and add command line info.Jim Laskey2005-10-191-0/+39
* Pull DAG ISel generation nodes out of the PowerPC backend to where theyChris Lattner2005-10-101-89/+2
* Add a forward defChris Lattner2005-10-041-1/+2
* Now that self referential classes are supported, get rid of a work-around.Chris Lattner2005-09-301-4/+6
* spell this rightChris Lattner2005-08-261-1/+1
* Add a flagChris Lattner2005-08-261-0/+1
* add an enum valueChris Lattner2005-08-251-2/+3
* Split RegisterClass 'Methods' into MethodProtos and MethodBodiesChris Lattner2005-08-191-3/+5
* Require that targets specify a namespace for their register classes.Chris Lattner2005-08-191-1/+4
* Add a new flagChris Lattner2005-08-181-0/+4
* Add some bits that can be set for instructions.Chris Lattner2005-01-021-0/+2