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path: root/lib/Target/Target.td
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* Make LABEL a builtin opcode.Jim Laskey2007-01-261-0/+6
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* Comment.Evan Cheng2007-01-121-1/+1
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* add a new field needed by the code emitter generator.Chris Lattner2006-11-151-0/+4
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* initial steps to getting the predicate on PPC::BLR right.Chris Lattner2006-11-031-0/+11
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* remove dead varChris Lattner2006-11-031-1/+0
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* Add constraints to Instruction class.Evan Cheng2006-11-011-0/+2
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* Move the Imp tblgen class from the X86 backend to common code.Chris Lattner2006-10-121-0/+7
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* Add code size to target instruction use it as the 3rd isel sorting tie-breaker.Evan Cheng2006-07-191-0/+3
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* Added a Flags field to TargetOperandInfo. Currently the only flag isEvan Cheng2006-05-181-0/+6
| | | | | | | | M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be resolved via a callback at runtime. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28387 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove CalleeSavedRegisters from class Target.Evan Cheng2006-05-181-4/+0
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* Remove PointerType from class TargetEvan Cheng2006-05-171-4/+0
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* Replace "../whatever.td" with "whatever.td", so that out-of-tree backendsVladimir Prus2006-05-161-2/+2
| | | | | | | can just add lib/Target to TableGen includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28318 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve comment, patch provided by Vladimir Prus!Chris Lattner2006-05-151-1/+3
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* Update comment.Chris Lattner2006-05-141-2/+3
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* Put PHI/INLINEASM into the correct namespace.Chris Lattner2006-05-011-0/+2
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* Renamed AddedCost to AddedComplexity.Evan Cheng2006-04-191-2/+2
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* Allow "let AddedCost = n in" to increase pattern complexity.Evan Cheng2006-04-191-0/+3
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* Add support for dwarf register numbering.Jim Laskey2006-03-241-0/+21
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* Shuffle some includes aroundChris Lattner2006-03-241-1/+2
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* Split the valuetypes out of Target.td into ValueTypes.tdChris Lattner2006-03-031-37/+1
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* New type v2f32.Evan Cheng2006-03-011-2/+3
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* Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bitEvan Cheng2006-02-201-6/+9
| | | | | | | packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
* Subtarget feature can now set any variable to any valueEvan Cheng2006-01-271-5/+5
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* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-271-3/+11
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* New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replaceEvan Cheng2006-01-091-2/+0
| | | | | | | hasInFlag, hasOutFlag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
* Added field noResults to Instruction.Evan Cheng2005-12-261-0/+1
| | | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-0/+2
| | | | | | | | | * Added a pseudo instruction (for each target) that represent "return void". This is a workaround for lack of optional flag operand (return void is not lowered so it does not have a flag operand.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support to specify predicates.Evan Cheng2005-12-141-0/+14
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* * Added instruction property hasCtrlDep for those which r/w control-flowEvan Cheng2005-12-041-0/+1
| | | | | | | | | | | | chains. * Added DAG node property SDNPHasChain for nodes which r/w control-flow chains. * Renamed SDTVT to SDTOther. * Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT. * Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24586 91177308-0d34-0410-b5e6-96231b3b80d8
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-3/+6
| | | | | | | work. This change has no effect on generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the majority of the vector machien value types we expect to support,Nate Begeman2005-11-291-1/+7
| | | | | | | | and make a few changes to the legalization machinery to support more than 16 types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
* refix typoChris Lattner2005-11-291-1/+1
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* revert my change for the time being, which broke the buildChris Lattner2005-11-291-1/+1
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* fix a typo :)Chris Lattner2005-11-281-1/+1
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* Capture more operand info, patch by Evan ChengChris Lattner2005-11-191-1/+2
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* Also add the new vector value type here, for completeness.Nate Begeman2005-11-181-0/+1
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* Add attribute name and type to SubtargetFeatures.Jim Laskey2005-10-261-1/+9
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* Plugin new subtarget backend into the build.Jim Laskey2005-10-211-1/+1
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* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-191-5/+8
| | | | | | | | Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
* Push processor descriptions to the top of target and add command line info.Jim Laskey2005-10-191-0/+39
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* Pull DAG ISel generation nodes out of the PowerPC backend to where theyChris Lattner2005-10-101-89/+2
| | | | | | | | can be used by other targets. For those targets that want to use it, have at. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23680 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a forward defChris Lattner2005-10-041-1/+2
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* Now that self referential classes are supported, get rid of a work-around.Chris Lattner2005-09-301-4/+6
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* spell this rightChris Lattner2005-08-261-1/+1
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* Add a flagChris Lattner2005-08-261-0/+1
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* add an enum valueChris Lattner2005-08-251-2/+3
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* Split RegisterClass 'Methods' into MethodProtos and MethodBodiesChris Lattner2005-08-191-3/+5
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* Require that targets specify a namespace for their register classes.Chris Lattner2005-08-191-1/+4
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* Add a new flagChris Lattner2005-08-181-0/+4
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* Add some bits that can be set for instructions.Chris Lattner2005-01-021-0/+2
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