| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add processor descriptions for Istanbul and Shanghai. | David Greene | 2009-06-29 | 1 | -0/+4 |
| * | Add feature flags for AVX and FMA and fix some SSE4A feature flag | David Greene | 2009-06-26 | 1 | -0/+10 |
| * | Revert 72707 and 72709, for the moment. | Dale Johannesen | 2009-06-02 | 1 | -2/+0 |
| * | Add missing file. | Dale Johannesen | 2009-06-01 | 1 | -0/+2 |
| * | Update CPU capabilities for AMD machines | Stefanus Du Toit | 2009-05-26 | 1 | -0/+12 |
| * | Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has | Dan Gohman | 2009-02-03 | 1 | -7/+13 |
| * | Add Intel processors core i7 and atom. | Evan Cheng | 2009-01-03 | 1 | -0/+2 |
| * | Do not isel load folding bt instructions for pentium m, core, core2, and AMD ... | Evan Cheng | 2009-01-02 | 1 | -16/+18 |
| * | Move target independent td files from lib/Target/ to include/llvm/Target so t... | Evan Cheng | 2008-11-24 | 1 | -1/+1 |
| * | Accept -march=i586, because gcc does (a synonym | Dale Johannesen | 2008-10-14 | 1 | -0/+1 |
| * | Add ability to override segment (mostly for code emitter purposes). | Anton Korobeynikov | 2008-10-11 | 1 | -0/+2 |
| * | Add lock prefix support to x86. Also add the instructions necessary for the ... | Andrew Lenharth | 2008-03-01 | 1 | -0/+2 |
| * | nocona, core2 and penryn support 64 bit. | Dale Johannesen | 2008-02-15 | 1 | -3/+3 |
| * | SSE 4.1 Intrinsics and detection | Nate Begeman | 2008-02-03 | 1 | -0/+7 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+2 |
| * | Corrected many typing errors. And removed 'nest' parameter handling | Arnold Schwaighofer | 2007-10-12 | 1 | -1/+1 |
| * | We only need to specify the most-implied feature for an architecture. | Bill Wendling | 2007-05-22 | 1 | -33/+21 |
| * | 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. | Bill Wendling | 2007-05-06 | 1 | -3/+5 |
| * | Add an "implies" field to features. This indicates that, if the current | Bill Wendling | 2007-05-04 | 1 | -17/+21 |
| * | Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers | Bill Wendling | 2007-04-25 | 1 | -1/+1 |
| * | Add support for our first SSSE3 instruction "pmulhrsw". | Bill Wendling | 2007-04-10 | 1 | -0/+2 |
| * | Add a description of the X86-64 calling convention and the return | Chris Lattner | 2007-02-26 | 1 | -0/+11 |
| * | Still need to support -mcpu=<> or cross compilation will fail. Doh. | Evan Cheng | 2006-10-06 | 1 | -0/+73 |
| * | Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3,... | Evan Cheng | 2006-10-06 | 1 | -73/+0 |
| * | Committing X86-64 support. | Evan Cheng | 2006-09-08 | 1 | -4/+10 |
| * | ImmMask should be 3 for a two-bit field; Compact X86II | Evan Cheng | 2006-05-18 | 1 | -1/+1 |
| * | getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. | Evan Cheng | 2006-05-18 | 1 | -3/+0 |
| * | Remove PointerType from class Target | Evan Cheng | 2006-05-17 | 1 | -3/+0 |
| * | - Use xor to clear integer registers (set R, 0). | Evan Cheng | 2006-02-01 | 1 | -4/+4 |
| * | * Fix 80-column violations | Chris Lattner | 2006-01-31 | 1 | -16/+16 |
| * | Fix typo. | Jeff Cohen | 2006-01-29 | 1 | -1/+1 |
| * | x86 CPU detection and proper subtarget support | Evan Cheng | 2006-01-27 | 1 | -24/+26 |
| * | PHI and INLINEASM are now built-in instructions provided by Target.td | Chris Lattner | 2006-01-27 | 1 | -1/+0 |
| * | Added preliminary x86 subtarget support. | Evan Cheng | 2006-01-26 | 1 | -0/+69 |
| * | Get closer to fully working scalar FP in SSE regs. This gets singlesource | Nate Begeman | 2005-07-15 | 1 | -1/+1 |
| * | First round of support for doing scalar FP using the SSE2 ISA extension and | Nate Begeman | 2005-07-06 | 1 | -1/+1 |
| * | Add support for the -x86-asm-syntax flag, which can be used to choose between | Chris Lattner | 2004-10-03 | 1 | -0/+14 |
| * | Remove a bunch of ad-hoc target-specific flags that were only used by the | Chris Lattner | 2004-08-11 | 1 | -6/+2 |
| * | Eliminate 3 of the X86 printImplicit* flags. | Chris Lattner | 2004-08-01 | 1 | -7/+1 |
| * | Add support for the printImplicitDefsBefore flag | Chris Lattner | 2004-04-13 | 1 | -1/+3 |
| * | Added the llvm.readport and llvm.writeport intrinsics for x86. These do | John Criswell | 2004-04-08 | 1 | -6/+20 |
| * | Add FP conditional move instructions, which annoyingly have special properties | Chris Lattner | 2004-03-31 | 1 | -2/+4 |
| * | Each instruction now has both an ImmType and a MemType. This describes | Alkis Evlogimenos | 2004-02-28 | 1 | -4/+4 |
| * | Added LLVM copyright header. | John Criswell | 2003-10-21 | 1 | -0/+7 |
| * | Completely eliminate the isVoid TSFlag, shifting over all other fields | Chris Lattner | 2003-08-06 | 1 | -4/+4 |
| * | There is nothing special about noops anymore | Chris Lattner | 2003-08-04 | 1 | -1/+0 |
| * | transition to using let instead of set | Chris Lattner | 2003-08-04 | 1 | -8/+8 |
| * | Add new TableGen instruction definitions | Chris Lattner | 2003-08-03 | 1 | -0/+11 |
| * | Add Target class for X86 target | Chris Lattner | 2003-08-03 | 1 | -0/+17 |
| * | Initial checkin of X86.td file | Chris Lattner | 2003-08-03 | 1 | -0/+17 |
