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* Add processor descriptions for Istanbul and Shanghai.David Greene2009-06-291-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74429 91177308-0d34-0410-b5e6-96231b3b80d8
* Add feature flags for AVX and FMA and fix some SSE4A feature flagDavid Greene2009-06-261-0/+10
| | | | | | | initialization problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-2/+0
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* Add missing file.Dale Johannesen2009-06-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72709 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CPU capabilities for AMD machinesStefanus Du Toit2009-05-261-0/+12
| | | | | | | | | | | | | | | | | - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
* Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware hasDan Gohman2009-02-031-7/+13
| | | | | | | | | | | | | | | SSE2, however it's possible to disable SSE2, and the subtarget support code thinks that if 64-bit implies SSE2 and SSE2 is disabled then 64-bit should also be disabled. Instead, just mark all the 64-bit subtargets as explicitly supporting SSE2. Also, move the code that makes -march=x86-64 enable 64-bit support by default to only apply when there is no explicit subtarget. If you need to specify a subtarget and you want 64-bit code, you'll need to select a subtarget that supports 64-bit code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63575 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Intel processors core i7 and atom.Evan Cheng2009-01-031-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61603 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not isel load folding bt instructions for pentium m, core, core2, and AMD ↵Evan Cheng2009-01-021-16/+18
| | | | | | processors. These are significantly slower than a load followed by a bt of a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-1/+1
| | | | | | they can be distributed along with the header files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
* Accept -march=i586, because gcc does (a synonymDale Johannesen2008-10-141-0/+1
| | | | | | | | | | for pentium). Fixes gcc.target/i386/20000720-1.c gcc.target/i386/pr26826.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57528 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ability to override segment (mostly for code emitter purposes).Anton Korobeynikov2008-10-111-0/+2
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* Add lock prefix support to x86. Also add the instructions necessary for the ↵Andrew Lenharth2008-03-011-0/+2
| | | | | | atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
* nocona, core2 and penryn support 64 bit.Dale Johannesen2008-02-151-3/+3
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* SSE 4.1 Intrinsics and detectionNate Begeman2008-02-031-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Corrected many typing errors. And removed 'nest' parameter handlingArnold Schwaighofer2007-10-121-1/+1
| | | | | | | | | for fastcc from X86CallingConv.td. This means that nested functions are not supported for calling convention 'fastcc'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
* We only need to specify the most-implied feature for an architecture.Bill Wendling2007-05-221-33/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37275 91177308-0d34-0410-b5e6-96231b3b80d8
* 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX.Bill Wendling2007-05-061-3/+5
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* Add an "implies" field to features. This indicates that, if the currentBill Wendling2007-05-041-17/+21
| | | | | | | | | feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36756 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SSSE3 as a feature of Core2. Add MMX registers to the list of registersBill Wendling2007-04-251-1/+1
| | | | | | | clobbered by a call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36448 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for our first SSSE3 instruction "pmulhrsw".Bill Wendling2007-04-101-0/+2
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* Add a description of the X86-64 calling convention and the returnChris Lattner2007-02-261-0/+11
| | | | | | | conventions. This doesn't do anything yet, but may in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34636 91177308-0d34-0410-b5e6-96231b3b80d8
* Still need to support -mcpu=<> or cross compilation will fail. Doh.Evan Cheng2006-10-061-0/+73
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* Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, ↵Evan Cheng2006-10-061-73/+0
| | | | | | SSE3, and 64-bit support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
* Committing X86-64 support.Evan Cheng2006-09-081-4/+10
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* ImmMask should be 3 for a two-bit field; Compact X86IIEvan Cheng2006-05-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28381 91177308-0d34-0410-b5e6-96231b3b80d8
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove PointerType from class TargetEvan Cheng2006-05-171-3/+0
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* - Use xor to clear integer registers (set R, 0).Evan Cheng2006-02-011-4/+4
| | | | | | | | | - Added a new format for instructions where the source register is implied and it is same as the destination register. Used for pseudo instructions that clear the destination register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8
* * Fix 80-column violationsChris Lattner2006-01-311-16/+16
| | | | | | | | * Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'. * Add inline asm constraint specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo.Jeff Cohen2006-01-291-1/+1
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* x86 CPU detection and proper subtarget supportEvan Cheng2006-01-271-24/+26
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* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-271-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
* Added preliminary x86 subtarget support.Evan Cheng2006-01-261-0/+69
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* Get closer to fully working scalar FP in SSE regs. This gets singlesourceNate Begeman2005-07-151-1/+1
| | | | | | | working, and Olden/power. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22441 91177308-0d34-0410-b5e6-96231b3b80d8
* First round of support for doing scalar FP using the SSE2 ISA extension andNate Begeman2005-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the -x86-asm-syntax flag, which can be used to choose betweenChris Lattner2004-10-031-0/+14
| | | | | | | | | Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a bunch of ad-hoc target-specific flags that were only used by theChris Lattner2004-08-111-6/+2
| | | | | | | old asmprinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15660 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate 3 of the X86 printImplicit* flags.Chris Lattner2004-08-011-7/+1
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* Add support for the printImplicitDefsBefore flagChris Lattner2004-04-131-1/+3
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* Added the llvm.readport and llvm.writeport intrinsics for x86. These doJohn Criswell2004-04-081-6/+20
| | | | | | | | | | | | | I/O port instructions on x86. The specific code sequence is tailored to the parameters and return value of the intrinsic call. Added the ability for implicit defintions to be printed in the Instruction Printer. Added the ability for RawFrm instruction to print implict uses and defintions with correct comma output. This required adjustment to some methods so that a leading comma would or would not be printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12782 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FP conditional move instructions, which annoyingly have special propertiesChris Lattner2004-03-311-2/+4
| | | | | | | | that require the asmwriter to be extended (printing implicit uses before the explicit operands) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12574 91177308-0d34-0410-b5e6-96231b3b80d8
* Each instruction now has both an ImmType and a MemType. This describesAlkis Evlogimenos2004-02-281-4/+4
| | | | | | | | | the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11967 91177308-0d34-0410-b5e6-96231b3b80d8
* Added LLVM copyright header.John Criswell2003-10-211-0/+7
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* Completely eliminate the isVoid TSFlag, shifting over all other fieldsChris Lattner2003-08-061-4/+4
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* There is nothing special about noops anymoreChris Lattner2003-08-041-1/+0
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* transition to using let instead of setChris Lattner2003-08-041-8/+8
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* Add new TableGen instruction definitionsChris Lattner2003-08-031-0/+11
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* Add Target class for X86 targetChris Lattner2003-08-031-0/+17
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* Initial checkin of X86.td fileChris Lattner2003-08-031-0/+17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7510 91177308-0d34-0410-b5e6-96231b3b80d8
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