| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', | Daniel Dunbar | 2010-08-12 | 1 | -1/+0 |
| * | Declare CLMUL as a subtarget feature | Bruno Cardoso Lopes | 2010-07-23 | 1 | -0/+2 |
| * | MC/X86: We now match instructions like "incl %eax" correctly for the arch we are | Daniel Dunbar | 2010-07-19 | 1 | -1/+0 |
| * | MC/X86: Add "support" for matching ATT style mnemonic prefixes. | Daniel Dunbar | 2010-05-04 | 1 | -2/+3 |
| * | Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. | Jakob Stoklund Olesen | 2010-04-05 | 1 | -27/+1 |
| * | Separate out the AES-NI instructions from the SSE4.2 instructions. Add | Eric Christopher | 2010-04-02 | 1 | -1/+9 |
| * | Nehalem unaligned memory access is fast. | Evan Cheng | 2010-04-01 | 1 | -2/+7 |
| * | Teach TableGen to understand X.Y notation in the TSFlagsFields strings. | Jakob Stoklund Olesen | 2010-03-25 | 1 | -3/+3 |
| * | Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain c... | Jakob Stoklund Olesen | 2010-03-25 | 1 | -0/+2 |
| * | MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a | Daniel Dunbar | 2010-03-18 | 1 | -0/+1 |
| * | all 64-bit cpus have cmov, this should fix CodeGen/X86/cmov.ll | Chris Lattner | 2010-03-14 | 1 | -1/+2 |
| * | revert r95949, it turns out that adding new prefixes is not a | Chris Lattner | 2010-02-12 | 1 | -3/+3 |
| * | add another bit of space for new kinds of instruction prefixes. | Chris Lattner | 2010-02-12 | 1 | -3/+3 |
| * | Implement a feature (-vector-unaligned-mem) to allow targets to | David Greene | 2010-01-11 | 1 | -0/+4 |
| * | Remove target attribute break-sse-dep. Instead, do not fold load into sse par... | Evan Cheng | 2009-12-22 | 1 | -22/+10 |
| * | On recent Intel u-arch's, folding loads into some unary SSE instructions can | Evan Cheng | 2009-12-18 | 1 | -10/+22 |
| * | Instruction fixes, added instructions, and AsmString changes in the | Sean Callanan | 2009-12-18 | 1 | -1/+1 |
| * | remove a temporary hack. | Chris Lattner | 2009-09-20 | 1 | -1/+1 |
| * | split MCInst printing out of the X86ATTInstPrinter | Chris Lattner | 2009-09-13 | 1 | -1/+1 |
| * | Add support for modeling whether or not the processor has support for | Chris Lattner | 2009-09-02 | 1 | -4/+9 |
| * | llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be | Daniel Dunbar | 2009-08-11 | 1 | -0/+6 |
| * | Match X86 register names to number. | Daniel Dunbar | 2009-07-29 | 1 | -1/+8 |
| * | Add processor descriptions for Istanbul and Shanghai. | David Greene | 2009-06-29 | 1 | -0/+4 |
| * | Add feature flags for AVX and FMA and fix some SSE4A feature flag | David Greene | 2009-06-26 | 1 | -0/+10 |
| * | Revert 72707 and 72709, for the moment. | Dale Johannesen | 2009-06-02 | 1 | -2/+0 |
| * | Add missing file. | Dale Johannesen | 2009-06-01 | 1 | -0/+2 |
| * | Update CPU capabilities for AMD machines | Stefanus Du Toit | 2009-05-26 | 1 | -0/+12 |
| * | Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has | Dan Gohman | 2009-02-03 | 1 | -7/+13 |
| * | Add Intel processors core i7 and atom. | Evan Cheng | 2009-01-03 | 1 | -0/+2 |
| * | Do not isel load folding bt instructions for pentium m, core, core2, and AMD ... | Evan Cheng | 2009-01-02 | 1 | -16/+18 |
| * | Move target independent td files from lib/Target/ to include/llvm/Target so t... | Evan Cheng | 2008-11-24 | 1 | -1/+1 |
| * | Accept -march=i586, because gcc does (a synonym | Dale Johannesen | 2008-10-14 | 1 | -0/+1 |
| * | Add ability to override segment (mostly for code emitter purposes). | Anton Korobeynikov | 2008-10-11 | 1 | -0/+2 |
| * | Add lock prefix support to x86. Also add the instructions necessary for the ... | Andrew Lenharth | 2008-03-01 | 1 | -0/+2 |
| * | nocona, core2 and penryn support 64 bit. | Dale Johannesen | 2008-02-15 | 1 | -3/+3 |
| * | SSE 4.1 Intrinsics and detection | Nate Begeman | 2008-02-03 | 1 | -0/+7 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+2 |
| * | Corrected many typing errors. And removed 'nest' parameter handling | Arnold Schwaighofer | 2007-10-12 | 1 | -1/+1 |
| * | We only need to specify the most-implied feature for an architecture. | Bill Wendling | 2007-05-22 | 1 | -33/+21 |
| * | 3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. | Bill Wendling | 2007-05-06 | 1 | -3/+5 |
| * | Add an "implies" field to features. This indicates that, if the current | Bill Wendling | 2007-05-04 | 1 | -17/+21 |
| * | Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers | Bill Wendling | 2007-04-25 | 1 | -1/+1 |
| * | Add support for our first SSSE3 instruction "pmulhrsw". | Bill Wendling | 2007-04-10 | 1 | -0/+2 |
| * | Add a description of the X86-64 calling convention and the return | Chris Lattner | 2007-02-26 | 1 | -0/+11 |
| * | Still need to support -mcpu=<> or cross compilation will fail. Doh. | Evan Cheng | 2006-10-06 | 1 | -0/+73 |
| * | Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3,... | Evan Cheng | 2006-10-06 | 1 | -73/+0 |
| * | Committing X86-64 support. | Evan Cheng | 2006-09-08 | 1 | -4/+10 |
| * | ImmMask should be 3 for a two-bit field; Compact X86II | Evan Cheng | 2006-05-18 | 1 | -1/+1 |
| * | getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. | Evan Cheng | 2006-05-18 | 1 | -3/+0 |
| * | Remove PointerType from class Target | Evan Cheng | 2006-05-17 | 1 | -3/+0 |
