| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN'... | Evan Cheng | 2010-01-31 | 1 | -1/+1 |
| * | Mark EH_RETURN64 as CodeGenOnly. | Daniel Dunbar | 2010-01-22 | 1 | -1/+1 |
| * | Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add pat... | Evan Cheng | 2010-01-12 | 1 | -3/+5 |
| * | Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. | Dan Gohman | 2010-01-12 | 1 | -9/+13 |
| * | Extend r93152 to work on OR r, r. If the source set bits are known not to ove... | Evan Cheng | 2010-01-11 | 1 | -2/+5 |
| * | Revert 93158. It's breaking quite a few x86_64 tests. | Evan Cheng | 2010-01-11 | 1 | -11/+8 |
| * | Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it | Dan Gohman | 2010-01-11 | 1 | -0/+11 |
| * | Re-instate MOV64r0 and MOV16r0, with adjustments to work with the | Dan Gohman | 2010-01-11 | 1 | -8/+11 |
| * | Pattern top-level operators don't need to be restricted to a | Dan Gohman | 2010-01-11 | 1 | -1/+1 |
| * | Select an OR with immediate as an ADD if the input bits are known zero. This ... | Evan Cheng | 2010-01-11 | 1 | -4/+12 |
| * | Fix what looks to me obvious instruction definition bugs. | Evan Cheng | 2010-01-08 | 1 | -0/+1 |
| * | Perform this folding as a target specific dag combine: | Evan Cheng | 2010-01-04 | 1 | -36/+1 |
| * | Instruction fixes, added instructions, and AsmString changes in the | Sean Callanan | 2009-12-18 | 1 | -117/+325 |
| * | Re-enable 91381 with fixes. | Evan Cheng | 2009-12-16 | 1 | -2/+2 |
| * | Fix an encoding bug. | Evan Cheng | 2009-12-15 | 1 | -1/+1 |
| * | Use sbb x, x to materialize carry bit in a GPR. The result is all one's or al... | Evan Cheng | 2009-12-15 | 1 | -0/+9 |
| * | Fix a minor inconsistency. | Dan Gohman | 2009-11-30 | 1 | -1/+1 |
| * | MOV64rm should be marked isReMaterializable. | Evan Cheng | 2009-11-17 | 1 | -1/+1 |
| * | Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this wo... | Anton Korobeynikov | 2009-11-02 | 1 | -10/+10 |
| * | Initial x86 support for BlockAddresses. | Dan Gohman | 2009-10-30 | 1 | -0/+9 |
| * | Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a | Dan Gohman | 2009-10-29 | 1 | -1/+1 |
| * | remove strings from instructions who are never asmprinted. | Chris Lattner | 2009-10-19 | 1 | -14/+7 |
| * | Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. | Torok Edwin | 2009-10-19 | 1 | -1/+2 |
| * | Add support for using the FLAGS result of or, xor, and and instructions | Dan Gohman | 2009-09-18 | 1 | -0/+96 |
| * | Added RCL and RCR (rotate left and right with a | Sean Callanan | 2009-09-18 | 1 | -0/+33 |
| * | Added the LODS (load byte into register, usually | Sean Callanan | 2009-09-16 | 1 | -0/+4 |
| * | Added the LAR (load segment access rights) | Sean Callanan | 2009-09-16 | 1 | -0/+8 |
| * | Added an alternate form of register-register CMP | Sean Callanan | 2009-09-16 | 1 | -0/+2 |
| * | Added the definitions for one-bit left shifts to | Sean Callanan | 2009-09-16 | 1 | -2/+4 |
| * | Updated comments per Eli's suggestion. | Sean Callanan | 2009-09-15 | 1 | -1/+2 |
| * | Added register-to-register ADD instructions to the | Sean Callanan | 2009-09-15 | 1 | -0/+5 |
| * | Added a new register class for segment registers | Sean Callanan | 2009-09-15 | 1 | -0/+10 |
| * | On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of | Dan Gohman | 2009-09-15 | 1 | -3/+5 |
| * | Added CMPS (string comparison) instructions for all | Sean Callanan | 2009-09-12 | 1 | -0/+2 |
| * | Added SCAS instructions in their 8, 16, 32, and | Sean Callanan | 2009-09-12 | 1 | -0/+2 |
| * | Added ADC, SUB, SBB, and OR instructions that operate | Sean Callanan | 2009-09-11 | 1 | -0/+13 |
| * | Added XOR instructions for rAX and immediates of | Sean Callanan | 2009-09-10 | 1 | -0/+4 |
| * | Added MOV instructions between rAX and memory offsets, | Sean Callanan | 2009-09-10 | 1 | -0/+9 |
| * | Added a variety of PUSH and POP instructions, including | Sean Callanan | 2009-09-10 | 1 | -2/+8 |
| * | Add a -disable-16bit flag and associated support for experimenting with | Dan Gohman | 2009-09-03 | 1 | -0/+12 |
| * | Added opaque 32-, 48-, and 80-bit memory operand types to the X86 | Sean Callanan | 2009-09-03 | 1 | -0/+5 |
| * | Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. | Sean Callanan | 2009-09-02 | 1 | -0/+10 |
| * | Added TEST %rAX, $imm instructions to the Intel tables. These are required f... | Sean Callanan | 2009-09-01 | 1 | -0/+2 |
| * | Don't use INSERT_SUBREG to model anyext operations on x86-64, as it | Dan Gohman | 2009-08-26 | 1 | -23/+20 |
| * | X86/AsmParser: Mark MOV64GSrm, MOV64FSrm, GS_MOV32rm, FS_MOV32rm as codegen o... | Daniel Dunbar | 2009-08-11 | 1 | -2/+2 |
| * | move some 32-bit instrs to x86instrinfo.td | Chris Lattner | 2009-08-11 | 1 | -8/+0 |
| * | llvm-mc/AsmParser: Disambiguate i64i8imm. | Daniel Dunbar | 2009-08-10 | 1 | -1/+3 |
| * | llvm-mc/AsmMatcher: Change assembler parser match classes to their own record | Daniel Dunbar | 2009-08-10 | 1 | -2/+2 |
| * | Extend comment on ParserMatchClass .td field, and add some missing | Daniel Dunbar | 2009-08-09 | 1 | -0/+2 |
| * | Do not generate 32-bit call on win64 when imm does not fit | Anton Korobeynikov | 2009-08-07 | 1 | -2/+2 |
