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path: root/lib/Target/X86/X86InstrInfo.cpp
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* Add MI-Sched support for x86 macro fusion.Andrew Trick2013-06-231-0/+161
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-161-13/+0
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-101-49/+163
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-110/+33
* TMP: LEA64_32r fixingTim Northover2013-06-011-33/+110
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-301-50/+15
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-301-10/+1
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-1/+1
* X86: Remove test instructions proceeding shift by immediate instructionsDavid Majnemer2013-05-221-17/+53
* X86: Bad peephole interaction between adc, MOV32r0David Majnemer2013-05-181-3/+18
* X86: Remove redundant test instructionsDavid Majnemer2013-05-151-7/+39
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-5/+3
* This patch follows is a follow up to r178171, which uses the register Preston Gurd2013-03-271-0/+9
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-301-4/+4
* Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to tar...Craig Topper2012-12-291-15/+0
* Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/mi...Craig Topper2012-12-291-20/+0
* Remove alignment from a bunch more VEX encoded operations in the folding tables.Craig Topper2012-12-261-47/+47
* Remove alignment from folding table for VMOVUPD as an unaligned instruction i...Craig Topper2012-12-261-1/+1
* Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit...Craig Topper2012-12-261-2/+2
* Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171...Craig Topper2012-12-261-2/+2
* VCVTSS2SD requires a strict alignment. Thanks Elena.Nadav Rotem2012-12-251-2/+2
* Some x86 instructions can load/store one of the operands to memory. On SSE, t...Nadav Rotem2012-12-241-260/+260
* In some cases, due to scheduling constraints we copy the EFLAGS.Nadav Rotem2012-12-211-0/+2
* X86: Match the SSE/AVX min/max vector ops using a custom node instead of intr...Benjamin Kramer2012-12-211-0/+24
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-191-18/+21
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling2012-12-191-2/+2
* Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also add...Craig Topper2012-12-171-0/+2
* Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and...Craig Topper2012-12-171-1/+26
* Remove store forms of DEC/INC from isDefConvertible. Since they are stores th...Craig Topper2012-12-171-6/+2
* Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as ne...Craig Topper2012-12-061-0/+3
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-3/+3
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-3/+3
* X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren2012-11-271-0/+15
* Remove alignments from folding tables for scalar FMA4 instructions.Craig Topper2012-11-041-16/+16
* Add scalar forms of FMA4 VFNMSUB/VFNMADD to folding tables. Patch from Camero...Craig Topper2012-10-311-0/+8
* Create enums for the different attributes.Bill Wendling2012-10-091-2/+4
* Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos...Craig Topper2012-10-051-0/+8
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. S...Sylvestre Ledru2012-09-271-1/+1
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-271-1/+1
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-2/+2
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-261-0/+6
* Add RORX code generation supportMichael Liao2012-09-261-0/+4
* Add MULX code generation supportMichael Liao2012-09-261-0/+4
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-201-2/+2
* Add some cases to x86 OptimizeCompare to handle DEC and INC, too.Jan Wen Voung2012-09-171-4/+14
* Mark FMA4 instructions as commutable and add them to the folding tables.Craig Topper2012-08-311-0/+60
* Add selection of RegOp2MemOpTable3 to canFoldMemoryOperandCraig Topper2012-08-311-0/+2
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-281-4/+5
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