| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add shift and rotate by 1 instructions / patterns. | Evan Cheng | 2006-06-29 | 1 | -0/+15 |
| * | Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobey... | Evan Cheng | 2006-06-13 | 1 | -4/+21 |
| * | Added X86FunctionInfo subclass of MachineFunction to record whether the | Evan Cheng | 2006-06-06 | 1 | -7/+3 |
| * | Cygwin support. Patch by Anton Korobeynikov! | Evan Cheng | 2006-06-02 | 1 | -2/+21 |
| * | Rename instructions for consistency sake. | Evan Cheng | 2006-05-31 | 1 | -10/+20 |
| * | getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. | Evan Cheng | 2006-05-18 | 1 | -0/+16 |
| * | X86 integer register classes naming changes. Make them consistent with FP, ve... | Evan Cheng | 2006-05-16 | 1 | -15/+15 |
| * | More coverity fixes | Chris Lattner | 2006-05-12 | 1 | -1/+0 |
| * | Fixing truncate. Previously we were emitting truncate from r16 to r8 as | Evan Cheng | 2006-05-08 | 1 | -6/+18 |
| * | Better implementation of truncate. ISel matches it to a pseudo instruction | Evan Cheng | 2006-05-05 | 1 | -0/+76 |
| * | Remove and simplify some more machineinstr/machineoperand stuff. | Chris Lattner | 2006-05-04 | 1 | -9/+9 |
| * | Move some methods out of MachineInstr into MachineOperand | Chris Lattner | 2006-05-04 | 1 | -2/+2 |
| * | There shalt be only one "immediate" operand type! | Chris Lattner | 2006-05-04 | 1 | -1/+1 |
| * | Remove a bunch more SparcV9 specific stuff | Chris Lattner | 2006-05-04 | 1 | -1/+1 |
| * | Use movaps instead of movapd for spill / restore. | Evan Cheng | 2006-04-28 | 1 | -2/+2 |
| * | MakeMIInst() should handle jump table index operands. | Evan Cheng | 2006-04-24 | 1 | -0/+3 |
| * | - PEXTRW cannot take a memory location as its first source operand. | Evan Cheng | 2006-04-18 | 1 | -2/+1 |
| * | SHUFP{S|D}, PSHUF* encoding bugs. Left out the mask immediate operand. | Evan Cheng | 2006-04-18 | 1 | -5/+5 |
| * | Encoding bug: CMPPSrmi, CMPPDrmi dropped operand 2 (condtion immediate). | Evan Cheng | 2006-04-18 | 1 | -2/+2 |
| * | Incorrect foldMemoryOperand entries | Evan Cheng | 2006-04-17 | 1 | -12/+6 |
| * | Can't fold loads into alias vector SSE ops used for scalar operation. The load | Evan Cheng | 2006-04-16 | 1 | -8/+0 |
| * | Added SSE (and other) entries to foldMemoryOperand(). | Evan Cheng | 2006-04-14 | 1 | -19/+155 |
| * | We were not adjusting the frame size to ensure proper alignment when alloca / | Evan Cheng | 2006-04-14 | 1 | -30/+23 |
| * | Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available ... | Evan Cheng | 2006-04-10 | 1 | -1/+1 |
| * | Foundation for call frame information. | Jim Laskey | 2006-04-07 | 1 | -1/+5 |
| * | Minor fixes + naming changes. | Evan Cheng | 2006-04-04 | 1 | -2/+2 |
| * | Expose base register for DwarfWriter. Refactor code accordingly. | Jim Laskey | 2006-03-28 | 1 | -9/+2 |
| * | Translate llvm target registers to dwarf register numbers properly. | Jim Laskey | 2006-03-27 | 1 | -1/+1 |
| * | Add support to locate local variables in frames (early version.) | Jim Laskey | 2006-03-23 | 1 | -0/+12 |
| * | Use the generic vector register classes VR64 / VR128 rather than V4F32, | Evan Cheng | 2006-03-18 | 1 | -9/+3 |
| * | Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. | Evan Cheng | 2006-03-17 | 1 | -0/+9 |
| * | Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. | Evan Cheng | 2006-03-17 | 1 | -6/+18 |
| * | Fix an obvious bug exposed when we are doing | Evan Cheng | 2006-02-25 | 1 | -1/+2 |
| * | Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64. | Evan Cheng | 2006-02-21 | 1 | -2/+6 |
| * | Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit | Evan Cheng | 2006-02-20 | 1 | -6/+6 |
| * | 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This | Evan Cheng | 2006-02-16 | 1 | -2/+8 |
| * | Use movaps / movapd to spill / restore V4F4 / V2F8 registers. | Evan Cheng | 2006-02-16 | 1 | -4/+12 |
| * | Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg | Evan Cheng | 2006-02-16 | 1 | -2/+2 |
| * | When rewriting frame instructions, emit the appropriate small-immediate | Chris Lattner | 2006-02-03 | 1 | -13/+21 |
| * | Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ... | Chris Lattner | 2006-02-02 | 1 | -46/+0 |
| * | implement isStoreToStackSlot | Chris Lattner | 2006-02-02 | 1 | -0/+23 |
| * | Added SSE entries to foldMemoryOperand(). | Evan Cheng | 2006-02-01 | 1 | -1/+49 |
| * | Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. | Evan Cheng | 2006-01-09 | 1 | -2/+0 |
| * | * Fast call support. | Evan Cheng | 2006-01-06 | 1 | -1/+2 |
| * | Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass. | Evan Cheng | 2005-12-24 | 1 | -6/+6 |
| * | * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. | Evan Cheng | 2005-12-23 | 1 | -0/+1 |
| * | Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns | Chris Lattner | 2005-12-21 | 1 | -4/+3 |
| * | Properly split f32 and f64 into separate register classes for scalar sse fp | Nate Begeman | 2005-10-14 | 1 | -5/+11 |
| * | simplify this code using the new regclass info passed in | Chris Lattner | 2005-09-30 | 1 | -29/+45 |
| * | Pass extra regclasses into spilling code | Chris Lattner | 2005-09-30 | 1 | -2/+4 |
